KR20020088032A - System having back plane in which a plurality of units are installed - Google Patents

Abstract

PURPOSE: A system having a back plane embedding with the plural units is provided to process the data freely and to implement the continuous data processing because the units output the data according to an arbitration result generated by not depending on a master chip. CONSTITUTION: The system includes the back plane having a data bus and a plurality of units sharing the data bus by installing to the back plane. Each unit(U1) includes a serial arbitration processor(421) deciding that the unit transmits the data to the data bus, and a data processor(411) storing the data received from the back plane and transmitting the stored data to the data bus by responding to the output of the serial arbitration processor. The serial arbitration processor and the data processor are operated by synchronizing with a frame signal and a clock signal inputted from the back plane and carry out the data communication with the back plane through the buffers(431-434).

Description

System having back plane in which a plurality of units are installed}

The present invention relates to a communication system, and more particularly to a system having a backplane equipped with a plurality of units.

The system typically has multiple units on the backplane. The backplane enables data communication between units mounted in slots formed on the backplane through a common system bus, and also enables data communication with backplanes of other external systems via cables. Device.

A conventional back plane is equipped with a plurality of units 101 to 104, as shown in FIG. The units 101 to 104 each include one of a master chip 111 and slave chips 112 to 114, respectively. The master chip 111 performs data communication with the slave chips 112 to 114 through the data bus 121.

When there are data to be transmitted to the data bus 121, the slave chips 111 to 114 first send a signal RQ to the master chip 111 to request permission. Then, when the permission signal GR is received from the master chip 111, the slave chips 112 to 114 transmit data to the data bus 121. At this time, the slave chip that receives the permission signal GR from the master chip 111 transmits data to the data bus 121, but the slave chip that does not receive the permission signal GR transmits data to the data bus 121. It is not able to transmit to the server and remains in the standby state.

As such, a system having a conventional backplane has the following problems.

First, when the slave chips 112 to 114 have data to be transmitted to the data bus 121, the data is not transmitted to the data bus 121 until the slave chip 112 to 114 receives the permission signal GR from the master chip 111. can not do it.

Second, even when continuous data is input to the slave chips 112 to 114, the slave chips 112 to 114 must exchange signals with the master chip 111, so the slave chips 112 to 114 are continuously connected. It is not possible to transfer data to the data bus 121.

Third, if the master chip 111 malfunctions, the slave chips 112 to 114 do not transmit the data bus 121 data, thereby causing the entire system to operate abnormally.

As described above, the conventional slave chips 112 to 114 are all instructed by the master chip 111 to perform data communication, and the dependency on the master chip 111 is too high to be efficient. If one chip 111 malfunctions, there is an irrationality that the whole system operates abnormally.

SUMMARY OF THE INVENTION The present invention has been made in an effort to solve the above problems, and to provide a system having a backplane equipped with units for transmitting data through abitation between units without depending on a master chip.

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

FIG. 1 is a diagram illustrating a method in which a plurality of units mounted on a conventional back plane communicate with each other.

2 is a diagram illustrating a system having a back plane according to the present invention.

3 is a diagram illustrating a state in which the units illustrated in FIG. 2 are electrically connected.

4 is a block diagram of one of the units shown in FIG.

FIG. 5 is a block diagram of the serial ablation processing unit shown in FIG. 4.

FIG. 6 is a timing diagram of signals when the serial ablation processing unit shown in FIG. 5 is win.

FIG. 7 is a timing diagram of signals for explaining a method of capturing arbitration data when the serial ablation processing unit illustrated in FIG. 5 is win.

FIG. 8 is a timing diagram of signals when the serial bit processing unit illustrated in FIG. 5 is a loser.

FIG. 9 is a timing diagram of signals for explaining a method of capturing arbitration data when the serial arbitration processing unit illustrated in FIG. 5 is a loser.

The present invention to achieve the above technical problem,

Backplane with data bus installed; And a plurality of units mounted on the backplane and sharing the data bus,

Wherein each unit comprises a serial ablation processing unit for determining whether to send data to the data bus; And a data processor which receives and stores data from the backplane and transmits the stored data to the data bus in response to the output of the serial ablation processor. .

Preferably, the serial ablation processing unit and the data processing unit operate in synchronization with a frame signal and a clock signal input from the backplane.

Preferably, the serial ablation processing unit and the data processing unit perform data communication with the backplane through buffers.

Preferably, the serial ablation processing unit includes a frame timing generation unit for inputting a frame signal from the backplane, and setting and outputting an ablation period for performing serial ablation; An ablation control unit connected to the data processing unit and the frame timing generation unit and generating an ablation start signal in response to an ablation period signal output from the frame timing generation unit when a signal indicating that there is stored data is received from the data processing unit. ; A priority generator for receiving a slot signal from the backplane and outputting the arbitration data configured by adding an internal priority to the slot signal; A conversion unit which receives the arbitration data from the priority generation unit and converts the arbitration data from parallel to serial in response to an output of the frame timing generator and an output of the arbitration control unit; And compares the ablation data output from the converter and the ablation data output from the converter in response to the comparison start signal output from the frame timing generator, and wired and wired on the backplane. The comparison unit generates a win signal and transmits the win signal to the data processor when the priority is high.

Preferably, the arbitration controller does not generate the arbitration start signal when it receives a signal indicating that there is no stored data from the data processor.

Preferably, the priority generation unit is connected to the comparison unit, and when the win signal is generated in the comparison unit, the internal priority is decreased by one to provide another unit with a chance of wining.

Preferably, the comparator does not generate a win signal when the comparison result has a low priority and informs the arbitation controller so that the data processor does not transmit the stored data to the backplane. .

According to the present invention, each unit can process its own data.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

FIG. 2 is a diagram illustrating a system having a backplane according to the present invention, and FIG. 3 is a diagram illustrating a state in which the units illustrated in FIG. 2 are electrically connected. 2 and 3, a plurality of units U1 to U14 are mounted to the backplane 211 of the system.

The backplane 211 is provided with a data bus 311 for transmitting data to the units U1 to U14 or for transferring data output from the units U1 to U14 to the outside.

The units U1 to U14 receive a frame signal and a clock signal through the backplane 211. The units U1 to U14 also output the ablation data generated on the backplane 211, which is wired AND at the backplane 211 and inputs back to the unit. do.

FIG. 4 is a block diagram of one unit U1 of the units U1 to U14 shown in FIG. 2. Referring to FIG. 4, the unit U1 includes a data processor 411, a serial ablation processor 421, and buffers 431 to 434.

The serial ablation processing unit 421 determines whether the unit U1 transmits data to the data bus 311. The serial ablation processing unit 421 will be described in more detail with reference to FIG. 5.

The data processor 411 receives and stores data from the backplane 211, and transmits the stored data to the data bus 311 in response to the output of the serial ablation processor 421.

The serial ablation processing unit 421 and the data processing unit 411 operate in synchronization with the frame signal FR and the clock signal CLK input from the backplane 211.

The buffers 431 to 434 buffer data (Data) and signals (FR, CLK, AI, AO, Slot_ID) input and output to the serial ablation processing unit 421 and the data processing unit 411. For example, the buffers 431434 may set the voltage levels of the data Data and the signals FR, CLK, AI, AO, Slot_ID, which are input from the backplane 211, to the data processing unit 411 and the serial ablation processing unit ( 421 converts the voltage levels into the appropriate voltage levels, and externally converts the voltage levels of the data and signals FR, CLK, AI, AO, Slot_ID outputted from the data processor 411 and the serial ablation processor 421. The outputs are converted to voltage levels suitable for the system or the voltage driving capability is enhanced.

5 is a block diagram of the serial ablation processing unit 421 shown in FIG. 4. Referring to FIG. 5, the serial ablation processor 421 includes a frame timing generator 511, an arbitration controller 541, a priority generator 531, a converter 521, and a comparator 551. do.

The frame timing generator 511 inputs the frame signal FR from the backplane 211 and sets an ablation period for performing serial ablation to the arbitration controller 541 and the converter 521. to provide. The serial ablation processing unit 421 performs ablation within the ablation period. The frame timing generator 511 also generates a comparison start signal COMPPST and provides it to the comparator 551.

The arbitration controller 541 is connected to the data processor 411 of FIG. 4 and the frame timing generator 511. When the arbitration control unit 541 receives a signal indicating that there is stored data from the data processing unit 411, the arbitration control unit 541 generates an arbitration start signal Compete in response to the arbitration interval signals F que to FRnn. When the arbitration control unit 541 receives a signal indicating that there is no stored data from the data processing unit 411, the arbitration control unit 541 does not generate the arbitration start signal Compete. When the win is not winned, the arbitration control unit 541 repeatedly transmits an ablation start signal Compete to the converter 521 until win is performed during the bit period.

The priority generation unit 531 receives the slot signal Slot_ID or the priority from the backplane 211, and outputs the arbitration data cn formed by adding up the internal priority. For example, if there are 32 units (in this case, the slot signal Slot_ID can be configured with 5 bits) and the internal priority is 3 bits, the ablation data cn is 8 bits. At this time, the ablation data cn is provided to the converter 521 in parallel. The priority generation unit 531 is connected to the comparison unit 551, and when the win signal WIN is generated in the comparison unit 551, the internal priority is decreased by one to provide another unit with a chance of wining.

The converter 521 receives the arbitration data cn from the priority generator 531, and responds to the output of the frame timing generator 511 and the output of the arbitration controller 541. ) Is converted from parallel to serial output.

The comparator 551 is output from the arbitration data AO transmitted from the converter 521 and the converter 521 in response to the comparison start signal COMPPST output from the frame timing generator 511. If the priority is high by comparing the wired-ended arbitration data AI at the in 211, a win signal WIN is generated and transmitted to the data processor 411 of FIG. 4. The comparison unit 551 does not generate the win signal WIN when the comparison result has a low priority, and informs the arbitation control unit 541 of the result so that the data processing unit 411 sends the stored data to the backplane. 211).

FIG. 6 is a timing diagram of signals when the serial ablation processing unit 421 shown in FIG. 5 is win. An operation of the data processor 411 and the serial ablation processor 421 shown in FIGS. 4 and 5 will be described with reference to FIG. 6.

In accordance with the clock signal CLK, the frame signal FR is enabled at a logic high, and a signal CAV indicating that data is stored in the data processing unit 411 is a serial ablation processing unit ( When input to 421, the frame timing generator 511 generates frame period signals FR15 and FR23 indicating a frame period. The count signal CNT is a signal for counting frames of the frame signal FR. Then, the arbitration control unit 541 generates the arbitration start signal Compete to cause the conversion unit 521 to start the arbitration. Subsequently, the comparison unit 551 wires the arbitration data AO output from the converter 521 in response to the comparison start signal COMPPST output from the frame timing generation unit 511. ) To perform the operation.

FIG. 7 is a timing diagram of signals for explaining a method of capturing the ablation data cn when the serial ablation processing unit 421 shown in FIG. 5 is win. As shown in FIG. 7, when the arbitration data cn is 8 bits, for example, the comparator 551 compares the arbitration data cn for each bit, and the result is represented by the signals CAP0 to CAP7. Lose. When all bits are wins, the win signal WIN is finally active at a logic high, and the trigger signal TRGTX is active at a logic high, and the internal priority of the priority generator 531 is decreased by one.

FIG. 8 is a timing diagram of signals when the serial bit processing unit 421 shown in FIG. 5 is a loser, and FIG. 9 is a bit liner when the serial bit processing unit 421 shown in FIG. 5 is a loser. In this case, it is a timing diagram of signals for explaining a method of capturing ablation data cn.

8 and 9, when the comparison result is a loser, as the serial win signal SWIN is disabled to a logic low in the lost bit, the capture signal CAP4 of the corresponding bit is also logic low. Is disabled. As a result, the win signal WIN is disabled to a logic low, and the loser signal LOSER is activated to a logic high to inform the data processor 411 of the fact. In the case of a loser, the internal priority of the priority generator 531 is not reduced.

The best embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, according to the present invention, since the units U1 to U14 output data according to the result of arbitration generated therein without depending on the master chip 111 of FIG. In particular, continuous data processing is possible. In addition, even if one unit fails, the other unit can process data independently without being affected by it at all. In addition, even if the number of units increases, the units U1 to U14 are free to process data regardless of the number.

Claims (7)

Backplane with data bus installed; And A plurality of units mounted on the backplane and sharing the data bus, Each unit is A serial ablation processing unit which determines whether or not the unit transmits data to the data bus; And And a data processor for receiving and storing data from the backplane and transmitting the stored data to the data bus in response to an output of the serial ablation processor. The system of claim 1, wherein the serial ablation processing unit and the data processing unit operate in synchronization with a frame signal and a clock signal input from the back plane. The system of claim 1, wherein the serial ablation processing unit and the data processing unit perform data communication with the back plane through buffers. The method of claim 1, wherein the serial ablation processing unit A frame timing generator for inputting a frame signal from the backplane and setting and outputting an ablation section for performing serial ablation; An ablation control unit connected to the data processing unit and the frame timing generation unit and generating an ablation start signal in response to an ablation period signal output from the frame timing generation unit when a signal indicating that there is stored data is received from the data processing unit. ; A priority generator for receiving a slot signal from the backplane and outputting the arbitration data configured by adding an internal priority to the slot signal; A conversion unit which receives the arbitration data from the priority generation unit and converts the arbitration data from parallel to serial in response to an output of the frame timing generator and an output of the arbitration control unit; And In response to the comparison start signal output from the frame timing generator, the comparison data outputted from the conversion unit and the conversion data wired and output from the conversion unit are compared with each other. And a comparator for generating a win signal and transmitting the win signal to the data processor when the rank is high. 5. The system of claim 4, wherein the arbitration controller does not generate the arbitration start signal when it receives a signal indicating that there is no stored data from the data processor. The backplate according to claim 4, wherein the priority generating unit is connected to the comparing unit, and when the win signal is generated in the comparing unit, the internal priority is decreased by one to provide another unit with a win opportunity. System with phosphorus. The method of claim 4, wherein the comparison unit does not generate a win signal when the comparison result has a low priority, and notifies the arbitration control unit of the result so that the data processing unit does not transmit the stored data to the backplane. And a back plane.