KR20040108055A - a bus system having serial/parallel circuitry - Google Patents

Abstract

PURPOSE: A bus system equipped with circuit serializing/paralleling data of a master/slave device is provided to transfer each data by using only one 1-bit bus line irrespective of a bit number of each data, and synchronize the transfer of each data with a strobe signal shorter than a cycle of a system clock in order to resolve time delay in case of serial data transfer through one 1-bit bus line. CONSTITUTION: The master device(100) includes the first parallel operation circuit(101) performing a basic function of the master device, and an operative instruction data serializing circuit(104) converting the parallel data transferred from the first parallel operation circuit into the serial data and transmitting it to the slave device(110). The slave device includes the second parallel operation circuit(111) performing the basic function of the slave device, and an operative instruction data paralleling circuit(114) converting the serial data transferred from the operative instruction data serializing circuit into the parallel data and transmitting it to the second paralleling operation device.

Description

Bus system having serial / parallel circuitry

The present invention relates to a bus system, and more particularly, to convert each parallel data transmitted from a parallel operation circuit of a master device / slave device into serial data, and to transmit each converted serial data, respectively, each of which is a 1-bit bus line. Only one bus system is used.

1 is a block diagram showing the structure of a conventional bus system.

In general, the bus system includes one or more master devices (11, 12), one or more slave devices (21, 22), an arbiter (40), a decoder (50), and one or more multiplexers (31, 32, 33). 34, 35, and consist of buses connecting them. Each bus is provided with one or more 1-bit bus lines, and each 1-bit bus line transmits data one bit at a time.

The master devices 11, 12 are generally processors or direct memory access (DMA) controllers, and the slave devices 21, 22 are generally memory, input / output devices, or other peripherals such as RAM, ROM, SDRAM, RDRAM, or the like. Can be.

The master devices 11 and 12 perform a write operation of writing predetermined data to a corresponding address of the slave device, and a read operation of reading predetermined data stored at the corresponding address of the slave device. Connected buses are used to perform write and read operations. In the present specification, the target data of the write operation is referred to as 'write data', and the target data of the read operation is referred to as 'read data'.

The master devices 11 and 12 transmit a bus use request signal to the arbiter 40. When a bus use request signal is received from one or more master devices 11 and 12, the arbiter 40 determines the master device having the highest priority among the master devices 11 and 12. Then, the bus permission signal is transmitted to the determined master device. Then, the master device receiving the bus permission signal has a right to use the bus and transmits each data using it. The decoder 50 receives address data from the master device. The slave device corresponding to the address data among the plurality of slave devices is determined. That is, when a plurality of slave devices 21 and 22 are connected to the bus, the decoder 50 receives address data from the master device granted the bus use right and determines the slave device based on the received address data. The decoder 50 outputs a selection signal to the determined slave device. Upon receiving the selection signal, the slave device transmits and receives each data with the master device entitled to the bus. In the present specification, the master device granted the bus use right is referred to as the 'master device', and the slave device selected by the decoder is referred to as 'the slave device'.

The master device transmits address data, write data, and operation command data to the slave device. The controller receives read data and operation response data from the slave device.

The slave device receives address data, write data, and operation command data from the master device. The read data and operation response data are transmitted to the master device.

In addition, the multiplexers 31, 32, 33, 34, 35 output only data selected from the master device determined under the control of the arbiter 40 and the decoder 50 or input to the master device. Be sure to The first multiplexer 31 receives the address data and outputs only the address data from the corresponding master device. The second multiplexer 32 corresponds to the operation command data, the third multiplexer 33 corresponds to the write data, the fourth multiplexer 34 corresponds to the read data, and the fifth multiplexer 35 corresponds to the operation response data. It works the same as the multiplexer 31. Of course, a multiplexer is not necessary for a bus system.

In order for the master device to perform a write operation, the master device transmits predetermined data toward the slave device. The slave device receives the predetermined data through the control of the multiplexers 31, 32, and 33. The predetermined data includes write data, operation command data, and address data. For convenience of explanation, the number of bits of the write data is indicated by #WD, the operation command data by #CD, and the address data by #AD.

In order for the master device to perform a read operation, the master device transmits predetermined data toward the slave device. Here, the predetermined data includes operation command data and address data. The slave device receiving the predetermined data transmits the predetermined data toward the corresponding master device. Here, the predetermined data includes read data and operation response data. For the convenience of explanation, the number of bits of read data is denoted by #RD and the number of bits of operation response data is denoted by #RE.

Conventionally, when transmitting data, it is transmitted in the form of parallel data. Therefore, a bus having a 1-bit bus line of more than the number of bits of each data is used for this. For example, when the address data is transmitted from the master device to the first multiplexer, since the number of bits of the address data is #AD, at least #AD bus lines should be provided on the bus to transmit the address data.

As technology advances, there is a tendency to have a large number of master devices and a plurality of slave devices in a microprocessor, thereby increasing the complexity of the bus connecting these devices. In addition, as described above, since each bus must have more than one bit bus lines corresponding to the number of bits of data to be transmitted, the complexity thereof is further increased.

Therefore, in order to reduce such complexity, a method of limiting the number of master devices or slave devices may be considered, but in this case, there is a problem that the function of the microprocessor is limited. In addition, when the line width of the wiring is narrowed in the semiconductor process for the complex bus system as described above, there is a problem that the microprocessor malfunctions due to the interference between the wirings.

SUMMARY OF THE INVENTION An object of the present invention for solving the above problems is to include a serialization / parallelization circuit for serializing / parallelizing each data in a master device and a slave device, and having only one 1-bit busline as a bus regardless of the number of bits of each data. It is to provide a bus system that can transmit each data even if it is.

It is still another object of the present invention to solve the delay of data transfer time that occurs when serially transmitting each data by using one 1-bit busline, and to transmit each data in a period of the strobe signal shorter than the period of the system clock. To provide a synchronized bus system.

1 is a block diagram showing the structure of a conventional bus system;

2 is a block diagram showing an internal structure of a master device and a slave device according to a preferred embodiment of the present invention;

3 is a timing diagram showing how each data is transmitted when the bus system according to the present invention is applied;

4 is a block diagram illustrating a structure of a bus system to which a master device and a slave device according to the present invention are applied.

<Description of Symbols for Main Parts of Drawings>

100: master device 101: the first parallel operation circuit

102: address data serialization circuit 103: write data serialization circuit

104: operation command data serialization circuit 105: first strobe signal generation circuit

106: read data parallelization circuit 107: motion response data parallelization circuit

110: slave device 111: second parallel operation circuit

112: address data parallel circuit 113: write data parallel circuit

114: operation command data parallelization circuit 115: second strobe signal generation circuit

116: read data serialization circuit 117: operation response data serialization circuit

In order to achieve the above object, the bus system according to the present invention is a bus system for transmitting predetermined data through a bus having one or more 1-bit busline between one or more master devices and one or more slave devices, the master The device includes a first parallel operation circuit performing a basic function of a master device, and a first serialization circuit converting parallel data transmitted from the first parallel operation circuit into serial data and transmitting the serial data to the slave device. The slave device may include a second parallel operation circuit performing a basic function of the slave device, and a second parallel operation circuit converting the serial data transmitted from the first serialization circuit into parallel data and transmitting the same to the second parallel operation circuit. And the slave device from the first serialization circuit. Transmission of the serial data of the throw is performed via a 1-bit bus rainreul.

The slave device includes a second serialization circuit for converting the parallel data transmitted from the second parallel operation circuit into serial data and transmitting the serial data to the master device, wherein the master device includes the second serialization circuit transmitted from the second serialization circuit. And a first parallelization circuit for converting serial data into parallel data and transmitting the same to the first parallel operation circuit, wherein the transmission of the serial data from the second serialization circuit to the master device is performed through one 1-bit bus line. Is performed.

The master device includes a first strobe signal generation circuit for generating a first strobe signal for matching transmission of the serial data from the first serialization circuit to the slave device under control of the first parallel operation circuit. When the master device performs a write operation, the serial data from the first serialization circuit to the slave device is transmitted in synchronization with the first strobe signal.

The slave device includes a second strobe signal generation circuit for generating a second strobe signal for matching transmission of the serial data from the second serialization circuit to the master device under control of the second parallel operation circuit; When the master device performs a read operation, the serial data from the second serialization circuit to the master device is transmitted in synchronization with the second strobe signal.

Hereinafter, an embodiment of a bus system according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram showing the structure of a master device 100 and a slave device 110 according to a preferred embodiment of the present invention, Figure 3 illustrates that data is transmitted in synchronization with the strobe signal according to the present invention Is a timing diagram.

2, the master device 100 according to the present invention includes a first parallel operation circuit 101, an address data serialization circuit 102, a write data serialization circuit 103, an operation command data serialization circuit 104, A first strobe signal generation circuit 105, a read data parallelization circuit 106, and an operation response data parallelization circuit 107 are provided. Here, the first parallel operation circuit 101 plays the same role as the conventional master devices 11 and 12, and transmits / receives and processes each data in parallel.

In addition, the slave device 110 according to the present invention generates the second parallel operation circuit 111, the address data parallelization circuit 112, the write data parallelization circuit 113, the operation command data parallelization circuit 114, and the second strobe signal generation. A circuit 115, a read data serialization circuit 116, and an operation response data serialization circuit 117. Here, the second parallel operation circuit 111 plays the same role as the conventional slave devices 21 and 22, and transmits / receives and processes each data in parallel.

Each of the parallelization circuits 106, 107, 112, 113, and 114 receives serial data and outputs the parallel data through parallelization, and each of the serialization circuits 102, 103, 104, 116, and 117 receives the parallel data and outputs the serial data.

According to the present invention, before each data is transmitted from each device, it is first converted into serial data via a serialization circuit. Each data is received by each device, and is first converted into parallel data through a parallelization circuit before being input to the parallel operation circuit.

That is, when address data is transmitted from the address data serialization circuit 102 to the address data parallelization circuit 112, the transmission data is in serial form, and thus only one 1-bit bus line is required for the transmission of the address data. Similarly, the bus between the write data serialization circuit 103 and the write data parallelization circuit 113, the bus between the operation command data serialization circuit 104 and the operation command data parallelization circuit 114, the read data parallelization circuit 106 and the read. The bus between the data serialization circuit 116 and the bus between the operation response data parallelization circuit 107 and the operation response data serialization circuit 117 only need one 1-bit bus line.

In addition, the first and second strobe signal generation circuits 105 and 115 generate a strobe signal of a predetermined period based on control signals from the first and second parallel calculation circuits 101 and 111, respectively. The generated strobe signal is provided to each serialization circuit and parallelization circuit. Each serialization circuit and parallelization circuit synchronizes data transmitted and received to an input strobe signal.

The strobe signal is generated in the first strobe signal generation circuit 105 based on the control signal of the first parallel operation circuit 101 when the master device performs a write operation. When the read operation is performed, the second strobe signal generation circuit 115 is generated based on the control signal of the second parallel operation circuit 111.

In addition, the first and second strobe signal generation circuits 105 and 115 provided in each device are connected to each other. In the case of a write operation, the first strobe signal generated from the first strobe signal generation circuit 105 is received by the second strobe signal generation circuit 115 and based on this, the first strobe signal in the corresponding slave device operated in connection with the write operation is generated. The parallelization circuit is synchronized with the first strobe signal. In the case of the read operation, the second strobe signal generated from the second strobe signal generation circuit 115 is received by the first strobe signal generation circuit 105 and based on the read-out operation in the corresponding master device operated in connection with the read operation. The serial / parallel circuit is synchronized with the second strobe signal.

Referring to FIG. 3, the system clock refers to a clock applied to a bus system, and the strobe signal refers to a signal output from one of the first and second strobe signal generation circuits 105 and 115 according to the present invention. The transmission data means data transmitted between devices. In this embodiment, the transmission data is composed of a start signal, valid data, and an end signal. The start signal indicates the start of the corresponding transmission data, and in this embodiment, the output of the '0' signal is taken as an example, the end signal indicates the end of the transmission data, and in this embodiment, the output of the '1' signal is taken as an example. . And the valid data is the data to actually transmit.

For convenience of explanation, the transmission data is assumed to be 32-bit write data. When the write data is to be transferred from the master device 100 to the slave device 110, the first parallel operation circuit 101 of the master device 100 outputs the write data to the write data serialization circuit 103. The first parallel operation circuit 101 transmits a predetermined control signal to the first strobe signal generation circuit 105. Here, the predetermined control signal is a signal related to 32-bit write data. In this embodiment, the predetermined control signal is a control signal for generating a strobe signal oscillating at 34 cycles in one cycle of the system clock.

The first strobe signal generation circuit 105 generates a first strobe signal based on a predetermined control signal, and transmits the generated first strobe signal to the write data serialization circuit 103. The first strobe signal information is transmitted to the second strobe signal generation circuit 115 of the slave device 110 at 34 cycles. Then, the second strobe signal generation circuit 115 generates a strobe signal based on the strobe signal, and outputs the generated strobe signal to the write data parallelization circuit 113. Through this, data processing and transmission / reception in the serial / parallelization circuits 103 and 113 related to the write data are synchronized with the strobe signal oscillating at 34 cycles.

4 is a block diagram illustrating a bus system to which a master device and a slave device according to the present invention are applied.

In FIG. 1, when predetermined data are mutually transmitted between the master devices 11 and 12 and the slave devices 21 and 22, each data is transmitted in parallel. Thus, the number of 1-bit bus lines included in each bus may be used. In contrast to the number of bits required, in FIG. 4, each data is converted in serial before each data is transmitted from the master devices 100-1 and 100-2 to the slave devices 110-1 and 110-2, so that the data is transmitted to each data. For each bus, only one 1-bit busline can be transmitted. First and second master devices 100-1, 100-2, First and second slave devices 110-1, 110-2, First to fifth multiplexers 121, 122, 123, 124, 125, Arbitrators 130, and decoder 140. Since the description and the interrelationship are the same as described above, the description thereof will be omitted.

While the above has been shown and described with respect to preferred embodiments of the present invention, the present invention is not limited to the specific embodiments described above, it is usually in the technical field to which the invention belongs without departing from the spirit of the invention claimed in the claims. Various modifications can be made by those skilled in the art, and these modifications should not be individually understood from the technical spirit or the prospect of the present invention.

Conventionally, when a plurality of master devices and a plurality of slave devices are provided in a microprocessor, an excessively large number of 1-bit buslines are required in the prior art, and thus, a process of manufacturing the same is difficult. In addition, interference between wires occurs even after the manufacture of the microprocessor. There was a case of malfunction. However, according to the present invention, even if a single bit busline is provided for each data, data can be transmitted, thereby solving the conventional problem. That is, the semiconductor fabrication process may be simple and the probability of interference may be very low even after fabrication.

Claims (5)

A bus system for transmitting predetermined data through a bus provided with at least one 1-bit busline between at least one master device and at least one slave device, The master device includes a first parallel operation circuit that performs a basic function of the master device; And a first serialization circuit converting the parallel data transmitted from the first parallel operation circuit into serial data and transmitting the serial data to the slave device. The slave device may include a second parallel operation circuit that performs a basic function of the slave device; And a second parallelization circuit converting the serial data transmitted from the first serialization circuit into parallel data and transmitting the same to the second parallel operation circuit. And transfer of the serial data from the first serialization circuit to the slave device is performed via one 1-bit busline. The method of claim 1, The slave device further includes a second serialization circuit converting parallel data transmitted from the second parallel operation circuit into serial data and transmitting the same to the master device. The master device further includes a first parallelization circuit converting the serial data transmitted from the second serialization circuit into parallel data and transmitting the same to the first parallel operation circuit. And said transfer of said serial data from said second serialization circuit to said master device is performed via one one-bit busline. The method of claim 1, The master device, A first strobe signal generation circuit for generating a first strobe signal for synchronizing the transfer of the serial data from the first serialization circuit to the slave device under the control of the first parallel operation circuit; And when the master device performs a write operation, the serial data from the first serialization circuit to the slave device is transmitted in synchronization with the first strobe signal. The method of claim 2, The slave device, A second strobe signal generation circuit for generating a second strobe signal for matching transmission of the serial data from the second serialization circuit to the master device under the control of the second parallel operation circuit; And when the master device performs a read operation, the serial data from the second serialization circuit to the master device is transmitted in synchronization with the second strobe signal. The method of claim 2, The first serialization circuit includes: an address data serialization circuit for converting parallel address data transmitted from the first parallel operation circuit into serial address data; A write data serialization circuit for converting the parallel write data transmitted from the first parallel operation circuit into serial write data; And an operation command data serialization circuit for converting parallel operation command data transmitted from the first parallel operation circuit into serial operation command data. The second parallel circuit includes: an address data parallel circuit for converting the serial address data into parallel address data and transmitting the same to the second parallel operation circuit; A write data parallelization circuit for converting the serial write data into parallel write data and transmitting the same to the second parallel operation circuit; And an operation command data parallelizing circuit for converting the serial operation command data into parallel operation command data and transmitting the same to the second parallel operation circuit. The second serialization circuit includes: a read data serialization circuit for converting parallel read data transmitted from the second parallel operation circuit into serial read data; And an operation response data serialization circuit for converting parallel operation response data transmitted from the second parallel operation circuit into serial operation response data. The first parallelizing circuit includes: a read data paralleling circuit for converting the serial read data into parallel read data and transmitting the same to the first parallel computing circuit; And an operation response data parallelization circuit for converting the serial operation response data into parallel operation response data and transmitting the same to the first parallel operation circuit. And the transfer of each serial data from each serialization circuit to each parallelization circuit is performed via one 1-bit busline.