KR20020074003A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- KR20020074003A KR20020074003A KR1020010014069A KR20010014069A KR20020074003A KR 20020074003 A KR20020074003 A KR 20020074003A KR 1020010014069 A KR1020010014069 A KR 1020010014069A KR 20010014069 A KR20010014069 A KR 20010014069A KR 20020074003 A KR20020074003 A KR 20020074003A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 title claims abstract description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 13
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims description 2
- 229910052731 fluorine Inorganic materials 0.000 claims description 2
- 239000011737 fluorine Substances 0.000 claims description 2
- 239000006117 anti-reflective coating Substances 0.000 abstract description 4
- 230000002093 peripheral effect Effects 0.000 abstract 3
- 239000010410 layer Substances 0.000 description 10
- 238000005530 etching Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 239000012044 organic layer Substances 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 230000003667 anti-reflective effect Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 125000003118 aryl group Chemical group 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000002598 diffusion tensor imaging Methods 0.000 description 1
- 238000001393 microlithography Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920002492 poly(sulfone) Polymers 0.000 description 1
- 229910000859 α-Fe Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0276—Photolithographic processes using an anti-reflective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Element Separation (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로 특히, 감광막 단차로 인한 하부층의 손상을 방지하는데 적당한 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device suitable for preventing damage to an underlying layer due to photoresist step.
최근에는 DUV(Deep Ultra Violet)용 반사방지막(Anti Reflective Coating ; ARC)으로 하부 유기층의 사용이 급격히 증가하고 있다.Recently, the use of the lower organic layer is rapidly increasing as an anti-reflective coating (ARC) for deep ultra violet (DUV).
즉, 반사방지막을 구성하는 구성물이 상기와 같은 아르메틱 폴리설폰 구조를 가질 경우에 DUV 마이크로리소그래피에 대해 유용한 반사방지막으로 사용된다.That is, it is used as an antireflective film useful for DUV microlithography when the constituent constituting the antireflective film has such an armetic polysulfone structure.
유기층의 성분은 아르메틱(Aromatic)기 등의 C가 주성분이며 그 이외에는 S, O-H 등의 성분을 가지므로 이러한 유기층을 식각하기 위해서는 다운 스트림(Down Stream) 형태, 또는 플라즈마 형태의 식각, 또는 반응성 이온식각 장비(Reactive Ion Etching; RIE) 등에서 O2플라즈마를 이용한다.The component of the organic layer is C, such as an aromatic group, and has a component such as S, OH, etc., so that the organic layer may be etched in a downstream form, plasma form, or reactive ion to etch such an organic layer. O 2 plasma is used in etching equipment (Reactive Ion Etching; RIE).
이하, 종래 기술에 따른 반도체 소자의 제조방법을 첨부된 도면을 참조하여 설명하기로 한다.Hereinafter, a method of manufacturing a semiconductor device according to the prior art will be described with reference to the accompanying drawings.
도 1a 내지 도 1d는 종래의 반도체 소자의 제조방법을 설명하기 위한 공정 단면도이다.1A to 1D are cross-sectional views illustrating a conventional method for manufacturing a semiconductor device.
ISNAND Flash 메모리를 구현하기 위해서는 DTI(Deep Trench Isolation)이 셀지역에 형성되어야 하며, 동시에 페리지역에는 STI(Shallow Trench Isolation)이 형성되어야 한다.In order to implement ISNAND Flash memory, a deep trench isolation (DTI) must be formed in a cell region while a shallow trench isolation (STI) must be formed in a ferry region.
먼저, 도 1a에 도시한 바와 같이, 선택적으로 식각하고자 하는 반도체 기판(1)상 전면에 질화물질을 증착하여 하드마스크(2)를 형성한다.First, as illustrated in FIG. 1A, a hard mask 2 is formed by depositing a nitride material over an entire surface of a semiconductor substrate 1 to be selectively etched.
도 1b에 도시한 바와 같이, 상기 하드마스크(2) 전면에 DUV 감광막을 도포한 후, 노광 및 현상공정을 통해 DTI를 형성하기 위한 셀지역을 패터닝하여 감광막 패턴(도시하지 않음)을 형성한다.As shown in FIG. 1B, after the DUV photosensitive film is coated on the entire surface of the hard mask 2, a cell region for forming the DTI is patterned through an exposure and developing process to form a photosensitive film pattern (not shown).
그리고, 상기 감광막 패턴(도시하지 않음)을 마스크로 이용하여 하드마스크(2)를 패터닝하여 셀지역의 하드마스크 패턴(2a)을 형성한다.The hard mask 2 is patterned using the photoresist pattern (not shown) as a mask to form a hard mask pattern 2a of a cell region.
도 1c에 도시한 바와 같이, 상기 감광막 패턴을 제거한 후, 상기 하드마스크패턴(2a)을 마스크로 셀지역의 반도체 기판(1)을 선택적으로 식각하여 DTI 형성을 위한 제 1 트렌치(3)를 형성한다.As illustrated in FIG. 1C, after the photoresist pattern is removed, the semiconductor substrate 1 in the cell region is selectively etched using the hard mask pattern 2a as a mask to form a first trench 3 for forming a DTI. do.
도 1d에 도시한 바와 같이, 상기 하드마스크 패턴 전면에 STI 패터닝을 위해 다시 DUV 감광막을 도포한다.As shown in FIG. 1D, the DUV photoresist film is coated on the entire surface of the hard mask pattern for STI patterning.
이때, 상기 DUV 감광막은 제 1 트렌치(3)의 내부에 유입되어 셀지역 및 페리지역의 감광막의 단차를 유발시킨다.At this time, the DUV photosensitive film is introduced into the first trench 3 to cause a step of the photosensitive film of the cell region and the ferry region.
이후, 노광 및 현상공정을 통해 STI를 형성하기 위한 페리지역을 패터닝하여 감광막 패턴(4)을 형성한다.Thereafter, the ferrite region for forming the STI is patterned through the exposure and development processes to form the photoresist pattern 4.
이어, 상기 감광막 패턴(4)을 마스크로 페리지역의 하드마스크(2a)를 패터닝하여 하드마스크 패턴(도시하지 않음)을 형성한다.Subsequently, the hard mask 2a of the ferry region is patterned using the photoresist pattern 4 as a mask to form a hard mask pattern (not shown).
그리고, 상기 하드마스크 패턴(도시하지 않음)을 마스크로 페리지역의 반도체 기판(1a)을 선택적으로 식각하여 STI 형성을 위한 제 2 트렌치(도시하지 않음)를 형성한다.The semiconductor substrate 1a of the ferry region is selectively etched using the hard mask pattern (not shown) as a mask to form a second trench (not shown) for forming an STI.
상기 감광막 패턴(4)을 제거한 후, 상기 제 1 트렌치(3) 및 제 2 트렌치(도시하지 않음)내에 절연물질을 사용하여 매립하여 DTI 및 STI를 형성한다.After the photoresist pattern 4 is removed, an insulating material is embedded in the first trenches 3 and the second trenches (not shown) to form DTIs and STIs.
그러나, 상기와 같은 종래의 반도체 소자의 제조방법은 다음과 같은 문제점이 있다.However, the conventional method of manufacturing a semiconductor device as described above has the following problems.
DTI 형성을 위한 트렌치 식각 후, STI 마스크 패턴 형성용 감광막이 트렌치내로 유입되어 셀지역의 감광막 두께가 얇아진다.After the trench etching for forming the DTI, the photosensitive film for forming the STI mask pattern flows into the trench, thereby reducing the thickness of the photosensitive film in the cell region.
즉, 감광막의 단차로 인해 하부의 하드마스크 및 트렌치 프로파일에 손상을 입히게 된다.That is, the hard mask and the trench profile of the lower portion are damaged due to the step of the photoresist.
본 발명은 이와 같은 종래 기술의 반도체 소자의 제조방법의 문제를 해결하기 위한 것으로, 콘택필 특성이 좋은 유기 반사방지막을 이용하여 평탄화된 감광막을 형성함으로써 셀지역과 페리지역에서 감광막의 단차를 줄이는데 적당한 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.The present invention is to solve the problem of the conventional method of manufacturing a semiconductor device, it is suitable to reduce the step of the photosensitive film in the cell region and ferry region by forming a flattened photosensitive film using an organic antireflection film with good contact fill characteristics Its purpose is to provide a method for manufacturing a semiconductor device.
도 1a 내지 도 1d는 종래 반도체 소자의 제조방법을 나타낸 공정 단면도1A to 1D are cross-sectional views illustrating a method of manufacturing a conventional semiconductor device.
도 2a 내지 도 2e는 본 발명에 따른 반도체 소자의 제조방법을 나타낸 공정 단면도2A through 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
21 : 반도체 기판 22 : 하드마스크21: semiconductor substrate 22: hard mask
23 : 제 1 트렌치 24 : 유기 반사방지막23: first trench 24: organic antireflection film
25 : 감광막 패턴 26 : 제 2 트렌치25 photosensitive film pattern 26 second trench
이와 같은 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 제조방법은 제 1, 2 영역을 포함하는 반도체 기판의 전면에 하드마스크층을 형성하는 단계; 상기 제 1 영역상의 하드마스크층을 선택적으로 제거하고 이를 이용하여 제 1 트렌치들을 형성하는 단계; 상기 제 1 트렌치들이 매립되도록 전면에 유기 반사방지막을 형성하는 단계; 상기 유기 반사방지막을 이용하여 평탄화된 감광막 패턴을 형성하는 단계; 상기 감광막 패턴을 이용하여 제 2 영역상의 하드 마스크층, 반도체 기판을 선택적으로 제거하여 제 2 영역에 제 2 트렌치들을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.A method of manufacturing a semiconductor device according to the present invention for achieving the above object comprises the steps of forming a hard mask layer on the front surface of a semiconductor substrate including first and second regions; Selectively removing the hardmask layer on the first region and using the same to form first trenches; Forming an organic antireflection film on the entire surface of the first trenches so as to fill the first trenches; Forming a planarized photoresist pattern using the organic antireflection film; And selectively removing the hard mask layer and the semiconductor substrate on the second region by using the photoresist pattern to form second trenches in the second region.
이하, 본 발명의 반도체 소자의 제조방법을 첨부된 도면을 참조하여 설명하기로 한다.Hereinafter, a method of manufacturing a semiconductor device of the present invention will be described with reference to the accompanying drawings.
도 2a 내지 도 2e는 본 발명에 의한 반도체 소자의 제조방법을 설명하기 위한 공정 단면도이다.2A to 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
도 2a에 도시한 바와 같이, 제 1 영역 및 제 2 영역을 포함하는 반도체기판(21)상 전면에 하드마스크층(22)을 형성한다.As shown in FIG. 2A, the hard mask layer 22 is formed on the entire surface of the semiconductor substrate 21 including the first region and the second region.
이때, 상기 반도체 기판(21)은 산화물질로 형성하고, 상기 하드마스크층(22)은 1200∼2000Å의 두께의 질화물질로 형성한다.In this case, the semiconductor substrate 21 is formed of an oxide material, and the hard mask layer 22 is formed of a nitride material having a thickness of 1200 to 2000 GPa.
도 2b에 도시한 바와 같이, 상기 하드마스크층(22) 전면에 감광막을 도포한 후, 노광 및 현상공정을 통해 제 1 영역상의 감광막을 선택적으로 제거하여 감광막 패턴(도시하지 않음)을 형성한다.As shown in FIG. 2B, after the photoresist film is applied to the entire surface of the hard mask layer 22, the photoresist film on the first region is selectively removed through an exposure and development process to form a photoresist pattern (not shown).
이어, 상기 감광막 패턴(도시하지 않음)을 마스크로 이용하여 제 1 영역상의 하드마스크층(22)을 선택적으로 제거하여 하드마스크 패턴(22a)을 형성한다.Subsequently, the hard mask layer 22 on the first region is selectively removed using the photoresist pattern (not shown) as a mask to form the hard mask pattern 22a.
도 2c에 도시한 바와 같이, 상기 감광막 패턴을 제거한 후, 상기 하드마스크 패턴(22a)을 마스크로 반도체 기판()을 선택적으로 식각하여 DTI 형성을 위한 제 1 트렌치(23)들을 형성한다.As shown in FIG. 2C, after the photoresist pattern is removed, the semiconductor substrate () is selectively etched using the hard mask pattern 22a as a mask to form first trenches 23 for forming a DTI.
그리고, 상기 하드마스크 패턴(22a) 전면에 콘택필 특성이 우수한 플레너 타입(Planer Type)의 유기 반사방지막(24)을 증착하여 상기 제 1 트렌치(23)들을 매립한다.In addition, a planar type organic anti-reflection film 24 having excellent contact fill characteristics is deposited on the entire surface of the hard mask pattern 22a to fill the first trenches 23.
여기서, 상기 유기 반사방지막(24)은 600∼1200Å 사이의 두께로 형성한다.In this case, the organic antireflection film 24 is formed to a thickness of between 600 and 1200 kPa.
이어, 도 2d에 도시한 바와 같이, 상기 유기 반사방지막(24)상에 DUV 감광막을 도포한 후, 노광 및 현상공정을 통해 제 2 영역상의 감광막을 선택적으로 제거하여 감광막 패턴(25)을 형성한다.Subsequently, as shown in FIG. 2D, after the DUV photoresist film is applied onto the organic antireflection film 24, the photoresist film on the second region is selectively removed through an exposure and development process to form the photoresist film pattern 25. .
이때, 상기 제 1 트렌치(23)들의 내부에 채워진 유기 반사방지막(24)으로 인해 셀지역 및 페리지역의 감광막 단차는 감소된다.At this time, due to the organic anti-reflection film 24 filled in the first trenches 23, the photoresist step of the cell region and the ferry region is reduced.
이어, 도 2e에 도시한 바와 같이, 상기 감광막 패턴(25)을 마스크로 제 2 영역상의 유기 반사방지막(24), 하드마스크층(22a), 반도체 기판(21a)을 선택적으로 제거하여 제 2 영역에 제 2 트렌치(26)들을 형성한다.Subsequently, as shown in FIG. 2E, the organic anti-reflection film 24, the hard mask layer 22a, and the semiconductor substrate 21a on the second region are selectively removed using the photosensitive film pattern 25 as a mask. To form second trenches 26.
여기서, 상기 유기 반사방지막을 선택적으로 제거하기 위해 O2플라즈마에 N2또는 플루오닌을 포함하는 화합물 가스인 N2CHF3, CF4, C2F6등의 가스를 첨가하여 다운 스트림(Down Stream) 형태의 식각 또는 반응성 이온식각(Reactive Ion Etching) 혹은 MERIE(Magnetically Enhanced RIE) 등의 장비에서 식각공정을 수행한다.Here, in order to selectively remove the organic anti-reflective film, a gas such as N 2 CHF 3 , CF 4 , C 2 F 6 , which is a compound gas containing N 2 or fluorine, is added to the O 2 plasma to perform a downstream stream. Etching process is performed in equipment such as etch or reactive ion etching or magnetically enhanced RIE (MERIE).
또한, 상기 제 2 트렌치(26)들은 상기 제 1 트렌치(23)들보다 얕은 깊이로 형성한다.In addition, the second trenches 26 are formed to have a shallower depth than the first trenches 23.
이어, 상기 제 1 트렌치(23) 및 제 2 트렌치(26)내에 스텝 커버리지 특성이 우수한 절연물질을 사용하여 한번에 매립하여 소자 격리막을 형성한다.Subsequently, the device isolation layer is formed by filling the first trench 23 and the second trench 26 with an insulating material having excellent step coverage characteristics at once.
상기와 같은 본 발명의 반도체 소자의 제조방법은 다음과 같은 효과가 있다.The method of manufacturing a semiconductor device of the present invention as described above has the following effects.
콘택필 특성이 좋은 유기 반사방지막을 이용하여 감광막을 도포함으로써 셀지역과 페리지역에서의 감광막 단차를 줄이고 식각 시 하부의 하드마스크 및 트렌치 프로파일에 손상을 줄일 수 있다.By applying a photoresist using an organic anti-reflective coating with good contact fill characteristics, it is possible to reduce the photoresist step difference in the cell region and the ferry region, and to reduce damage to the hard mask and trench profile under the etching.
또한, 깊이가 다른 소자 격리막을 동시에 형성함으로써 공정단순화 및 수율향상의 효과가 있다.In addition, by simultaneously forming element isolation films having different depths, there is an effect of process simplification and yield improvement.
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| KR100696382B1 (en) * | 2005-08-01 | 2007-03-19 | 삼성전자주식회사 | Semiconductor device and method of fabricating the same |
| KR100869358B1 (en) * | 2002-06-29 | 2008-11-19 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
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| JPH07112006B2 (en) * | 1988-05-02 | 1995-11-29 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| JPH05315442A (en) * | 1992-05-11 | 1993-11-26 | Fujitsu Ltd | Manufacture of semiconductor device |
| US5536675A (en) * | 1993-12-30 | 1996-07-16 | Intel Corporation | Isolation structure formation for semiconductor circuit fabrication |
| KR970017948A (en) * | 1995-09-21 | 1997-04-30 | 김광호 | Organic antireflection film manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100869358B1 (en) * | 2002-06-29 | 2008-11-19 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
| KR100696382B1 (en) * | 2005-08-01 | 2007-03-19 | 삼성전자주식회사 | Semiconductor device and method of fabricating the same |
| US7550363B2 (en) | 2005-08-01 | 2009-06-23 | Samsung Electronics Co., Ltd. | Method of fabricating a semiconductor device having first and second trenches using non-concurrently formed hard mask patterns |
| US8148784B2 (en) | 2005-08-01 | 2012-04-03 | Samsung Electronics Co., Ltd. | Semiconductor device having first and second device isolation layers formed of different insulation materials |
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