KR20020065734A - Semiconductor package and method for fabricating the same - Google Patents
Semiconductor package and method for fabricating the same Download PDFInfo
- Publication number
- KR20020065734A KR20020065734A KR1020010005907A KR20010005907A KR20020065734A KR 20020065734 A KR20020065734 A KR 20020065734A KR 1020010005907 A KR1020010005907 A KR 1020010005907A KR 20010005907 A KR20010005907 A KR 20010005907A KR 20020065734 A KR20020065734 A KR 20020065734A
- Authority
- KR
- South Korea
- Prior art keywords
- lead
- semiconductor chip
- package
- semiconductor
- mold body
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
본 발명은 반도체 패키지에 관한 것으로서, 더욱 상세하게는 기존의 부자재인 리드프레임을 이용하면서도 경박단소화되며 열방출 성능이 향상된 새로운 구조의 반도체 패키지를 제공하기 위한 것이다.The present invention relates to a semiconductor package, and more particularly, to provide a semiconductor package having a new structure, which is light and small, and has improved heat dissipation performance while using a conventional lead frame.
일반적으로, 반도체 산업에서 집적회로에 대한 패키징 기술은 소형화에 대한 요구 및 실장 신뢰성을 만족시키기 위해 지금까지 계속 발전해오고 있다.In general, the packaging technology for integrated circuits in the semiconductor industry continues to evolve to meet the demand for miniaturization and mounting reliability.
즉, 소형화에 대한 요구는 칩 스케일에 근접한 패키지에 대한 개발을 가속화시키고 있으며, 실장 신뢰성에 대한 요구는 실장작업의 효율성 및 실장후의 기계적·전기적 신뢰성을 향상시킬 수 있는 패키지 제조 기술에 대한 중요성을 부각시키고 있다.In other words, the demand for miniaturization is accelerating the development of packages close to the chip scale, and the demand for mounting reliability emphasizes the importance of package manufacturing technology that can improve the efficiency of mounting work and the mechanical and electrical reliability after mounting. I'm making it.
한편, 일반적으로 반도체소자는 집적회로가 형성된 웨이퍼 상태에서 낱개의 칩으로 각각 분리된 후, 이것을 플라스틱 패키지나 세라믹 패키지에 탑재하여 기판에의 실장이 용이하도록 조립하는 패키징 공정을 거치게 된다.On the other hand, in general, semiconductor devices are separated into individual chips in a wafer in which integrated circuits are formed, and then mounted in a plastic package or a ceramic package, and then subjected to a packaging process for assembling the substrate to facilitate mounting on the substrate.
이와 같이 행해지는 반도체소자에 대한 패키징 공정의 주목적은 기판이나 소켓에 실장하기 위한 형상의 확보와 기능보호에 있다고 할 수 있다.The main purpose of the packaging step for the semiconductor element thus performed is to secure the shape and protect the function for mounting on the substrate or the socket.
또한, 최근에는 집적회로의 고집적화에 따라 다핀화, 미세조립기술, 또 실장형태의 다양화에 따른 패키지의 다종류화 등, 조립공정과 관련된 기술도 각각 세분된 분야에 따라 크게 변화하고 있다.In addition, in recent years, technologies related to the assembly process, such as multi-pinning, micro-assembly technology, and package variety due to the diversification of the mounting type according to the high integration of integrated circuits, are also greatly changed according to the subdivided fields.
반도체 조립공정의 개요에 대해 현재 가장 많이 사용되고 있는 플라스틱 타입의 반도체소자를 예로 들어 설명하면 다음과 같다.An overview of the semiconductor assembly process will be described below with an example of a plastic type semiconductor device which is most used.
먼저, 전기적 회로가 형성된 웨이퍼를 각각의 단일 칩으로 분리하는데, 이때 Si(실리콘)는 모스경도 7로서 딱딱하고 깨지기 쉬운 성질을 갖고 있으므로 웨이퍼의 제조시 미리 분리할 라인에 절단하기 위한 물질을 넣어두고 이 분리라인을 따라브레이크 응력을 가해 파괴, 분리시키는 방법을 취하는 경우가 많다.First, the wafer on which the electrical circuit is formed is separated into each single chip, and Si (silicon) has a Mohs hardness of 7 and is hard and brittle, so that a material for cutting is placed in a line to be separated in advance in manufacturing the wafer. In many cases, a break stress is applied along this separation line to break and separate.
또한, 분리된 각각의 반도체 칩은 리드프레임의 다이패드에 본딩되고, 이때의 접합방법은 Au-Si 공정(共晶)법, 납땜법, 수지접착법 등이 있으며 용도에 따라 알맞은 방법이 선택되어 사용된다.In addition, each separated semiconductor chip is bonded to the die pad of the lead frame, and the bonding method is Au-Si process, soldering method, resin bonding method, etc. Used.
한편, 전술한 바와 같이 반도체 칩을 리드프레임의 다이패드에 접착하는 목적은 조립이 완료된 후 기판에 실장시키기 위해서 뿐만 아니라, 전기적 입출력단자나 어스(earth)를 겸하는 일도 있으며 소자의 동작시 발생하는 열의 방열통로로서도 필요로 하는 경우가 있기 때문이다.On the other hand, as described above, the purpose of bonding the semiconductor chip to the die pad of the lead frame is not only to be mounted on the substrate after assembly is completed, but also to serve as an electrical input / output terminal or earth, This is because the heat dissipation path may be required.
상기와 같이 반도체 칩을 본딩한 후에는 칩의 본딩패드와 리드프레임의 인너리드를 와이어로 본딩함으로써 연결하게 되며, 와이어 본딩의 방법으로 플라스틱 봉함 패키지에서는 일반적으로 골드 와이어를 사용한 열압착법 또는 열압착법과 초음파법을 혼용한 방법이 주로 이용되고 있다.After bonding the semiconductor chip as described above, the bonding pad of the chip and the inner lead of the lead frame are bonded by wires. In the plastic sealing package, a thermal bonding method or thermocompression bonding is generally performed using a gold wire in a plastic sealing package. The method which mixed the method and the ultrasonic method is mainly used.
또한, 와이어 본딩에 의해 반도체 칩과 인너리드가 전기적으로 연결된 후에는 칩을 고순도의 에폭시 수지를 사용하여 성형 봉합함으로써 몰드바디를 형성시키는 몰딩공정이 수행되는데, 이때 사용되는 에폭시 수지는 집적회로의 신뢰성을 좌우하는 중요한 요소이며, 수지의 고순도화와 몰딩시 집적회로에 주어지는 응력을 저감시키기 위한 저응력화 등의 개선이 추진되고 있다.In addition, after the semiconductor chip and the inner lead are electrically connected by wire bonding, a molding process of forming a mold body by forming and sealing the chip using a high purity epoxy resin is performed. In addition, the improvement of the high purity of the resin and the reduction of the stress for reducing the stress applied to the integrated circuit during molding are being promoted.
그리고, 상기한 공정이 완료된 후에는 IC 패키지를 소켓이나 기판에 실장하기 위해 아웃터리드(outer lead)를 소정의 형상으로 절단하고 성형하는 공정이 행해지며, 아웃터리드에는 실장접합성(납땜성)을 향상시키기 위해 도금이나납딥(dip)이 처리된다.After the above process is completed, a process of cutting and molding an outer lead into a predetermined shape is carried out to mount the IC package on a socket or a substrate, and the mount is improved in solderability. Plating or dip is processed to make it work.
한편, 반도체 패키지는 실장형태 및 리드형태에 따라 여러 가지 유형으로 나뉘는데, 패키지의 대표적인 예로서는 전술한 DIP(Dual Inline Package)외에 QFP(Quad Flat Package), TSOP(Thin Small Outline Package), BGA 패키지( Ball Grid Array package), BLP(Bottom Leaded Package) 등이 있으며, 계속 다핀(多-pin)화 또는 경박단소(輕薄短小)화 되고 있다.On the other hand, semiconductor packages are divided into various types according to the mounting type and the lead type. As a representative example of the package, in addition to the above-described dual inline package (DIP), QFP (Quad Flat Package), TSOP (Thin Small Outline Package), and BGA package (Ball) Grid Array package (BLP), Bottom Leaded Package (BLP), and the like, continue to be multi-pin or light and thin.
상기한 패키지 타입중, BGA 패키지(Ball Grid Array package)는 반도체 칩이 부착된 기판의 이면에 구형의 솔더볼을 소정의 상태로 배열(Array)하여 아웃터리드(outer lead) 대신으로 사용하게 되며, 상기 BGA 패키지는 패키지 몸체(Package Body) 면적을 QFP(Quad Flat Package) 타입보다 작게 할 수 있으며, QFP와는 달리 리드의 변형이 없는 장점이 있다.Among the above package types, the BGA package (Ball Grid Array package) is used to replace the outer lead by arranging a spherical solder ball in a predetermined state on the back side of the substrate on which the semiconductor chip is attached. The BGA package can make the package body area smaller than the QFP (Quad Flat Package) type, and unlike QFP, there is an advantage that there is no deformation of the lead.
그러나, 상기 BGA 패키지는 기존의 리드프레임에 비해 값이 비싼 회로기판을 사용하므로 제조원가가 높아지고, 반도체 칩 및 골드 와이어의 보호를 위해 봉지공정 수행시 상형 및 하형에 의해 회로기판이 눌러져 솔더마스크에 크랙이 발생할 우려가 높아지는 등의 단점이 있다.However, since the BGA package uses a circuit board that is more expensive than a conventional lead frame, the manufacturing cost increases, and when the encapsulation process is performed to protect the semiconductor chip and the gold wire, the circuit board is pressed by the upper and lower molds and cracks in the solder mask. There are disadvantages such as a high possibility of occurrence.
한편, BLP(Bottom Leaded Package)는 패키지 몸체의 바텀면을 통해 노출된 리드를 이용하여 기판에 실장하므로, 패키지 몸체의 두께를 아웃터리드를 갖는 DIP나 QFP 타입에 비해 작게 할 수 있다.On the other hand, since BLP (Bottom Leaded Package) is mounted on the substrate using the lead exposed through the bottom surface of the package body, the thickness of the package body can be made smaller than that of the DIP or QFP type having an outlier.
상기한 반도체 패키지들은 실장면적, 입출력 단자수, 전기적 신뢰성, 제조공정의 유연성, 제조비용등에 있어 제각기 장점 및 단점을 갖고 있다.The semiconductor packages have advantages and disadvantages in terms of mounting area, number of input / output terminals, electrical reliability, manufacturing process flexibility, manufacturing cost, and the like.
따라서, 상기한 각 패키지들의 장점을 살리면서 단점을 해소한 새로운 타입의 반도체 패키지가 지속적으로 연구 개발되고 있는 실정이다.Therefore, a new type of semiconductor package that solves the disadvantages while making use of the advantages of the above-mentioned packages is constantly being researched and developed.
본 발명은 상기한 바와 같은 실정에 따라 기존의 반도체 패키지가 갖는 장점을 최대한 살리면서 단점은 해소한 새로운 타입의 반도체 패키지를 제공하기 위해 안출된 것으로, 값싸고 신뢰성 높은 기존의 부자재(附資材)를 이용함으로써 제조 비용 측면에서는 저비용으로 제조가능하고 구조적 측면에서는 경박단소하며 방열성능이 뛰어난 신뢰성 높은 반도체 패키지 및 그 제조방법을 제공하는데 그 목적이 있다.The present invention has been devised to provide a new type of semiconductor package that solves the disadvantages of the existing semiconductor package while maximizing the advantages of the existing semiconductor package. It is an object of the present invention to provide a highly reliable semiconductor package and a method of manufacturing the same, which can be manufactured at low cost in terms of manufacturing cost, are light and simple in structure, and excellent in heat dissipation performance.
도 1은 본 발명에 따른 반도체 패키지를 나타낸 종단면도1 is a longitudinal sectional view showing a semiconductor package according to the present invention;
도 2a 내지 도 2c는 본 발명에 따른 반도체 패키지 제조 과정을 나타낸 것으로서,2A to 2C illustrate a semiconductor package manufacturing process according to the present invention.
도 2a는 다이 어태치 후의 상태도2A is a state diagram after the die attach
도 2b는 와이어 본딩 후의 상태도2B is a state diagram after wire bonding
도 2c는 몰딩 후의 상태도2c is a state diagram after molding
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1:반도체 칩2:다이패드1: semiconductor chip 2: die pad
3:랜드4:전도성 연결부재3: land 4: conductive connecting member
5:리드6:몰드바디5: lead 6: molded body
상기한 목적을 달성하기 위한 본 발명에 따르면, 반도체칩과, 상기 반도체칩이 안착되는 다이패드와, 상기 다이패드 주위에 이격되어 위치하며 내측 및 외측 에지부 바텀측에 하프에칭 영역이 구비되고 그 사이에는 랜드 영역이 구비되는 리드와, 상기 반도체칩의 본딩패드와 상기 리드를 전기적으로 연결하는 전도성 연결부재와, 상기 리드의 랜드 영역만이 노출되도록 하고 이를 제외한 나머지 전체 구조를 감싸는 몰드바디를 포함하여서 된 반도체 패키지가 제공된다.According to the present invention for achieving the above object, there is provided a semiconductor chip, a die pad on which the semiconductor chip is seated, and a half-etching area on the bottom side of the inner and outer edges and spaced apart around the die pad. A lead having a land region therebetween, a conductive connection member electrically connecting the bonding pad of the semiconductor chip to the lead, and a mold body covering only the land structure of the lead and covering the entire structure except for this; A semiconductor package is provided.
한편, 상기한 목적을 달성하기 위한 본 발명의 다른 형태에 따르면, 내측 및 외측 에지부 바텀측에 하프에칭 영역이 구비되고 그 사이에는 랜드 영역이 구비되는 랜드 그리드 타입의 리드를 구비한 리드프레임의 다이패드 상에 반도체칩을 부착하는 단계와, 상기 반도체칩의 본딩패드와 상기 내측 및 외측 에지부 바텀측이하프 에칭된 리드를 와이어등의 전도성 연결부재로 연결하는 단계와, 상기 전도성 연결부재 및 반도체칩이 봉지되도록 몰드바디를 형성하는 단계를 포함하여서 됨을 특징으로 하는 반도체 패키지 제조방법이 제공된다.On the other hand, according to another aspect of the present invention for achieving the above object, a half-etching region is provided on the bottom side of the inner and outer edge portion, and between the lead frame having a land grid type lead having a land region therebetween. Attaching a semiconductor chip on a die pad, connecting the bonding pad of the semiconductor chip and the lead etched the bottom side of the inner and outer edge portions with a conductive connecting member such as a wire, and the conductive connecting member; Provided is a method of manufacturing a semiconductor package, comprising forming a mold body such that the semiconductor chip is encapsulated.
이하, 본 발명의 실시예에 대해 도 1 및, 도 2a 내지 도 2c를 참조하여 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2A to 2C.
도 1은 본 발명에 따른 반도체 패키지를 나타낸 종단면도로서, 반도체칩(1)과, 상기 다이패드(2) 주위에 이격되어 위치하며 내측 및 외측 에지부 바텀측에 하프에칭 영역이 구비되고 그 사이에는 랜드(3) 영역이 구비되는 리드(5)와, 상기 반도체칩(1)의 본딩패드와 상기 리드(5)를 전기적으로 연결하는 전도성 연결부재(4)와, 상기 리드(5)의 랜드(3) 영역만이 노출되도록 하고 이를 제외한 나머지 전체 구조를 감싸는 몰드바디(6)를 포함하여 구성된다.1 is a longitudinal cross-sectional view showing a semiconductor package according to the present invention, wherein the semiconductor chip 1 and the die pad 2 are spaced apart from each other, and half-etched regions are provided at the bottom side of the inner and outer edges thereof. A lead 5 having a land 3 region, a conductive connection member 4 electrically connecting the bonding pad of the semiconductor chip 1 and the lead 5, and a land of the lead 5; (3) It is configured to include a mold body (6) to cover only the entire structure except to expose the area.
이 때, 상기 전도성 연결부재(4)는 골드, 알루미늄, 또는 구리중의 어느 하나이거나 이들을 포함한 합금으로 이루어진다.At this time, the conductive connecting member 4 is made of any one of gold, aluminum, or copper, or an alloy containing them.
이와 같이 구성된 본 발명의 반도체 패키지의 제조과정은 다음과 같다.The manufacturing process of the semiconductor package of the present invention configured as described above is as follows.
먼저, 리드프레임의 다이패드(2) 상에 반도체칩(1)을 부착한다.First, the semiconductor chip 1 is attached onto the die pad 2 of the lead frame.
그 후, 상기 반도체칩(1)의 본딩패드와 상기 리드(5)를 골드와이어 등의 전도성 연결부재(4)를 이용하여 전기적으로 연결한다.Thereafter, the bonding pads of the semiconductor chip 1 and the leads 5 are electrically connected by using conductive connecting members 4 such as gold wires.
이어, 봉지제를 이용하여 리드(5)의 랜드(3) 영역만이 노출되고 나머지 구조는 감싸지도록 봉지하여 몰드바디(6)를 형성한다.Subsequently, the encapsulant is encapsulated so that only the land 3 region of the lid 5 is exposed and the rest of the structure is enclosed to form the mold body 6.
이에 따라, 반도체칩(1)과 전도성 연결부재(4)는 외부의 영향으로부터 보호된다.Accordingly, the semiconductor chip 1 and the conductive connecting member 4 are protected from external influences.
이러한 본 발명의 패키지는 리드(5)의 내측 및 외측 에지부 바텀측에 하프에칭 영역이 구비되어 있으므로, 리드(5)에 대한 몰드바디(6)의 지지력 및 상호간의 결합력이 향상되어 리드 들뜸이나 갭발생이 방지된다.Since the package of the present invention has a half etching area at the bottom side of the inner and outer edges of the lid 5, the supporting force of the mold bodies 6 and the mutual coupling force with respect to the lid 5 are improved, so that the lead is lifted. Gap occurrence is prevented.
또한, 외측 에지부 바텀측이 하프 에칭되어 그 두께가 줄어들고, 외측 에지 부분의 하프 에칭된 영역 하부에 몰드바디(6)가 형성되어 있으므로 인해, 메탈 버(burr)의 발생을 방지할 수 있게 된다.In addition, since the bottom side of the outer edge portion is half etched, the thickness thereof is reduced, and since the mold body 6 is formed under the half etched region of the outer edge portion, it is possible to prevent the occurrence of metal burrs. .
즉, 외측 에지부 바텀측이 하프 에칭되어 있지 않다면, 싱귤레이션시에 메탈 버가 발생할 가능성이 높으나, 본 발명에서는 리드(5)의 외측 에지 부분 상·하부에 양측에 봉지제가 위치하므로 인해 메탈 버의 발생이 방지되는 것이다.That is, if the bottom side of the outer edge portion is not half-etched, metal burrs are more likely to be generated during singulation. However, in the present invention, since the encapsulant is located on both sides of the upper and lower portions of the outer edge of the lid 5, the metal burrs are disposed. Will be prevented.
그리고, 실장시의 전기적 신뢰성 향상을 위해 랜드(3) 영역에 플레이팅되는 골드등의 도금량을 줄여 플레이팅 비용을 절감할 수 있게 된다.In addition, the plating cost can be reduced by reducing the plating amount of gold, etc., which is plated on the land 3 to improve the electrical reliability at the time of mounting.
한편, 상기한 본 발명의 반도체 패키지는 리드프레임 상에서 스트립 단위로 몰딩까지 진행한 후에, 소잉 또는 펀칭하여 개별 유니트로 분리시킬 수도 있음은 물론이다.On the other hand, the semiconductor package of the present invention described above may be separated into individual units by sawing or punching after the molding to the strip unit on the lead frame.
이상에서와 같이, 본 발명은 기존의 반도체 패키지가 갖는 장점을 최대한 살리면서 단점은 해소한 새로운 타입의 반도체 패키지를 제공하기 위한 것이다.As described above, the present invention is to provide a new type of semiconductor package, while making the most of the advantages of the existing semiconductor package while eliminating its disadvantages.
즉, 본 발명의 패키지는 리드의 내측 및 외측 에지부 바텀측에 하프에칭 영역이 구비되어 있으므로, 리드에 대한 몰드바디의 지지력 및 상호간의 결합력이 향상되어 리드 들뜸이나 갭발생이 방지되며, 외측 에지 부분이 하프 에칭되어 그 두께가 줄어들고 리드가 몰드바디 함몰되므로 인해, 메탈 버(burr)의 발생이 방지된다.That is, the package of the present invention is provided with a half etching area on the bottom side of the inner and outer edges of the lead, thereby improving the support force and mutual coupling force of the mold body to the lead to prevent the lifting of the lead or the occurrence of gap, the outer edge Since the part is half etched to reduce its thickness and the lead is recessed in the mold body, the occurrence of metal burrs is prevented.
그리고, 실장시의 전기적 신뢰성 향상을 위해 랜드 영역에 플레이팅되는 골드등의 도금량을 줄여 플레이팅 비용을 절감할 수 있게 된다.In addition, the plating cost can be reduced by reducing the plating amount of gold, which is plated in the land region, to improve electrical reliability at the time of mounting.
요컨대, 본 발명은 값싸고 신뢰성 높은 기존의 부자재(附資材)를 이용함으로써 제조 비용 측면에서는 저비용으로 제조가능하고 구조적 측면에서는 경박단소하며 방열성능이 뛰어난 신뢰성 높은 반도체 패키지의 제조를 제공할 수 있게 된다.In short, the present invention can provide a highly reliable semiconductor package that can be manufactured at low cost in terms of manufacturing cost, light in structure, and excellent in heat dissipation performance by using existing subsidiary materials which are inexpensive and reliable. .
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010005907A KR20020065734A (en) | 2001-02-07 | 2001-02-07 | Semiconductor package and method for fabricating the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010005907A KR20020065734A (en) | 2001-02-07 | 2001-02-07 | Semiconductor package and method for fabricating the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20020065734A true KR20020065734A (en) | 2002-08-14 |
Family
ID=27693601
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020010005907A KR20020065734A (en) | 2001-02-07 | 2001-02-07 | Semiconductor package and method for fabricating the same |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20020065734A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19980044244A (en) * | 1996-12-06 | 1998-09-05 | 황인길 | Structure of Semiconductor Package |
| JPH1174404A (en) * | 1997-08-28 | 1999-03-16 | Nec Corp | Ball-grid-array semiconductor device |
| KR20000009885A (en) * | 1998-07-29 | 2000-02-15 | 윤종용 | Semiconductor package with a ball grid array type |
| EP0989608A2 (en) * | 1998-09-21 | 2000-03-29 | Amkor Technology Inc. | Plastic integrated circuit device package and method of making the same |
-
2001
- 2001-02-07 KR KR1020010005907A patent/KR20020065734A/en not_active Application Discontinuation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19980044244A (en) * | 1996-12-06 | 1998-09-05 | 황인길 | Structure of Semiconductor Package |
| JPH1174404A (en) * | 1997-08-28 | 1999-03-16 | Nec Corp | Ball-grid-array semiconductor device |
| KR20000009885A (en) * | 1998-07-29 | 2000-02-15 | 윤종용 | Semiconductor package with a ball grid array type |
| EP0989608A2 (en) * | 1998-09-21 | 2000-03-29 | Amkor Technology Inc. | Plastic integrated circuit device package and method of making the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6545347B2 (en) | Enhanced leadless chip carrier | |
| US8836101B2 (en) | Multi-chip semiconductor packages and assembly thereof | |
| KR20020049944A (en) | semiconductor package and method for fabricating the same | |
| US7348659B2 (en) | Semiconductor device and method of manufacturing thereof | |
| US6781242B1 (en) | Thin ball grid array package | |
| CN110010489B (en) | Method for manufacturing semiconductor device with side wall recess and related device | |
| US8487424B2 (en) | Routable array metal integrated circuit package fabricated using partial etching process | |
| US20030006055A1 (en) | Semiconductor package for fixed surface mounting | |
| US20030214048A1 (en) | Semiconductor package and fabricating method thereof | |
| US20050218499A1 (en) | Method for manufacturing leadless semiconductor packages | |
| CN100541748C (en) | Lead frame, semiconductor die package, and the manufacture method of this encapsulation | |
| US20100193922A1 (en) | Semiconductor chip package | |
| KR20050109502A (en) | Lead frame with included passive devices | |
| US20100200972A1 (en) | BGA package with leads on chip | |
| US20090206459A1 (en) | Quad flat non-leaded package structure | |
| US10290593B2 (en) | Method of assembling QFP type semiconductor device | |
| JPH11297917A (en) | Semiconductor device and its manufacture | |
| KR20020065733A (en) | Semiconductor package and method for the same | |
| KR100462373B1 (en) | Chip scale package and method for fabricating the same | |
| KR20020065734A (en) | Semiconductor package and method for fabricating the same | |
| KR100437821B1 (en) | semiconductor package and metod for fabricating the same | |
| KR20020065735A (en) | Semiconductor package and method for fabricating the same | |
| KR20020049823A (en) | semiconductor package and method for fabricating the same | |
| KR20020049821A (en) | chip scale semiconductor package in wafer level and method for fabricating the same | |
| KR20020065729A (en) | Semicoductor package |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E601 | Decision to refuse application |