KR20020061063A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- KR20020061063A KR20020061063A KR1020010001843A KR20010001843A KR20020061063A KR 20020061063 A KR20020061063 A KR 20020061063A KR 1020010001843 A KR1020010001843 A KR 1020010001843A KR 20010001843 A KR20010001843 A KR 20010001843A KR 20020061063 A KR20020061063 A KR 20020061063A
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- oxide film
- film
- pad oxide
- trench
- silicon nitride
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- 238000000034 method Methods 0.000 title claims abstract description 45
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 238000002955 isolation Methods 0.000 claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 238000005530 etching Methods 0.000 claims abstract description 6
- 150000004767 nitrides Chemical class 0.000 claims description 6
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 20
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 20
- 238000001020 plasma etching Methods 0.000 abstract description 9
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 8
- 239000012535 impurity Substances 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000000059 patterning Methods 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 15
- 238000005468 ion implantation Methods 0.000 description 15
- 229910052710 silicon Inorganic materials 0.000 description 15
- 239000010703 silicon Substances 0.000 description 15
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 6
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 5
- 239000012528 membrane Substances 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/3115—Doping the insulating layers
- H01L21/31155—Doping the insulating layers by ion implantation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
본 발명은 반도체 제조 방법에 관한 것으로서, 더욱 상세하게는 소자 분리막의 식각 마스크 패턴으로 사용되는 패드 산화막을 제거하지 않고 게이트 산화막 제조 공정 전에 진행되는 이온 주입의 버퍼 산화막으로 활용하는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device, which is used as a buffer oxide film for ion implantation that is performed before a gate oxide film manufacturing process without removing the pad oxide film used as an etching mask pattern of the device isolation film. It is about.
최근 반도체 장치의 제조공정 기술의 발달과 메모리 소자의 응용 분야가 확장되어 감에 따라 대용량의 메모리 소자의 개발이 진척되고 있는데, 이러한 메모리 소자의 대용량화는 각 세대마다 2배로 진행하는 미세 공정 기술을 기본으로 한 메모리 셀 연구에 의해 추진되어 오고 있다. 특히 소자간을 분리하는 소자 분리막의 축소는 메모리소자의 미세화 기술에 있어서 중요한 항목중의 하나로 대두되고 있다.Recently, as the development of semiconductor device manufacturing process technology and the application field of memory device have been expanded, the development of large-capacity memory device is progressing, and the large capacity of such memory device is based on the micro process technology that is doubled for each generation. It has been promoted by research on memory cells. In particular, the reduction of the device isolation film separating the devices has emerged as one of the important items in the miniaturization technology of the memory device.
종래의 소자분리기술로는 반도체 기판 상에 두꺼운 산화막을 선택적으로 성장시켜 소자 분리막을 형성하는 로커스(Local Oxidation of Silicon: 이하 LOCOS라 함) 기술이 대부분 이었으나, 최근에는 트렌치(trench) 구조의 소자분리기술이 널리 사용되고 있다. LOCOS 방식은 소자 분리막의 측면 확산 및 분리를 원하지 않는 부분에 산화막이 생성되는 현상에 의해 고집적 반도체소자의 경우 소자 분리막의 폭을 축소하는데 어려움이 있지만, 이 트렌치 소자 분리 방법의 경우에는 반도체 기판에 소정 폭과 소정 깊이로 트렌치를 형성하고 이 트렌치에 산화막을 매립하여 소자 분리막을 형성하는 바, LOCOS에 비해 80%에 가깝게 소자분리영역을 축소할 수 있었다.Conventional device isolation technology has mostly been a local oxide of silicon (LOCOS) technology for selectively growing a thick oxide film on a semiconductor substrate to form a device isolation film, but recently, device isolation with a trench structure Technology is widely used. In the LOCOS method, it is difficult to reduce the width of the device isolation film in the case of the highly integrated semiconductor device due to the phenomenon in which the oxide film is formed on the side of the device isolation film and the portion where the separation is not desired. A trench was formed with a width and a predetermined depth, and an oxide film was buried in the trench to form a device isolation film. Thus, the device isolation region could be reduced to nearly 80% compared to LOCOS.
도 1a 내지 1g는 종래 기술에 의한 소자 분리막 및 이온 주입 공정을 나타낸 공정 순서도이다. 이들을 참조하여 종래 트렌치 구조의 소자 분리막 및 이온 주입 공정에 대해 설명한다.1A to 1G are process flowcharts illustrating a device isolation membrane and an ion implantation process according to the prior art. With reference to these, the device isolation membrane and ion implantation process of a conventional trench structure are demonstrated.
도 1a에 도시된 바와 같이, 반도체 기판으로서 실리콘 기판(10)에 패드 산화막(20)과 실리콘 질화막(30) 순차 증착한다. 이때, 패드 산화막(20)은 열산화 공정에 의해 형성되고, 실리콘 질화막(30)은 화학 기상 증착법(Chemical VaporDeposition), 예를 들면 저압 화학 기상 증착법(LPCVD : Low Pressure Chemical Vapor Deposition), 상압 화학 기상 증착법(APCVD : Atmospheric Pressure Chemical Vapor Deposition) 등에 의해 형성된다.As shown in FIG. 1A, the pad oxide film 20 and the silicon nitride film 30 are sequentially deposited on the silicon substrate 10 as a semiconductor substrate. At this time, the pad oxide film 20 is formed by a thermal oxidation process, the silicon nitride film 30 is chemical vapor deposition (Chemical Vapor Deposition), for example, low pressure chemical vapor deposition (LPCVD: low pressure chemical vapor deposition), atmospheric pressure chemical vapor deposition It is formed by an evaporation method (APCVD: Atmospheric Pressure Chemical Vapor Deposition).
다음에, 포토 리소그래피(photo lithography) 공정을 수행하여 실리콘 질화막(30) 및 패드 산화막(20)을 패터닝하여 도 1b에 도시된 형태와 같은 소자 분리 마스크 패턴을 형성한다.Next, a photolithography process is performed to pattern the silicon nitride film 30 and the pad oxide film 20 to form a device isolation mask pattern as illustrated in FIG. 1B.
도 1c에 도시된 바와 같이, 트렌치 소자분리 마스크 패턴에 의해 드러난 실리콘 기판(10)을 소정 깊이로 식각(예를 들면, 건식 식각)하여 트렌치(T)를 형성하고, 트렌치(T)를 포함하는 실리콘 기판(10)의 전면(즉, 실리콘 질화막(30)의 전면)에, 화학 기상 증착법(CVD)으로 산화막(40)을 증착한다.As illustrated in FIG. 1C, the silicon substrate 10 exposed by the trench isolation mask pattern is etched (for example, dry etched) to a predetermined depth to form a trench T, and includes a trench T. The oxide film 40 is deposited on the entire surface of the silicon substrate 10 (that is, the entire surface of the silicon nitride film 30) by chemical vapor deposition (CVD).
이어서, 트렌치(T)가 형성되지 않은 부위의 실리콘 질화막(30)이 노출될 때까지 산화막(40)을 CMP(Chemical Mechanical Polishing)공정으로 연마하여 도 1d에 도시된 바와 같이, 실리콘 질화막(30) 상부의 산화막(40)을 모두 제거한다.Subsequently, the oxide film 40 is polished by a chemical mechanical polishing (CMP) process until the silicon nitride film 30 of the portion where the trench T is not formed is exposed, and the silicon nitride film 30 is shown in FIG. 1D. All of the upper oxide film 40 is removed.
그 다음, 트렌치(T)가 형성되지 않은 실리콘 기판(10) 상부에 있는 실리콘 질화막(30)과 패드 산화막(20)을 식각 공정, 예를 들면 반응성 이온 식각(RIE : Reactive Ion Ething) 등으로 제거하여 도 1e에 도시된 바와 같이, 실리콘 기판(10)의 트렌치(T)에 만 산화막(40)을 남겨 STI(Shallow Trench Insulation) 구조의 소자 분리막(T｀)을 형성한다.Next, the silicon nitride layer 30 and the pad oxide layer 20 on the silicon substrate 10 where the trench T is not formed are removed by an etching process, for example, reactive ion etching (RIE). As shown in FIG. 1E, the isolation layer T ′ having a shallow trench insulation (STI) structure is formed by leaving the oxide film 40 only in the trench T of the silicon substrate 10.
이러한 소자분리 공정을 실시한 후에 도 1f에 도시된 바와 같이, 반도체 소자 공정시 요구되는 이온 주입 공정을 실시하는데, 이온 주입 공정을 진행하기에앞서 실리콘 기판(10) 전면에 버퍼(buffer) 작용을 하는 버퍼 산화막(50)을 열산화 공정으로 형성한다.After the device isolation process is performed, as shown in FIG. 1F, an ion implantation process required for the semiconductor device process is performed, and a buffer which acts as a buffer on the entire surface of the silicon substrate 10 before proceeding with the ion implantation process. The oxide film 50 is formed by a thermal oxidation process.
도 1g에 도시된 바와 같이, 버퍼 산화막(50)이 형성된 기판에 이온 주입 공정을 실시하여 기판에 요구되는 불순물층을 형성한 후에, 실리콘 기판(10)의 전면에 형성된 버퍼 산화막(50)을 제거하는데, 예를 들면 반응성 이온 식각(RIE) 등의 방법으로 제거한다.As shown in FIG. 1G, after performing an ion implantation process on a substrate on which the buffer oxide film 50 is formed to form an impurity layer required for the substrate, the buffer oxide film 50 formed on the entire surface of the silicon substrate 10 is removed. For example, it may be removed by a method such as reactive ion etching (RIE).
전술한 바와 같이, 종래 기술은 소자 분리막이 형성된 기판에 버퍼 산화막을 형성하고 나서 이온 주입 공정을 진행하는 바, 그 제조 공정이 복잡하고, 여러 공정을 거치게 됨에 따라 반도체소자의 제조 시간이 길어지는 단점이 있었다.As described above, the conventional technique is to form a buffer oxide film on the substrate on which the device isolation film is formed, and then proceed with the ion implantation process, and the manufacturing process is complicated, the manufacturing process of the semiconductor device is lengthened as it goes through various processes There was this.
본 발명의 목적은 상기와 같은 종래 기술의 문제점을 해결하기 위하여 소자분리 마스크 패턴으로 사용되는 패드 산화막을 제거하지 않고 이온 주입 공정시 버퍼 산화막으로 대체 활용함으로써 소자의 제조 공정 수를 단축할 수 있는 반도체 소자 제조 방법을 제공하고자 한다.An object of the present invention is to eliminate the pad oxide film used as the device isolation mask pattern in order to solve the problems of the prior art as described above, the semiconductor can reduce the number of manufacturing process of the device by replacing the buffer oxide film in the ion implantation process To provide a device manufacturing method.
이러한 본 발명의 목적을 달성하기 위한 본 발명은, 반도체 기판에 소자 분리막을 갖는 반도체 소자의 제조 방법에 있어서,The present invention for achieving the object of the present invention is a method for manufacturing a semiconductor device having an element isolation film on a semiconductor substrate,
상기 기판 상부에 패드 산화막과 질화막을 순차 증착하고 상기 적층된 질화막 및 패드 산화막을 식각해서 소자분리 마스크 패턴을 형성하는 단계와, 상기 소자분리 마스크 패턴에 의해 드러난 기판에 소자 분리막을 형성하는 단계와, 상기 질화막을 제거하는 단계와, 상기 소자 분리막이 형성된 기판내에 이온을 주입하고,상기 남아있는 소자분리 마스크 패턴의 패드 산화막을 제거하는 단계로 이루어진 반도체 소자의 제조 방법을 제공하고자 한다.Forming a device isolation mask pattern by sequentially depositing a pad oxide film and a nitride film on the substrate and etching the stacked nitride film and the pad oxide film, and forming a device isolation film on the substrate exposed by the device isolation mask pattern; It is to provide a method for manufacturing a semiconductor device comprising the step of removing the nitride film, implanting ions into the substrate on which the device isolation film is formed, and removing the pad oxide film of the remaining device isolation mask pattern.
도 1a 내지 1g는 종래 기술에 의한 소자 분리막 및 이온 주입 공정을 나타낸 공정 순서도,1A to 1G are process flowcharts illustrating a device isolation membrane and an ion implantation process according to the prior art;
도 2a 내지 2f는 본 발명에 따른 반도체 소자의 소자 분리막 및 이온 주입 공정을 나타낸 공정 순서도이다.2A to 2F are process flowcharts illustrating a device isolation layer and an ion implantation process of a semiconductor device according to the present invention.
＜도면의 주요부분에 대한 부호의 설명＞<Description of the code | symbol about the principal part of drawing>
10, 100 : 실리콘 기판 20, 102 : 패드 산화막10, 100: silicon substrate 20, 102: pad oxide film
30, 104 : 실리콘 질화막 40, 106 : 산화막30, 104 silicon nitride film 40, 106 oxide film
T : 트렌치 T' : 소자 분리막T: trench T ': device isolation
이하 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
도 2a 내지 2f는 본 발명에 따른 반도체 소자의 소자 분리막 및 이온 주입 공정을 나타낸 공정 순서도이다. 이들을 참조하여 본 발명에 따른 트렌치 구조의 소자분리막 및 이온 주입 공정에 대해 설명한다.2A to 2F are process flowcharts illustrating a device isolation layer and an ion implantation process of a semiconductor device according to the present invention. With reference to these, a device isolation membrane and an ion implantation process of a trench structure according to the present invention will be described.
도 2a에 도시된 바와 같이, 반도체 기판으로서 실리콘 기판(100)에 패드 산화막(102)과 실리콘 질화막(104) 순차 증착한다. 이때, 패드 산화막(102)은 실리콘 산화막(SiO2)으로써 열산화 공정에 의해 두께 50Å∼100Å로 형성되고, 실리콘 질화막(104)은 화학 기상 증착법(Chemical Vapor Deposition), 예를 들면 저압 화학 기상 증착법(LPCVD : Low Pressure Chemical Vapor Deposition), 상압 화학 기상 증착법(APCVD : Atmospheric Pressure Chemical Vapor Deposition) 등에 의해 형성된다.As shown in FIG. 2A, the pad oxide film 102 and the silicon nitride film 104 are sequentially deposited on the silicon substrate 100 as a semiconductor substrate. At this time, the pad oxide film 102 is a silicon oxide film (SiO 2 ) formed by a thermal oxidation process with a thickness of 50 kPa to 100 kPa, and the silicon nitride film 104 is formed by chemical vapor deposition (eg, low pressure chemical vapor deposition). (LPCVD: Low Pressure Chemical Vapor Deposition), Atmospheric Pressure Chemical Vapor Deposition (APCVD), or the like.
이후, 포토 리소그래피(photo lithography) 공정을 수행하여 실리콘 질화막(104) 및 패드 산화막(102)을 패터닝하여 도 2b에 도시된 형태와 같은 소자 분리 마스크 패턴을 형성한다.Thereafter, a photolithography process is performed to pattern the silicon nitride film 104 and the pad oxide film 102 to form a device isolation mask pattern as illustrated in FIG. 2B.
도 2c에 도시된 바와 같이, 트렌치 소자분리 마스크 패턴에 의해 드러난 실리콘 기판(100)을 소정 깊이로 식각하여 트렌치(T)를 형성하고, 트렌치(T)를 포함하는 실리콘 기판(100)의 전면에, 화학 기상 증착법(CVD)으로 산화막(106)을 증착한다.As shown in FIG. 2C, the silicon substrate 100 exposed by the trench isolation mask pattern is etched to a predetermined depth to form a trench T, and the front surface of the silicon substrate 100 including the trench T is formed. The oxide film 106 is deposited by chemical vapor deposition (CVD).
이어서, 트렌치(T)가 형성되지 않은 부위의 실리콘 질화막(104)이 노출될 때까지 산화막(106)을 CMP(Chemical Mechanical Polishing)로 연마하여 도 2d에 도시된 바와 같이, 실리콘 질화막(104) 상부의 산화막(106)을 모두 제거한다.Subsequently, the oxide film 106 is polished by CMP (Chemical Mechanical Polishing) until the silicon nitride film 104 of the portion where the trench T is not formed is exposed, and as shown in FIG. 2D, the upper portion of the silicon nitride film 104 is formed. All of the oxide film 106 is removed.
그 다음, 트렌치(T)가 형성되지 않은 실리콘 기판(100) 상부에 있는 실리콘 질화막(104)을 식각 공정, 예를 들면 반응성 이온 식각(RIE : Reactive Ion Ething) 등으로 제거하여 도 2e에 도시된 바와 같이, 실리콘 기판(100)의 트렌치(T)에 만 패드 산화막(102)을 남겨 STI(Shallow Trench Insulation) 구조의 소자 분리막(T｀)을 형성한다.Next, the silicon nitride film 104 on the silicon substrate 100 where the trench T is not formed is removed by an etching process, for example, reactive ion etching (RIE), and the like, as illustrated in FIG. 2E. As described above, only the pad oxide layer 102 is left in the trench T of the silicon substrate 100 to form an isolation layer T ′ having a shallow trench insulation (STI) structure.
소자 분리막(T')을 형성한 후, 이온 주입 공정을 실시하는데 있어서, 실리콘 질화막(104) 형성시에 스트레스(stress)를 줄이기 위해 형성된 패드 산화막(102)을 버퍼 산화막으로 사용하여 이온 주입 공정을 실시한다.After the device isolation film T 'is formed, the ion implantation process may be performed by using the pad oxide film 102 formed as a buffer oxide film to reduce stress when forming the silicon nitride film 104. Conduct.
도 2f에 도시된 바와 같이, 패드 산화막(102)이 형성된 기판에 이온 주입 공정을 실시하여 기판에 요구되는 불순물층을 형성한 후에, 실리콘 기판(100)에 형성된 패드 산화막(102)을 제거하는데, 예를 들면 반응성 이온 식각(RIE) 등의 방법으로 제거한다.As shown in FIG. 2F, after the ion implantation process is performed on the substrate on which the pad oxide film 102 is formed to form an impurity layer required for the substrate, the pad oxide film 102 formed on the silicon substrate 100 is removed. For example, it is removed by a method such as reactive ion etching (RIE).
이상 설명한 바와 같이, 본 발명은 소자 분리 마스크 패턴으로 사용되는 패드 산화막을 제거하지 않고 이온 주입 공정시 버퍼 산화막으로 대체 활용함으로써 반도체 소자의 제조 공정 수를 단축할 수 있는 효과가 있다.As described above, the present invention has the effect of shortening the number of manufacturing steps of the semiconductor device by replacing the pad oxide film used as the device isolation mask pattern with the buffer oxide film during the ion implantation process.
한편, 본 발명은 상술한 실시예에 국한되는 것이 아니라 후술되는 청구범위에 기재된 본 발명의 기술적 사상과 범주내에서 당업자에 의해 여러 가지 변형이 가능하다.On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11186400A (en) * | 1997-12-17 | 1999-07-09 | Sharp Corp | Manufacturing semiconductor device |
| JPH11289007A (en) * | 1998-04-02 | 1999-10-19 | Sony Corp | Manufacture of semiconductor device |
| KR20000019635A (en) * | 1998-09-14 | 2000-04-15 | 윤종용 | Method for simplifying gate oxide process of semiconductor device having trench isolation |
| KR20010038755A (en) * | 1999-10-27 | 2001-05-15 | 박종섭 | Fabricating method of semiconductor device |
| KR20010046070A (en) * | 1999-11-10 | 2001-06-05 | 박종섭 | Method for forming isolation region of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11186400A (en) * | 1997-12-17 | 1999-07-09 | Sharp Corp | Manufacturing semiconductor device |
| JPH11289007A (en) * | 1998-04-02 | 1999-10-19 | Sony Corp | Manufacture of semiconductor device |
| KR20000019635A (en) * | 1998-09-14 | 2000-04-15 | 윤종용 | Method for simplifying gate oxide process of semiconductor device having trench isolation |
| KR20010038755A (en) * | 1999-10-27 | 2001-05-15 | 박종섭 | Fabricating method of semiconductor device |
| KR20010046070A (en) * | 1999-11-10 | 2001-06-05 | 박종섭 | Method for forming isolation region of semiconductor device |
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