JPH11289007A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a highly-reliable semiconductor device of a trench isolation type structure. SOLUTION: The manufacturing method includes steps of forming a pad oxide film 102 on a semiconductor substrate 101, forming a film of material slower in polishing rate than a trench filling insulating material 106 on the pad oxide film, making a trench groove in a predetermined zone, depositing the trench filling insulating material so as to fill the trench groove, polishing the trench filling insulating material to form an element isolation region, removing the material slower in polishing rate than the trench filling insulating material, and forming an impurity diffusion region 108 by leaving the oxidized pad film and implanting ions into the element isolation region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor integrated circuit such as a memory element which has been highly miniaturized and integrated.

[0002]

2. Description of the Related Art A semiconductor device, for example, a semiconductor integrated circuit is conventionally manufactured by a LOCOS method (Local Oxidation
An element isolation region is formed by a non-silicon method. However, with the recent miniaturization and integration of semiconductor integrated circuits, fine element isolation is required, and the insulating layer is filled and formed between semiconductor elements or between required parts in semiconductor elements. (So-called trench method) has been widely performed.

The process of filling a trench with an insulator in a trench formed in a semiconductor substrate by the trench method has been performed as follows.

First, a pad oxide film is formed on a semiconductor substrate, and then a chemical mechanical polishing (hereinafter, referred to as “CMP”; Chemical M) from an insulator for filling a trench.
It is an abbreviation for mechanical polishing. A) a material having a high selectivity, for example, a film made of silicon nitride is formed thereon, a resist film is formed thereon, and a predetermined patterning is performed. A film made of a material having a high selectivity in CMP, a pad oxide film, and a semiconductor substrate are dry-etched.

Then, after removing the resist film,
An insulator for filling a trench, for example, silicon oxide 306 is deposited so as to fill the trench, and a silicon nitride film 3 is formed.
02 is exposed, that is, the surface of the trench filling insulator is polished by the CMP method using the film made of a material having a high selectivity to the trench filling insulator CMP as a stopper so that the surface of the trench filling insulator becomes flat. 10 (a)).

Next, as shown in FIG. 10 (b), after removing the film made of the material having a high selection ratio of the trench filling insulator CMP and the pad oxide film, the semiconductor substrate is oxidized again. 308 is formed.

Next, as shown in FIG. 11C, after a resist film 307 is formed, a predetermined region is masked, and ions are implanted through the formed oxide film 308 to form a well 309. Form. After that, the oxide film 3
08 is removed and a gate oxide film 310 is formed to complete trench isolation (FIG. 11D).

Here, the reason why the pad oxide film 302 is removed and the oxide film 308 is formed again is that the manufacturing process of the conventional LOCOS method is applied to the trench method as it is. That is, in the conventional LOCOS method, if the ion implantation is performed without removing the pad oxide film, the film quality of the gate oxide film formed in the subsequent process is deteriorated. After forming the film, ion implantation had to be performed.

[0009]

However, in the above-described conventional trench method, the insulator for filling the trench is simultaneously etched when the pad oxide film and the oxide film formed before the ion implantation are removed and etched. Another problem has arisen that the object surface may be more concave than the semiconductor substrate. As a result, a change in transistor characteristics and a decrease in gate withstand voltage are likely to occur.

Further, by increasing the thickness of the silicon nitride film serving as a stopper for polishing by the CMP method, the thickness of the device isolation film made of the insulator for filling the trench is increased (the height of the device isolation film is increased). Higher) is also conceivable. However, the removal etching of the pad oxide film and the oxide film formed before the ion implantation employs isotropic etching, so that the side wall is etched this time,
There is a possibility that a depression is formed near the boundary between the element isolation region and the element isolation film. The occurrence of such dents leads to fluctuations in transistor characteristics and a decrease in gate breakdown voltage.
Not preferred.

Further, a method of performing ion implantation in a state in which the semiconductor substrate is exposed without forming an oxide film before ion implantation can be considered. However, the damage of the ion implantation causes a decrease in the breakdown voltage of the gate insulating film and a reduction in reliability. Causes a decline.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and a method of manufacturing a trench isolation type semiconductor device, characterized in that a trench formed in a semiconductor substrate is filled with an insulator. It is an object of the present invention to provide a method of manufacturing a highly reliable semiconductor device having a trench isolation type structure with high reliability.

[0013]

According to the present invention, there is provided a process for forming an element isolation region by forming a trench in a semiconductor substrate and filling the trench with an insulator for filling the trench. Forming a pad oxide film on a semiconductor substrate; and forming a pad oxide film on the semiconductor substrate.
Forming a film made of a material having a lower polishing rate than the trench filling insulator, forming a trench in a predetermined region, and depositing a trench filling insulator to fill the trench; Polishing the trench-filling insulator to form an isolation region; removing a film made of a material having a lower polishing rate than the trench-filling insulator; and removing the pad oxide film from the device isolation region. And a method of manufacturing a semiconductor device having a trench isolation type structure.

In the method of manufacturing a semiconductor device having a trench isolation type structure according to the present invention, the thickness of the pad oxide film is preferably 20 μm or more, more preferably 20 to 50 n.
m. If the thickness of the pad oxide film is less than 20 μm, the surface of the semiconductor substrate is greatly damaged by ion implantation, and the quality of a gate oxide film formed in a subsequent step is undesirably deteriorated. On the other hand, if the film thickness exceeds 50 μm, the energy of ion implantation must be increased more than necessary, and mechanical damage on the surface of the semiconductor substrate is undesirably increased.

In the present invention, the pad oxide film is
Preferably, the film is mainly composed of silicon oxide. Also,
The insulator for filling the trench is preferably silicon oxide,
As a material having a lower polishing rate than the insulator for filling the trench, silicon nitride is preferable.

In the present invention, the step of polishing the insulator for filling the trench to form an element isolation region includes the following steps:
This is preferably a step of forming an element isolation region by polishing the insulator for filling a trench by a chemical mechanical polishing method.

In the method of manufacturing a semiconductor device according to the present invention, the step of removing the pad oxide film after forming an impurity diffusion region by ion-implanting the element isolation region while leaving the pad oxide film; Forming a gate oxide film in a region and forming a gate electrode in a predetermined region on the gate oxide film, for example, in the manufacture of a highly miniaturized and integrated semiconductor integrated circuit. Can be used. According to the present invention, a trench isolation type semiconductor device having a fine structure and excellent transistor characteristics can be manufactured with high yield.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in more detail with reference to embodiments. First embodiment

A first embodiment of the present invention will be described with reference to the drawings. First, as shown in FIG. 1A, a pad oxide film 102 made of silicon oxide is formed on a semiconductor substrate (p-type or n-type) 101 by, for example, a thermal oxidation method.
0 nm, and a film 103 made of a material having a higher selectivity in chemical mechanical polishing than an insulator for filling a trench is formed on the film 103 by, for example, CVD (Chemical Vap).
film thickness of 100 to 100 μm by our Deposition method.
It is formed with a thickness of 300 nm. Such materials include, for example,
Silicon nitride and the like can be given.

Next, as shown in FIG. 1B, a resist film 104 is formed on the entire surface. Subsequently, as shown in FIG. 1C, the element isolation region is masked and dry etching is performed. The film 103, the pad oxide film 102, and the semiconductor substrate 101 made of a material having a higher selectivity in chemical mechanical polishing than the insulator for filling the trench are etched to form a trench A having a depth of, for example, 300 nm in the semiconductor substrate 101. I do. The etching can be performed by, for example, RIE (reactive ion etching).

Next, as shown in FIG. 2D, after removing the resist film 104, the bottom and side walls of the trench A are thermally oxidized to form a silicon oxide film 105, for example. The thermal oxidation can be performed, for example, by heating to 1000 ° C. in a dry oxidation atmosphere containing 1% hydrochloric acid. The reason why the oxide film is formed inside the trench in this way is to recover the damage that has entered the silicon substrate during dry etching and to round the corner of the trench top.

Next, as shown in FIG. 2E, a trench filling, for example, a film 10 made of silicon oxide is formed on the entire surface.
6 is buried in the trench groove A, for example, O ₃
-Deposit about 600 nm in thickness by CVD of TEOS (tetraethoxysilane).

Thereafter, as shown in FIG. 3F, the film 106 made of the insulator for filling the trench is polished and flattened by chemical mechanical polishing (hereinafter referred to as "CMP method"). In this case, a film 102 made of a material having a lower polishing rate than the trench filling insulator, that is, a material having a high selectivity in the chemical mechanical polishing is provided, and the film 102 is selected from the trench filling insulator in the chemical mechanical polishing. Polishing is performed at a position where the film 102 made of a material having a high ratio is exposed.

Next, as shown in FIG. 3G, the film 102 made of a material having a higher selectivity in the chemical mechanical polishing than the insulator for filling the trench is removed by etching with, for example, a hot phosphoric acid solution. The step of forming the element isolation region by the trench method is completed.

Further, as shown in FIG. 4H, a resist film 107 is formed on the entire surface, only the region for forming the well is opened by patterning, and a well 108 is formed by ion implantation. In this case, the semiconductor substrate is n
A p-type impurity, for example, boron, and an n-type impurity, for example, phosphorus or arsenic if the semiconductor substrate is a p-type. Wells can be formed.

According to the conventional method, the pad oxide film is once removed before the ion implantation, and then the oxide film is formed again.
Ion implantation was performed using this as a mask. Since this conventional method requires a step of removing a pad oxide film and an oxide film formed before ion implantation, a trench filling insulator of the formed element isolation film is simultaneously etched, and the surface of the element isolation film is etched. Was sometimes more concave than the surface of the semiconductor substrate. In the manufacturing method of the present invention, the pad oxide film 102
Since the ion implantation is performed in a state where is left, the above-mentioned problem does not occur.

Thereafter, the resist film 107 and the pad oxide film 102 are removed by etching to form a gate oxide film 109. Finally, polysilicon (not shown) is deposited on the entire surface, a gate electrode is processed and formed, a source / drain region is formed, and ion implantation for Vth adjustment is performed to manufacture a desired MOS transistor. it can.

According to the present embodiment, a highly reliable trench isolation type semiconductor device having a fine element isolation structure can be manufactured with a high yield.

Second Embodiment A second embodiment is an example in which the manufacturing method of the present invention is applied to actual manufacturing of a CMOS integrated circuit. First, as shown in FIG. 5A, a 20 to 30 nm-thick pad oxide film 202 made of, for example, silicon oxide is formed on an n-type semiconductor substrate 201 by, for example, a thermal oxidation method. A film made of a material having a higher selectivity in chemical mechanical polishing than an insulator, for example, a film 2 made of silicon nitride
03, for example, with a film thickness of 150 to 200 n by a CVD method.
m.

Next, a resist film 204 is formed on the entire surface as shown in FIG. 5B, and after a predetermined patterning is performed, as shown in FIG. Film 203, pad oxide film 202 and n-type semiconductor substrate 201 are formed, for example, by RIE.
(Reactive Ion Etching) to form a trench B having a depth of about 300 nm.

Next, as shown in FIG. 6D, a trench filling insulator, for example, silicon oxide 205 is buried in the trench B, and the entire surface is formed by a CVD method using, for example, O ₃ -TEOS. Deposit about 600 nm.
Next, the trench filling 205 is polished and flattened by a CMP method to obtain a state sectional view shown in FIG. This CMP polishing is performed on the silicon nitride film 20.
3 is performed so as to stop at a position where it is exposed.

Further, as shown in FIG. 7F, the silicon nitride film 203 is removed using a hot phosphoric acid solution, thereby completing the step of forming the element isolation region by the trench method.

Next, as shown in FIG. 7G, after a resist film 207 is formed on the entire surface, a p-well formation region is opened, and a p-type impurity such as boron is ion-implanted. A p-well 209 is formed.

Also in this embodiment, since the ion implantation is performed without removing the pad oxide film 202 as in the first embodiment, extra etching such as etching removal of the pad oxide film and formation and etching removal of the oxide film are performed. It does not require a complicated process. Therefore, in a series of etching steps, the silicon oxide 205 constituting the element isolation film is excessively etched, so that there is no possibility that the breakdown voltage of the gate insulating film and the reliability are deteriorated.

Thereafter, the resist film 207 and the pad oxide film 202 are removed by etching, and the gate oxide film 208 made of silicon oxide is formed to a thickness of 1 by, for example, a thermal oxidation method.
By forming a film with a thickness of 0 to 20 nm, a state sectional view shown in FIG. 7H in which the p-well and the gate insulating film are formed is obtained.

Next, as shown in FIG. 8 (i), after depositing polysilicon on the entire surface by, eg, CVD, a resist film (not shown) is formed, predetermined patterning is performed, and etching is performed. , Gate electrode 2
Form 10.

Next, as shown in FIG. 8J, source / drain regions 211 to 214 are formed by predetermined ion implantation. Further, as shown in FIG.
For example, an interlayer insulating film 215 made of, for example, silicon oxide is formed by a CVD method, a resist film (not shown) is formed, predetermined patterning is performed, and etching is performed to form a contact hole C for connection.

Next, a conductive material made of, for example, aluminum is deposited on the entire surface by, for example, a sputtering method, and a predetermined process is performed to form a wiring layer 217 connecting the elements. Further, in order to prevent the deterioration of the semiconductor device, a passivation film 216 made of, for example, silicon oxide is
The film is formed by a method. As described above, the CMOS integrated circuit shown in FIG. 9L can be manufactured with high yield.

The CMOS integrated circuit manufactured according to this embodiment is a trench isolation type semiconductor integrated circuit having a fine element isolation structure, and has excellent transistor characteristics and reliability.

[0040]

As described above, the present invention relates to a method of manufacturing a trench isolation type semiconductor device, which has a step of implanting ions while leaving a pad oxide film.

In the conventional process, the pad oxide film is removed, an oxide film is formed again, and then ion implantation is performed.
The oxide film was removed and a gate oxide film was formed. Therefore, the trench insulating film (element isolation film) is reduced in a plurality of etching removal steps, and as a result, the breakdown voltage of the gate insulating film is reduced and the reliability is reduced.

According to the present invention, the step of etching the oxide film formed before the ion implantation can be eliminated, whereby the reduction in the thickness of the trench insulator can be reduced. Therefore, there is no possibility that the gate insulating film withstand voltage is reduced and the reliability is deteriorated, and a highly reliable semiconductor device having excellent gate insulating film withstand voltage can be manufactured.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing main steps of a method for manufacturing a semiconductor device according to the present invention. (A) is a diagram in which a film made of a material having a higher CMP selectivity than a pad oxide film and a trench filling is formed on a semiconductor substrate, (b) is a resist film formed from the state shown in (a), It is a figure which performed predetermined patterning, and (c) is a figure in which a trench was formed.

FIG. 2 is a sectional view showing main steps of a method for manufacturing a semiconductor device according to the present invention. FIG. 1D is a view in which an oxide film is formed inside the trench from the state shown in FIG.
FIG. 2 is a diagram in which a trench filling is deposited.

FIG. 3 is a sectional view of a main step in the method for manufacturing a semiconductor device of the present invention. FIG. 2F is a view in which the trench filling is polished and flattened by the CMP method from the state shown in FIG. 2E, and FIG. 2G is a film made of a material having a higher CMP selectivity than the trench filling. FIG. 4 is a diagram in which an element isolation region is formed by removing the element.

FIG. 4 is a sectional view of a main step in a method for manufacturing a semiconductor device of the present invention. FIG. 3H is a diagram in which a resist is formed from the state shown in FIG. 3G, predetermined patterning is performed, and ion implantation is performed, and FIG. 3I is a diagram in which a well is formed.

FIG. 5 is a sectional view showing main steps in which the manufacturing method of the present invention is applied to the manufacture of a CMOS integrated circuit. (A) is n
FIG. 2B is a diagram in which a pad oxide film and a silicon nitride film are formed on a mold semiconductor substrate, and FIG. 2B is a diagram in which a resist film is formed and then predetermined patterning for forming a trench formation region is performed.

FIG. 6 is a sectional view showing main steps in which the manufacturing method of the present invention is applied to the manufacture of a CMOS integrated circuit. (C) is a diagram in which a trench is formed, (d) is a diagram in which silicon oxide is deposited on the entire surface, and (e) is a diagram in which a silicon oxide film is polished and flattened by a CMP method. .

FIG. 7 is a sectional view showing main steps in which the manufacturing method of the present invention is applied to the manufacture of a CMOS integrated circuit. (F) is a view in which the silicon nitride film is removed, (g) is a view in which a predetermined patterning is performed after forming a resist, and ion implantation is performed in a well formation region, and (h) is a view in which p is formed. It is the figure which formed the well.

FIG. 8 is a sectional view of a main process in which the manufacturing method of the present invention is applied to the manufacture of a CMOS integrated circuit. (I) is a diagram in which a gate oxide film is formed in an element isolation region, polysilicon is deposited on the entire surface, and a gate electrode is formed by predetermined processing. (J) is a diagram in which a source / drain region is formed. FIG.

FIG. 9 is a sectional view showing main steps in which the manufacturing method of the present invention is applied to the manufacture of a CMOS integrated circuit. (K) is a view in which a contact hole is formed after forming an interlayer insulating film on the entire surface, and (l) is a view in which a passivation film is formed after forming a wiring layer.

FIG. 10 is a sectional view of a main step in a conventional method of manufacturing a trench isolation type semiconductor device. (A) is a diagram in which a trench filling insulator is polished and flattened by a CMP method, and (b) is a film and a pad made of a material having a higher selectivity in chemical mechanical polishing than the trench filling insulator. FIG. 3 is a view in which an oxide film is removed to form an oxide film.

FIG. 11 is a sectional view of a main step in a conventional method of manufacturing a trench isolation type semiconductor device. (C) is a diagram in which a resist film is formed, predetermined patterning is performed, and then ion implantation is performed. (D), after forming a well, an oxide film is removed and a gate oxide film is formed. FIG.

[Explanation of symbols]

101, 201, 301: semiconductor substrate, 102, 20
2,302 ... pad oxide film, 103, 203, 303 ...
Films made of a material having a polishing rate lower than that of the trench filling insulator, 104, 107, 204, 207.
05, 206, 305, 308: oxide films, 106, 20
5,306 ... Insulator for filling trench, 108,209,
309: well (impurity diffusion layer), 109, 208, 3
10: gate oxide film; 210: gate electrode;
12, 213, 214 ... source / drain regions, 215
... interlayer insulating film, 216 ... passivation film, 217 ...
Wiring layers A, B: trench groove, C: contact hole

Claims (8)

[Claims] A step of forming a pad oxide film on a semiconductor substrate; a step of forming a film made of a material having a lower polishing rate than a trench filling insulator on the pad oxide film; Forming a groove, depositing a trench filling insulator to fill the trench groove, polishing the trench filling insulator to form an element isolation region, and forming the trench filling insulator. A step of removing a film made of a material having a lower polishing rate; and a step of forming an impurity diffusion region by ion-implanting an element isolation region while leaving the oxide pad film. Production method. 2. The semiconductor device according to claim 1, wherein said pad oxide film has a thickness of at least two.
The method for manufacturing a semiconductor device having a trench isolation type structure according to claim 1, wherein the thickness is 0 μm or more. 3. The pad oxide film has a thickness of 20 μm to 5 μm.
The method for manufacturing a semiconductor device having a trench isolation type structure according to claim 1, wherein the thickness is 0 μm. 4. The method according to claim 1, wherein said trench filling insulator is silicon oxide. 5. The method of manufacturing a semiconductor device having a trench isolation type structure according to claim 1, wherein said pad oxide film is a film made of silicon oxide. 6. The method according to claim 1, wherein the material having a polishing rate lower than that of the trench filling insulator is silicon nitride. 7. The step of forming an element isolation region by polishing the insulator for filling a trench, wherein the step of forming the element isolation region is performed by polishing the insulator for filling a trench by a chemical mechanical polishing method. The method of manufacturing a semiconductor device having a trench isolation type structure according to claim 1. 8. A step of forming a pad oxide film on a semiconductor substrate; a step of forming a film made of a material having a lower polishing rate than a trench filling insulator on the pad oxide film; Forming a groove, depositing a trench filling insulator to fill the trench groove, polishing the trench filling insulator to form an element isolation region, and forming the trench filling insulator. A step of removing a film made of a material having a lower polishing rate, a step of forming an impurity diffusion region by ion-implanting the element isolation region while leaving the pad oxide film, and a step of removing the pad oxide film; Forming a gate oxide film in the element isolation region; and forming a gate electrode in a predetermined region on the gate oxide film. A method for manufacturing a semiconductor device.