KR20020059952A - Bonding pad of semiconductor memory device for improving adhesive strength bonding pad and bonding wire and method of manufacturing the same - Google Patents
Bonding pad of semiconductor memory device for improving adhesive strength bonding pad and bonding wire and method of manufacturing the same Download PDFInfo
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- KR20020059952A KR20020059952A KR1020010001131A KR20010001131A KR20020059952A KR 20020059952 A KR20020059952 A KR 20020059952A KR 1020010001131 A KR1020010001131 A KR 1020010001131A KR 20010001131 A KR20010001131 A KR 20010001131A KR 20020059952 A KR20020059952 A KR 20020059952A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000000853 adhesive Substances 0.000 title description 3
- 230000001070 adhesive effect Effects 0.000 title description 3
- 239000000463 material Substances 0.000 claims abstract description 14
- 239000004020 conductor Substances 0.000 claims abstract description 10
- 238000000059 patterning Methods 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims abstract 3
- 238000000034 method Methods 0.000 claims description 11
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 5
- 239000000758 substrate Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
- H01L2224/05089—Disposition of the additional element
- H01L2224/05093—Disposition of the additional element of a plurality of vias
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4845—Details of ball bonds
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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Abstract
Description
본 발명은 반도체 장치에 관한 것으로, 특히 반도체 장치의 본딩 패드에 단차를 만들어 와이어 본딩 시 본딩 패드와 본딩 와이어와의 접착력을 증가시키는 반도체 장치의 패드 및 이를 제조하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a pad of a semiconductor device and a method of manufacturing the same, by making a step on a bonding pad of a semiconductor device to increase adhesion between the bonding pad and the bonding wire during wire bonding.
반도체 장치에 있어서, 패드(pad)는 반도체 장치(device)의 동작 시 반도체 장치에 바이어스를 인가하기 위한 목적으로 사용된다. 또한, 상기 패드는패키지(package) 시에 본딩을 위한 본딩 와이어(bonding wire)가 접속되는 곳으로 사용되고, 반도체 소자를 테스트(test)하는 경우에는 프로빙(probing)을 위한 곳으로 사용된다.In a semiconductor device, a pad is used for the purpose of applying a bias to the semiconductor device during operation of the semiconductor device. In addition, the pad is used as a bonding wire (bonding wire) for bonding at the time of packaging (package), is used as a place for probing (testing) when testing a semiconductor device.
도 1은 종래의 반도체 장치의 본딩 패드의 구조를 나타내는 수직 단면도이다. 도 1을 참조하면, 반도체 장치의 본딩 패드 구조는 반도체 기판(1), 절연막(예컨대 inter- metal dielectric; 이하 'IMD'라 한다.), 콘택 물질(5), 본딩 패드(7) 및 본딩 와이어(9)를 구비하며, 도 1의 수직 단면도와 같이 차례로 적층된다.1 is a vertical cross-sectional view showing the structure of a bonding pad of a conventional semiconductor device. Referring to FIG. 1, a bonding pad structure of a semiconductor device may include a semiconductor substrate 1, an insulating film (for example, an inter-metal dielectric (hereinafter referred to as an “IMD”), a contact material 5, a bonding pad 7, and a bonding wire). (9) is provided and laminated one by one as in the vertical sectional view of FIG.
종래의 본딩 패드는 절연막(3) 및 콘택 물질(5)의 상부에 본딩 패드(7)가 평면 형태로 형성되므로, 본딩 패드(7)의 상부면의 본딩 와이어(9)도 평면형태로 형성된다. 따라서 와이어 본딩을 하는 경우 본딩 패드(7)와 본딩 와이어(9)의 접착력이 약하여 본딩 패드(7)와 본딩 와이어(9)가 분리되는 문제점이 있다.In the conventional bonding pad, since the bonding pad 7 is formed in a planar shape on the insulating film 3 and the contact material 5, the bonding wire 9 on the upper surface of the bonding pad 7 is also formed in a planar shape. . Therefore, in the case of wire bonding, there is a problem in that the bonding pad 7 and the bonding wire 9 have weak adhesive strength, so that the bonding pad 7 and the bonding wire 9 are separated.
본 발명이 이루고자하는 기술적 과제는 본딩 패드와 본딩 와이어의 접착면적을 증가시켜 본딩 패드와 본딩 와이어의 접착력을 증가시키는 반도체 장치의 패드 및 이를 제조하는 방법을 제공하는 것이다.SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a pad of a semiconductor device and a method of manufacturing the same, which increases the bonding area between the bonding pad and the bonding wire by increasing the bonding area of the bonding pad and the bonding wire.
도 1은 종래의 반도체 장치의 본딩 패드의 구조를 나타내는 수직 단면도이다.1 is a vertical cross-sectional view showing the structure of a bonding pad of a conventional semiconductor device.
도 2 내지 도 5는 본 발명의 일 실시예에 따른 반도체 장치의 본딩 패드를 제조하는 방법을 나타내는 도면이다.2 to 5 are diagrams illustrating a method of manufacturing a bonding pad of a semiconductor device according to an embodiment of the present invention.
6은 본 발명의 다른 실시예에 따른 반도체 장치의 본딩 패드를 나타내는 도면이다.6 is a diagram illustrating a bonding pad of a semiconductor device according to another embodiment of the present invention.
상기 기술적 과제를 이루기 위한 본 발명에 의한 반도체 장치의 패드 제조 방법은 패드가 형성될 소정의 위치에 사진 식각 기술을 이용하여 절연막을 패터닝하여 콘택 홀을 형성하는 단계 및 상기 콘택 홀 및 상기 절연막 상에 상기 패드를 형성할 도체를 도포하여, 상기 패드의 표면에 단차를 형성하는 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method of manufacturing a pad of a semiconductor device, the method including: forming a contact hole by patterning an insulating layer at a predetermined position where a pad is to be formed by using a photolithography technique and on the contact hole and the insulating layer It is characterized by applying a conductor to form the pad, to form a step on the surface of the pad.
상기 패드 제조 방법은 상기 콘택 홀에 소정의 콘택 물질을 채워 넣는 단계를 더 구비하며, 바람직하게는 상기 단차는 상기 콘택 홀에 의하여 생성된다.The pad manufacturing method further includes filling a predetermined contact material in the contact hole, preferably, the step is generated by the contact hole.
상기 다른 기술적 과제를 이루기 위한 본 발명에 의한 반도체 장치의 패드는 콘택홀 및 도전체를 구비한다. 상기 콘택홀은 패드가 형성될 소정의 위치에 사진 식각 기술을 이용하여 절연막을 패터닝하여 형성되며, 상기 도전체는 상기 콘택 홀 및 상기 절연막 상에 형성되고, 상기 패드의 표면에 상기 콘택 홀에 의하여 상기 단차가 형성된다.According to another aspect of the present invention, a pad of a semiconductor device includes a contact hole and a conductor. The contact hole is formed by patterning an insulating film using a photolithography technique at a predetermined position where a pad is to be formed, and the conductor is formed on the contact hole and the insulating film, and the surface of the pad is formed by the contact hole. The step is formed.
본 발명과 본 발명의 동작상의 이점 및 본 발명의 실시에 의하여 달성되는 목적을 충분히 이해하기 위해서는 본 발명의 바람직한 실시예를 예시하는 첨부 도면 및 첨부 도면에 기재된 내용을 참조하여야만 한다.In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예를 설명함으로써, 본 발명을 상세히 설명한다. 각 도면에 제시된 동일한 참조부호는 동일한 부재를 나타낸다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.
도 2 내지 도 5는 본 발명의 일 실시예에 따른 반도체 장치의 본딩 패드를 제조하는 방법을 나타내는 도면이다. 도 2를 참조하면, 절연막(13)은 본딩 패드(17)가 형성될 메탈층이나, 실리콘 기판과 같은 도체(11)의 위에 형성된다.2 to 5 are diagrams illustrating a method of manufacturing a bonding pad of a semiconductor device according to an embodiment of the present invention. Referring to FIG. 2, the insulating layer 13 is formed on the metal layer on which the bonding pad 17 is to be formed or on the conductor 11 such as a silicon substrate.
도 3은 실리콘 기판(11)위에 콘택 홀이 형성된 도면을 나타낸다. 콘텍 홀(contact hole)은 포토 레지스트(photo resist)를 절연막(13) 위에 도포하고, 회로의 패턴이 그려져 있는 마스크(mask) 또는 레티클(reticle)을 절연막(13) 위에놓고 노광(expose)하고, 현상(develop)한 뒤 절연막(13)을 식각(etch)한 후 포토 레지스트를 제거하고 세정하는 과정을 통하여 형성된다.3 shows a contact hole formed on the silicon substrate 11. The contact hole is a photo resist coated on the insulating film 13, a mask or a reticle on which the pattern of the circuit is drawn is placed on the insulating film 13, and exposed. After developing, the insulating layer 13 is etched, and then the photoresist is removed and cleaned.
도 4는 소정의 콘택 물질(15)이 도 3의 공정으로 만들어진 콘택 홀에 채워진 도면을 나타낸다. 도 4를 참조하면, 콘택 홀에 콘택 물질(15), 예컨대 텅스텐을 채워넣는 경우 콘택 홀을 종래의 콘택 홀보다 넓게 만들어 콘택 홀이 콘택 물질(15)에 의하여 완전히 채워지지 않게 하는 것이 바람직하다.FIG. 4 shows a view in which certain contact materials 15 are filled in contact holes made in the process of FIG. 3. Referring to FIG. 4, when the contact hole is filled with the contact material 15, for example, tungsten, it is preferable to make the contact hole wider than the conventional contact hole so that the contact hole is not completely filled by the contact material 15.
도 5는 본 발명의 실시예에 따른 반도체 장치의 본딩 패드를 나타내는 도면이다. 도 5를 참조하면, 본딩 패드(17)는 산화막(13)과 도 2 내지 4의 공정으로 만들어진 콘택물질(15)의 표면에 본딩 패드(17)를 형성할 도전체를 도포하여 생성된다. 그리고 본딩 와이어(19)는 본딩 패드(17)의 위에 적층된다.5 is a diagram illustrating a bonding pad of a semiconductor device in accordance with an embodiment of the present invention. Referring to FIG. 5, the bonding pads 17 are formed by coating an oxide film 13 and a conductor to form the bonding pads 17 on the surface of the contact material 15 formed by the process of FIGS. 2 to 4. And the bonding wire 19 is laminated on the bonding pad 17.
콘택 홀이 콘택 물질(15)에 의하여 완전히 채워지지 않았기 때문에, 절연막(13) 및 콘택 물질(15) 위에 본딩 패드(17)를 형성할 도체를 덮으면, 본딩 패드(17)의 표면에 콘택 물질(15)로 부분적으로 채워진 부분과 절연막(13)에 의한 부분으로 인하여 소정의 요철을 갖는 단차(20)가 자연스럽게 형성된다.Since the contact hole is not completely filled by the contact material 15, when the conductor to form the bonding pad 17 is covered on the insulating film 13 and the contact material 15, the surface of the bonding pad 17 A step 20 having a predetermined unevenness is naturally formed due to the part partially filled with 15) and the part by the insulating film 13.
따라서 소정의 단차(20)를 갖는 본딩 패드(17)가 형성되면, 와이어 본딩을 하는 경우에 본딩 와이어(19)와의 접촉 면적이 도 1의 본딩 패드(7)의 접촉면적보다 넓어져 본딩 패드(17)와 본딩 와이어와(19)의 접착력이 증가한다.Therefore, when the bonding pad 17 having the predetermined step 20 is formed, the contact area with the bonding wire 19 becomes larger than the contact area of the bonding pad 7 of FIG. 1 when the wire bonding is performed. 17) and the bonding wire 19 and the adhesive force increases.
도 6은 본 발명의 다른 실시예에 따른 반도체 장치의 본딩 패드를 나타내는 도면이다. 도 6을 참조하면, 본딩 패드는 콘택 물질(15)이 없는 것을 제외하면 도 5의 본딩 패드 및 이를 제조하는 방법과 유사하다.6 is a diagram illustrating a bonding pad of a semiconductor device according to another embodiment of the present invention. Referring to FIG. 6, the bonding pad is similar to the bonding pad of FIG. 5 and a method of manufacturing the same, except that the contact material 15 is absent.
도 6의 본딩 패드(19)는 도 2 및 도 3의 공정에 의하여 콘택 홀을 형성한다. 콘택 홀이 형성된 후 콘택 물질(15)을 콘택홀에 채워 넣지 않고, 직접 콘택 홀 및 절연막(13)의 표면에 본딩 패드(17)를 형성할 도체를 덮으면, 본딩 패드(17)의 표면에 소정의 단차(20)가 자연스럽게 형성된다.The bonding pads 19 of FIG. 6 form contact holes by the processes of FIGS. 2 and 3. After the contact hole is formed, the conductive material for forming the bonding pad 17 is directly covered on the surfaces of the contact hole and the insulating layer 13 without filling the contact material 15 in the contact hole. Step 20 is naturally formed.
따라서 소정의 단차(20)를 갖는 본딩 패드가 형성되면, 와이어 본딩 공정을 하는 경우 본딩 와이어(19)와의 접촉 면적이 도 1의 본딩 패드(7)의 접촉면적보다 넓어져 본딩 패드(17)와 본딩 와이어와(19)의 접착력이 증가한다. 따라서 본 발명의 실시에와 같이 본딩 패드의 구조를 변경하면, 패키지의 질을 향상시킬 수 있다.Therefore, when a bonding pad having a predetermined step 20 is formed, the contact area with the bonding wire 19 becomes wider than the contact area of the bonding pad 7 of FIG. 1 when the wire bonding process is performed. The adhesion between the bonding wires and 19 is increased. Therefore, by changing the structure of the bonding pad as in the embodiment of the present invention, the quality of the package can be improved.
본 발명은 도면에 도시된 일 실시 예를 참고로 설명되었으나 이는 예시적인 것에 불과하며, 본 기술 분야의 통상의 지식을 가진 자라면 이로부터 다양한 변형 및 균등한 타 실시 예가 가능하다는 점을 이해할 것이다. 따라서, 본 발명의 진정한 기술적 보호 범위는 첨부된 등록청구범위의 기술적 사상에 의해 정해져야 할 것이다.Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.
상술한 바와 같이 본 발명에 의한 단차를 구비하는 반도체 장치의 본딩 패드를 제조하는 방법 및 이 방법에 의하여 제조된 본딩 패드는 와이어 본딩을 하는 경우 본딩 와이어와의 접착력을 증가시키는 장점이 있다.As described above, the method of manufacturing a bonding pad of a semiconductor device having a step according to the present invention and the bonding pad manufactured by the method have an advantage of increasing adhesion to the bonding wire when wire bonding is performed.
Claims (6)
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| KR101034538B1 (en) * | 2010-06-01 | 2011-05-12 | 여흥레이저텍(주) | A tree protector for storing water |
| US9142489B2 (en) | 2012-08-10 | 2015-09-22 | Samsung Electronics Co., Ltd. | Semiconductor devices including a non-planar conductive pattern, and methods of forming semiconductor devices including a non-planar conductive pattern |
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| KR101933015B1 (en) | 2012-04-19 | 2018-12-27 | 삼성전자주식회사 | Pad structure of a semiconductor device, method of manufacturing the pad structure and semiconductor package including the pad structure |
| KR20200116577A (en) | 2019-04-01 | 2020-10-13 | 삼성디스플레이 주식회사 | Display device and method for manufacturing the same |
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| JPS6055634A (en) * | 1983-09-07 | 1985-03-30 | Nec Corp | Semiconductor integrated circuit device |
| JPS63283040A (en) * | 1987-05-15 | 1988-11-18 | Toshiba Corp | Semiconductor device |
| JPH04288843A (en) * | 1991-03-07 | 1992-10-13 | Mitsubishi Electric Corp | Semiconductor device |
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| KR101034538B1 (en) * | 2010-06-01 | 2011-05-12 | 여흥레이저텍(주) | A tree protector for storing water |
| US9142489B2 (en) | 2012-08-10 | 2015-09-22 | Samsung Electronics Co., Ltd. | Semiconductor devices including a non-planar conductive pattern, and methods of forming semiconductor devices including a non-planar conductive pattern |
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