CN111834316A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN111834316A CN111834316A CN201910313392.XA CN201910313392A CN111834316A CN 111834316 A CN111834316 A CN 111834316A CN 201910313392 A CN201910313392 A CN 201910313392A CN 111834316 A CN111834316 A CN 111834316A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
Abstract
The disclosure provides a semiconductor device and a manufacturing method thereof, and relates to the technical field of wafer packaging test. The semiconductor device includes: a substrate; a dielectric layer on a side remote from the substrate; a pad on the dielectric layer; a trap formed in the pad to divide the pad into a bonding pad and a testing pad. Form the trap in the pad, divide the pad into bonding pad and test pad for the area of probe injury can not influence each other with bonding pad, promotes the yield and the stability of chip.
Description
Technical Field
The present disclosure relates to semiconductor technologies, and particularly to a semiconductor device and a method for manufacturing the same.
Background
With the development of semiconductor technology, semiconductor devices are increasingly used in production and daily life. Semiconductor devices, such as chips and the like, generally require pad design, and connection to the outside is achieved by using the pad. However, the pad and the external connection line often have unstable connection, which affects the electrical connection between the pad and other external semiconductor components, and reduces the yield and stability of the semiconductor device.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
An object of the present disclosure is to provide a semiconductor device and a method for manufacturing the same, which overcome, at least to some extent, the technical problem of instability of the semiconductor device due to the limitations and disadvantages of the related art.
According to an aspect of the present disclosure, there is provided a semiconductor device including:
a substrate;
a dielectric layer on one side of the substrate;
the bonding pad is positioned on the surface of the dielectric layer far away from the substrate;
a trap formed in the pad to divide the pad into a bonding pad and a testing pad.
In an embodiment, the trap is rectangular or inverted trapezoid, the width of the trap is 1 um-20 um, the length of the trap is 30 um-80 um, and the height of the trap is 100 nm-6 um.
In an embodiment, the substrate includes a wiring layer including a bonding wire connected with the bonding pad by a conductive post passing through the dielectric layer.
In an embodiment, the semiconductor device further includes a protective layer on a side of the dielectric layer away from the substrate and exposing the pad.
In an embodiment, the material of the protective layer is one or more of polyimide and tetraethoxysilane.
In an embodiment, the semiconductor device further comprises a passivation layer located between the protective layer and the dielectric layer.
In an embodiment, a passivation layer is formed on sidewalls of the traps.
In an embodiment, the sidewalls of the traps are not covered with a passivation layer.
In an embodiment, the material of the bonding pad is one of copper, aluminum, tungsten, titanium, gold, silver, or an alloy of the above materials.
According to another aspect of the present disclosure, there is provided a semiconductor device manufacturing method including:
providing a substrate;
forming a dielectric layer on the substrate;
forming a pad layer on the dielectric layer;
forming a trap in the pad layer by etching, thereby dividing the pad layer into a bonding pad and a test pad through the trap.
In an embodiment, forming traps in the pad layer by etching includes:
forming a photoresist layer on the surface of the dielectric layer far away from the substrate;
exposing through a mask plate, and transferring the pattern of the mask plate to the photoresist layer;
developing to enable the photoresist layer to be exposed out of the region where the trap is to be formed;
etching, and forming the trap in the area to be provided with the trap;
and removing the photoresist layer.
In an embodiment, the forming of the trap in the pad layer by etching includes:
and forming a bonding pad by etching the bonding pad layer, and forming a trap in the bonding pad.
In an embodiment, the semiconductor device manufacturing method further includes:
forming a passivation layer on the pad and the dielectric layer;
depositing a protective layer on the passivation layer;
exposing and developing the protective layer to expose the passivation layer on the pad;
the exposed passivation layer is removed by etching to expose the pad.
In an embodiment, the passivation layer is a pad oxide layer or a pad silicon nitride layer, and the material of the protection layer is one or more of polyimide and tetraethoxysilane.
In an embodiment, the material of the bonding pad is one of copper, aluminum, tungsten, titanium, gold, silver, or an alloy of the above materials.
The pad layer is divided into the welding pad and the testing pad by forming the trap on the pad layer, so that the mutual influence of the probe damage area and the welding pad is avoided, and the stability of the chip is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.
Fig. 1 illustrates a cross-sectional view of a semiconductor device in the related art;
fig. 2 illustrates a cross-sectional view of a semiconductor device of one embodiment of the present disclosure;
fig. 3 illustrates a usage effect diagram of a semiconductor device according to an embodiment of the present disclosure;
fig. 4 shows a flow chart of a method of manufacturing a semiconductor device of one embodiment of the present disclosure;
FIG. 5 illustrates a flow chart of trap formation by a method of a mask-to-photolithography process in one embodiment of the present disclosure;
fig. 6A to 6J are sectional views showing stages in a method of manufacturing a semiconductor device according to another embodiment of the present disclosure;
fig. 7 illustrates a top view of a semiconductor device in one embodiment of the present disclosure;
fig. 8 illustrates a cross-sectional view of a semiconductor device of another embodiment of the present disclosure; and
fig. 9 shows a top view of a semiconductor device in another embodiment of the present disclosure.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus their repetitive description will be omitted.
In the related art, as shown in fig. 1, a pad 04 on a semiconductor device is generally used both as a test pad for making contact with a test probe and as a bonding pad for connecting with a conductive connection line 01. However, in the semiconductor device test, the contact of the test probe with the pad 04 easily causes damage 02 to the pad 04, such as generation of scratches or generation of fine dust. The pad damage 02 easily causes the connection between the pad 04 and the conductive connection line 01 to be insecure, the conductive connection line 01 (i.e. the packaging routing) is easy to fall off, the electrical connection between the semiconductor device and other external semiconductor components is affected, and the yield and the stability of the semiconductor device are reduced.
In the embodiment of the present disclosure, a semiconductor device including a pad structure is provided, as shown in fig. 2, the semiconductor device includes a substrate 301, a dielectric layer 302 on one side of the substrate 301; pads 308, 309 on the surface of the dielectric layer 302 remote from the substrate 301; and a trap 306 formed in the pad to divide the pad into a bonding pad 308 and a test pad 309.
In the pad structure in the above embodiment, the bonding pad 308 is used for being connected to the conductive connection line 01, the testing pad 309 is used for being contacted with the testing probe, and the bonding pad 308 and the testing pad 309 are isolated by the trap 306, so that even if the testing pad 309 is damaged 02 when being contacted with the testing probe, the bonding pad 308 is not affected, the bonding pad 308 can be effectively connected to the conductive connection line 01, and the yield and the stability of the semiconductor device are improved.
As shown in fig. 2, the substrate 301 may include a dielectric layer 3011 and a wiring layer 3012. The wiring layer 3012 may be provided between the dielectric layer 3011 and the dielectric layer 302.
The material of the dielectric layer 3011 may be selected and determined according to the design requirements of the semiconductor device, and may be an organic insulating material, an inorganic insulating material, or a mixed material of an organic insulating material and an inorganic insulating material. For example, in one embodiment, the material of the dielectric layer 3011 may be one of silicon oxide, silicon nitride, and silicon oxynitride, or any combination thereof. It is understood that the dielectric layer 3011 may be a layer of insulating material or a stack of layers of different insulating materials.
As shown in fig. 2, the wiring layer 3012 may include a bonding wire 3031, and the bonding wire 3031 may be connected to the bonding pad 308 for connection of the semiconductor device to an external circuit. The orthogonal projection of the bonding pad 308 on the wiring layer 3012 may at least partially overlap the bonding wire 3031, and the bonding pad 308 and the bonding wire 3031 may be connected by a first conductive pillar 304 passing through the dielectric layer 302.
When the first conductive pillar 304 is prepared, a first through hole may be formed in the dielectric layer 302, and the first through hole exposes a surface of the solder wire 3031; then, when the bonding pad 308 is formed, the material for forming the bonding pad 308 is filled in the first via hole to form the first conductive pillar 304. The first conductive pillar 304 not only can realize the connection between the bonding pad 308 and the bonding wire 3031, but also can realize the support of the bonding pad 308, so that when the conductive connection wire 01 is bonded or bonded to the bonding pad 308, the support force of the bonding pad 308 is effectively improved, and the yield of the semiconductor device is improved.
The material of the dielectric layer 302 may be selected and determined according to the design requirements of the semiconductor device, and may be an organic insulating material or an inorganic insulating material. For example, in an embodiment, the material of the dielectric layer 302 may be one of silicon oxide, silicon nitride and silicon oxynitride, or any combination thereof. It is understood that the dielectric layer 302 may be a layer of insulating material or a stack of layers of different insulating materials. As shown in fig. 2, the wiring layer 3012 may further include a test wiring 3032.
The trap 306 is located in the pad, dividing the pad into a bond pad 308 and a test pad 309. In one embodiment, the trap 306 may be rectangular or inverted trapezoidal, and in one embodiment, the width of the trap is 1um to 20um, the length of the trap is 30um to 80um, and the height of the trap is 100nm to 6 um. For example, the width of the trap may be 2um, 5um, 7um, 10um, 15um, or 18um, the length of the trap may be 30um, 40um, 50um, 60um, 70um, or 80um, and the height of the trap may be 100nm, 300nm, 500nm, 800nm, 1um, 3um, 5um, or 6 um.
As shown in fig. 3, when the test probe 03 moves to the edge of the test pad 309, it is restricted by the trap 306, so that the test probe 03 cannot reach the bonding pad 308 beyond the trap 306, and can only move in the area of the test pad 309, and thus the damage 02 can only be generated in the area of the test pad 309. Therefore, the possibility that the test probe 03 is mistakenly inserted into the welding pad 308 when the surface of the test pad 309 deviates can be reduced, the damage of the welding pad 308 is reduced, the structural integrity of the welding pad 308 is ensured, and the yield and the stability of the semiconductor device package are improved.
The bonding pad can be rectangular, and the length-width ratio is 1: 1-2: 1. In one embodiment, the pads are rectangular. Accordingly, the bonding pads 308 and the test pads 309 divided by the trap 306 may be square, for example, the bonding pads 308 and the test pads 309 may be square. The material of the bonding pads 308 and the testing pads 309 may be one of copper, aluminum, tungsten, titanium, gold, silver, or an alloy of the above materials.
In one embodiment, the semiconductor device further includes a protective layer 311 located on a side of the dielectric layer 302 away from the substrate 301 and exposing the pad, wherein a material of the protective layer 311 may be one or more of polyimide and tetraethoxysilane. In one embodiment, as shown in fig. 2, the semiconductor device further includes a passivation layer 310 located between the protective layer 311 and the dielectric layer 302. The passivation layer may be a pad silicon oxide layer or a pad silicon nitride layer. The passivation layer may be one or more layers. The side walls of the traps 306 are also formed with a passivation layer 307.
A method of forming the semiconductor device is described below with reference to the accompanying drawings.
Fig. 4 shows a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.
As shown in fig. 4, a substrate is provided, step S402.
The substrate may include a dielectric layer and a wiring layer, and the wiring layer and the dielectric layer may be one or more layers.
Step S404, a dielectric layer is formed on the substrate.
In particular implementations, the dielectric layer can be formed by chemical vapor deposition, atomic layer deposition, and the like. It will be appreciated that the dielectric layer may be a single layer of insulating material or a stack of layers of the same or different insulating materials. The material of the dielectric layer may be selected and determined according to the design requirements of the semiconductor device, and may be an organic insulating material or an inorganic insulating material. In an exemplary embodiment of the present disclosure, the material of the dielectric layer may be one or more of silicon oxide, silicon nitride, amorphous silicon, or silicon oxynitride.
In step S406, a pad layer on the dielectric layer is formed.
In one embodiment, the pad layer on the dielectric layer may be formed by physical vapor deposition, and the material of the pad layer may be one of copper, aluminum, tungsten, titanium, gold, silver, or an alloy of the above materials. In another embodiment, the pad layer on the dielectric layer may also be formed by electroplating.
Step S408 is to form a trap in the pad layer by etching, thereby dividing the pad layer into a bonding pad and a test pad by the trap.
Traps can be formed in the pad layer through a mask-photoetching process, and etching can be dry etching or wet etching. In one embodiment, the trap is rectangular or inverted trapezoidal, the width of the trap is 1um to 20um, the length of the trap is 30um to 80um, and the height of the trap is 100nm to 6 um.
In the embodiment, the trap is formed in the pad layer, so that the pad layer is divided into the welding pad and the testing pad, the area damaged by the probe and the welding pad cannot be influenced mutually, the yield and the stability of the chip are improved, and extra cost cannot be generated. The trap is naturally formed in the process of etching the bonding pad, an independent process is not needed, the cost is low, and the realization is convenient.
Figure 5 illustrates a flow chart of a method of forming traps by a mask-to-photolithography process in one embodiment of the present disclosure. As shown in fig. 5, the mask photolithography process may include:
step S5601, forming a photoresist layer on the surface of the pad layer;
step S5602, carrying out exposure through a corresponding mask plate, and transferring the pattern of the mask plate to a photoresist layer;
step S5603, exposing the photoresist layer to a region where a trap is to be formed through development;
step S5604, forming a trap by etching, wherein the etching can be dry etching, wet etching or plasma etching;
in step S5605, the photoresist layer is removed to obtain a trap.
Fig. 6A to 6J are sectional views showing stages in a method of manufacturing a semiconductor device according to another embodiment of the present disclosure.
As shown in fig. 6A, a substrate 301, and a dielectric layer 302 formed on the substrate 301 are provided. The substrate 301 includes a wiring layer, and the wiring layer includes a solder wire 3031 and a test wire 3032.
As shown in fig. 6B, a photoresist layer 320 is formed on the dielectric layer 302, and via pattern lithography is performed. And carrying out exposure development through the corresponding mask plate so as to transfer the pattern of the mask plate to the dielectric layer.
As shown in fig. 6C, a first via hole 304 is formed by etching, and the photoresist 320 is removed. The first through hole 304 communicates with the bonding wire 3031. By etching, the opening portion which is not covered and protected by the photoresist is removed, and the first via hole 304 is formed. The etching method may be dry etching, wet etching or plasma etching.
As shown in fig. 6D, the pad layer is formed by physical vapor deposition or electroplating, and the first via hole 304 is filled with a metal material such as copper, aluminum, tungsten, or the like during the deposition process.
As shown in fig. 6E, a photoresist layer 322 is formed on the pad layer 305.
As shown in fig. 6F, the photoresist layer 322 is subjected to pad pattern lithography. And exposing and developing through a corresponding mask plate, removing the photoresist outside the pad area, and simultaneously removing the photoresist in the area 323 to be provided with the trap.
As shown in fig. 6G, the material of the pad region is retained due to the photoresist coverage by etching away the material of the pad layer outside the pad region and forming a trap 306 in the pad. The trap 306 divides the pad area into a bond pad 308 and a test pad 309.
As shown in fig. 6H, a passivation layer 310 is formed over the dielectric layer 302, pads 308, 309 and traps 306. The passivation layer 310 may be one or more layers, and the material of the passivation layer 310 may be silicon oxide or silicon nitride. In one embodiment, the passivation layer includes a layer of silicon nitride and a layer of silicon oxide.
As shown in fig. 6I, a protection layer 311 is formed on the passivation layer 310, and the protection layer 311 is exposed, developed, and etched, thereby exposing the passivation layer 310 on the pad region and the trap region. The method for forming the protective layer can be chemical vapor deposition, atomic layer deposition and the like. The material of the protective layer may be one or more of polyimide (polyimide), tetraethyl orthosilicate (TEOS), and the like.
The exposed passivation layer 310 is removed by etching to expose the pad regions 308, 309 and traps 306 for testing and connecting wires, as shown in fig. 6J. The side walls of the traps 306 have a passivation layer 307.
In the embodiment, the trap is generated in the process of forming the bonding pad by etching, so that no additional process step is needed, no additional cost is generated, and the method has better advantages and effects.
A semiconductor device formed by a method similar to the above-described semiconductor manufacturing method is shown in fig. 6J, and includes a substrate 301, a dielectric layer 302 on a side remote from the substrate 301, the substrate 301 including a wiring layer 3012 and a dielectric layer 3011, the wiring layer 3012 including a solder wiring 3031 and a test wiring 3032; a first through hole 304 is formed in the dielectric layer 302, and the first through hole 304 communicates with the bonding wire 3031; pads 308, 309 on the dielectric layer 302, the first via 304 being filled with a pad material; a trap 306 is formed in the pad to divide the pad into a bonding pad 308 and a test pad 309.
In the embodiment, the trap is formed in the pad layer, and the pad is divided into the welding pad and the testing pad, so that the area damaged by the probe and the welding pad cannot be influenced mutually, and the yield and the stability of the chip are improved.
It should be noted that although the various steps of the methods of the present disclosure are depicted in the drawings in a particular order, this does not require or imply that these steps must be performed in this particular order, or that all of the depicted steps must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions, etc., are all considered part of this disclosure.
The present disclosure also provides a semiconductor device comprising any one of the pad structures described in the above pad structure embodiments. The semiconductor device may be a memory, a processor, or other semiconductor integrated circuit device.
The pad structure adopted by the semiconductor device of the embodiment of the present disclosure is the same as that in the embodiment of the pad structure, and therefore, the pad structure has the same beneficial effects, and details are not repeated herein.
Fig. 7 illustrates a top view of a semiconductor device in one embodiment of the present disclosure. As shown in fig. 7, the pad regions 308 and 309 are rectangular in top view, a protective layer 311 is formed outside, the trap 306 is formed in the pad region, the pad region is divided into two parts 308 and 309, which are respectively a bonding pad and a test pad, and the side wall of the trap 306 has a passivation layer 307. In one embodiment, the trap is rectangular or inverted trapezoidal. In one embodiment, the width of the trap is 1um to 20um, the length is 30um to 80um, and the height of the trap is 100nm to 6 um. In one embodiment, the bonding pad is rectangular and has an aspect ratio of 1:1 to 2: 1. In one embodiment, the pads are rectangular. In one embodiment, the trap 306 divides the pad into bond pads 308 having the same area as the test pads 309. In another embodiment, the area of the pad divided by the trap 306 into the bonding pad 308 is larger than the area of the testing pad 309, and the size of the specific bonding pad 308 and the area of the testing pad 309 need to be set according to the requirement of wire bonding, which is not limited in this disclosure.
Fig. 8 illustrates a cross-sectional view of a semiconductor device according to another embodiment of the present disclosure. Unlike the embodiment shown in fig. 2, in this embodiment the side walls of the traps 306 do not have the passivation layer 307, as shown in fig. 8. In the embodiment shown in fig. 6A to 6J, the passivation layer on the side wall of the trap 306 can be directly removed by etching in the step shown in fig. 6J. Fig. 9 shows a top view of the semiconductor device in this embodiment. As shown in fig. 9, the pad regions 308 and 309 are rectangular in top view, a protection layer 311 is formed outside, the trap 306 is formed in the pad region, the pad region is divided into two parts 308 and 309, which are respectively used as a bonding pad and a test pad, and the sidewall of the trap 306 is not covered with a passivation layer.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
Claims (15)
1. A semiconductor device, comprising:
a substrate;
a dielectric layer on one side of the substrate;
the bonding pad is positioned on the surface of the dielectric layer far away from the substrate;
a trap formed in the pad, dividing the pad into a bonding pad and a testing pad.
2. The semiconductor device according to claim 1, wherein the trap is rectangular or inverted trapezoidal, the width of the trap is 1um to 20um, the length of the trap is 30um to 80um, and the height of the trap is 100nm to 6 um.
3. The semiconductor device according to claim 1, wherein the substrate includes a wiring layer including a bonding wire connected to the bonding pad through a conductive pillar penetrating the dielectric layer.
4. The semiconductor device according to claim 1, further comprising a protective layer on a side of the dielectric layer away from the substrate and exposing the pad.
5. The semiconductor device according to claim 4, wherein the protective layer is made of one or more of polyimide and tetraethoxysilane.
6. The semiconductor device of claim 4, further comprising a passivation layer between the protective layer and the dielectric layer.
7. The semiconductor device of claim 6, wherein a passivation layer is formed on the sidewalls of the trap.
8. The semiconductor device of claim 6, wherein the sidewalls of the traps are not covered with a passivation layer.
9. The semiconductor device according to claim 1, wherein a material of the pad is one of copper, aluminum, tungsten, titanium, gold, and silver, or an alloy thereof.
10. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a dielectric layer on the substrate;
forming a pad layer on the dielectric layer;
forming a trap in the pad layer by etching, thereby dividing the pad layer into a bonding pad and a test pad through the trap.
11. The manufacturing method of a semiconductor device according to claim 10, wherein the forming of the trap in the pad layer by etching includes:
forming a photoresist layer on the surface of the dielectric layer far away from the substrate;
exposing through a mask plate, and transferring the pattern of the mask plate to the photoresist layer;
developing to enable the photoresist layer to be exposed out of the region where the trap is to be formed;
etching, and forming the trap in the area to be provided with the trap;
and removing the photoresist layer.
12. The manufacturing method of a semiconductor device according to claim 10, wherein the forming of the trap in the pad layer by etching comprises:
and forming a bonding pad by etching the bonding pad layer, and forming a trap in the bonding pad.
13. The manufacturing method of a semiconductor device according to claim 12, further comprising:
forming a passivation layer on the pad and the dielectric layer;
depositing a protective layer on the passivation layer;
exposing and developing the protective layer to expose the passivation layer on the pad;
the exposed passivation layer is removed by etching to expose the pad.
14. The method for manufacturing a semiconductor device according to claim 13, wherein the passivation layer is a pad silicon oxide layer or a pad silicon nitride layer, and the material of the protection layer is one or a combination of polyimide and tetraethoxysilane.
15. A method for manufacturing a semiconductor device according to claim 13, wherein a material of the bonding pad is one of copper, aluminum, tungsten, titanium, gold, and silver, or an alloy of the above materials.
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| CN201910313392.XA CN111834316A (en) | 2019-04-18 | 2019-04-18 | Semiconductor device and method for manufacturing the same |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023206976A1 (en) * | 2022-04-25 | 2023-11-02 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method for semiconductor structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2023206976A1 (en) * | 2022-04-25 | 2023-11-02 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method for semiconductor structure |
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