CN109360860B - Wafer packaging structure and preparation method thereof - Google Patents
Wafer packaging structure and preparation method thereof Download PDFInfo
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- CN109360860B CN109360860B CN201811113171.XA CN201811113171A CN109360860B CN 109360860 B CN109360860 B CN 109360860B CN 201811113171 A CN201811113171 A CN 201811113171A CN 109360860 B CN109360860 B CN 109360860B
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 150
- 238000002360 preparation method Methods 0.000 title claims abstract description 8
- 238000000034 method Methods 0.000 claims abstract description 23
- 230000008569 process Effects 0.000 claims abstract description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims description 40
- 238000005530 etching Methods 0.000 claims description 24
- 239000003292 glue Substances 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 239000011248 coating agent Substances 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 claims 3
- 239000002344 surface layer Substances 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 24
- 229910052710 silicon Inorganic materials 0.000 abstract description 22
- 239000010703 silicon Substances 0.000 abstract description 22
- 238000005336 cracking Methods 0.000 abstract description 10
- 235000012431 wafers Nutrition 0.000 description 256
- 238000010586 diagram Methods 0.000 description 6
- 239000000758 substrate Substances 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 238000010981 drying operation Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000012536 packaging technology Methods 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000006552 photochemical reaction Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0203—Containers; Encapsulations, e.g. encapsulation of photodiodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1876—Particular processes or apparatus for batch treatment of the devices
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Manufacturing & Machinery (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Packaging Frangible Articles (AREA)
Abstract
The embodiment of the invention discloses a wafer packaging structure and a preparation method thereof, wherein the wafer packaging structure comprises a wafer, and comprises a photosurface and a non-photosurface which is arranged opposite to the photosurface; the packaging cover plate is arranged on one side of the light sensitive surface of the wafer, and the vertical projection of the packaging cover plate on the plane of the wafer covers the wafer; and the groove structure is formed on the non-photosensitive surface of the wafer. By adopting the technical scheme, the wafer is covered by the vertical projection of the packaging cover plate on the plane of the wafer, so that the edge of the wafer is prevented from exceeding the edge of the packaging cover plate, the wafer is prevented from being impacted with other objects in the process of taking and transferring, the phenomena of silicon breakage and silicon cracking are avoided, the integrity of the wafer packaging structure is ensured, and the performance is stable.
Description
Technical Field
The embodiment of the invention relates to the technical field of wafer packaging, in particular to a wafer packaging structure and a preparation method thereof.
Background
Wafer level packaging (Wafer Level Packaging, WLP) technology is a technology in which a single finished chip is obtained by cutting after a package test is performed on the entire wafer, and the packaged chip size is completely consistent with the die. The wafer-level chip-scale packaging technology thoroughly overturns the modes of traditional packaging such as a ceramic leadless chip carrier (Ceramic Leadless Chip Carrier), an organic leadless chip carrier (Organic Leadless Chip Carrier) and the like, and meets the requirements of the market on increasing light, small, short, thinning and low price of microelectronic products. The chip size packaged by the wafer-level chip size packaging technology achieves high miniaturization, and the chip cost is obviously reduced along with the reduction of the chip size and the increase of the wafer size. Wafer-level chip-scale packaging technology is a technology capable of integrating IC design, wafer fabrication, package testing, and substrate fabrication, and is a hot spot in the current packaging field and a trend of future development.
In a wafer level chip package structure, a layer of package cover plate is generally bonded on a wafer as a protection structure to perform package protection on the wafer.
However, the size of the package cover is generally fixed, and for wafers of different manufacturers, the sizes of the wafers of some manufacturers are different, and the sizes of the wafers of some manufacturers are larger than the size of the package cover, so that the edge of the wafer protrudes out of the edge of the package cover, and silicon breakage and silicon cracking are easily caused when the wafer is in impact contact with other objects in the process of taking and transferring by a worker.
Disclosure of Invention
In view of the above, the embodiment of the invention provides a wafer packaging structure and a preparation method thereof, so as to solve the technical problem that the wafer is easy to crack and break when the wafer size is larger than the packaging cover plate in the prior art.
In a first aspect, an embodiment of the present invention provides a wafer packaging structure, including:
the wafer comprises a photosensitive surface and a non-photosensitive surface which is arranged opposite to the photosensitive surface;
the packaging cover plate is arranged on one side of the light sensitive surface of the wafer, and the vertical projection of the packaging cover plate on the plane of the wafer covers the wafer;
and the groove structure is formed on the non-photosensitive surface of the wafer.
Optionally, the non-photosensitive surface is divided into a plurality of center division areas located in the center area of the wafer and a plurality of edge division areas located in the edge area of the wafer by the groove structure, wherein the ratio between the coverage area of each edge division area and the coverage area of each center division area is greater than or equal to one third.
Optionally, the diameter of the packaging cover plate is L1, wherein L1 is more than or equal to 199.5mm and less than or equal to 200mm;
the diameter of the wafer is L2, wherein L2 which is 199mm or more is 199.5mm or less.
Optionally, a protruding pattern is formed on a side, facing the light sensitive surface of the wafer, of the packaging cover plate, packaging glue is covered on the surface of the protruding pattern, and packaging bonding is performed on the packaging cover plate and the wafer through the packaging glue.
Optionally, the shape of the center divided region includes a rectangle, and the shape of the edge divided region includes at least one of a curved trapezoid, a curved polygon, and a curved triangle.
Optionally, the packaging cover plate is packaging glass.
In a second aspect, an embodiment of the present invention further provides a method for manufacturing a wafer package structure, including:
providing a wafer, wherein the wafer comprises a photosurface and a non-photosurface which is arranged opposite to the photosurface;
preparing a packaging cover plate on one side of the photosensitive surface of the wafer;
etching the wafer on the non-photosensitive surface of the wafer so that the vertical projection of the packaging cover plate on the plane of the wafer covers the wafer, and forming a groove structure on the non-photosensitive surface of the wafer.
Optionally, etching the wafer on the non-photosensitive surface of the wafer so that the vertical projection of the packaging cover plate on the plane of the wafer covers the wafer, and forming a groove structure on the non-photosensitive surface of the wafer, including:
coating photoresist on the non-photosensitive surface of the wafer to form a photoresist layer;
exposing the photoresist layer by using a mask, wherein the covering size of the mask is smaller than that of the packaging cover plate, and the mask pattern of the mask is arranged corresponding to the groove structure;
developing the photoresist layer after exposure by using a developing solution;
etching the wafer, removing the edge area of the wafer, so that the vertical projection of the packaging cover plate on the plane of the wafer covers the wafer, and forming the groove structure on the non-photosensitive surface of the wafer.
Optionally, the mask pattern includes a center mask pattern located in a center region of the mask and an edge mask pattern located in an edge region of the mask, where a ratio between a coverage area of each edge mask region and a coverage area of each center mask region is greater than or equal to one third;
etching the wafer on the non-photosensitive surface of the wafer so that the vertical projection of the packaging cover plate on the plane of the wafer covers the wafer, forming a groove structure on the non-photosensitive surface of the wafer, and further comprising:
and controlling the groove structure to divide the non-photosensitive surface into a plurality of center dividing areas positioned in the center area of the wafer and a plurality of edge dividing areas positioned in the edge area of the wafer, wherein the ratio of the coverage area of each edge dividing area to the coverage area of the center dividing area is more than or equal to one third.
Optionally, preparing a packaging cover plate on one side of the photosensitive surface of the wafer, including:
providing a packaging cover plate;
preparing a convex pattern on one side of the packaging cover plate facing the light sensitive surface of the wafer;
and coating packaging glue on the surface of the convex pattern, and packaging and bonding the packaging cover plate and the wafer through the packaging glue.
Optionally, etching the wafer on the non-photosensitive surface of the wafer includes:
and etching the wafer on the non-photosensitive surface of the wafer by using a dry etching process.
According to the wafer packaging structure and the preparation method thereof, the wafer is covered by the vertical projection of the packaging cover plate on the plane of the wafer, so that the edge of the wafer cannot exceed the edge of the packaging cover plate, the wafer cannot be impacted with other objects in the process of taking and transferring, the phenomena of silicon breakage and silicon cracking cannot occur, the integrity of the wafer packaging structure is guaranteed, and the performance is stable.
Drawings
In order to more clearly illustrate the technical solution of the exemplary embodiments of the present invention, a brief description is given below of the drawings required for describing the embodiments. It is obvious that the drawings presented are only drawings of some of the embodiments of the invention to be described, and not all the drawings, and that other drawings can be made according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a wafer package structure in the prior art;
fig. 2 is a schematic structural diagram of a wafer package structure according to an embodiment of the present invention;
FIG. 3 is an enlarged schematic view of the wafer package structure provided in FIG. 2 in the area A;
fig. 4 is a schematic structural diagram of forming a bump pattern on a package cover according to an embodiment of the present invention;
fig. 5 is a flowchart of a method for manufacturing a wafer package according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be fully described below by way of specific embodiments with reference to the accompanying drawings in the examples of the present invention. It is apparent that the described embodiments are some, but not all, embodiments of the present invention, and that all other embodiments, which a person of ordinary skill in the art would obtain without making inventive efforts, are within the scope of this invention.
Fig. 1 is a schematic structural diagram of a wafer package structure in the prior art, as shown in fig. 1, the wafer package structure in the prior art may include a wafer 11 and a package cover 12 located on one side of the wafer, wherein a vertical projection of the package cover 12 on a plane on which the wafer 11 is located does not completely cover the wafer 11, and a size of the wafer 11 is larger than a size of the package cover 12.
Because the overall dimension of the wafer 11 is larger than that of the packaging cover plate 12, the wafer is opposite to the packaging cover plate 12, the edge of the wafer 11 protrudes out of the edge of the packaging cover plate 12, silicon breakage and silicon cracking are easily caused when the wafer packaging structure is in impact contact with other objects in the process of taking and transferring the wafer packaging structure, broken silicon foreign matters are introduced, and in some process links with pressing actions, the product is easily cracked due to the fact that hard foreign matters exist on the surface of the product, and the surface of the product is easily crushed due to stress.
Based on the technical problems, the embodiment of the invention provides a wafer packaging structure, which comprises a wafer, a first substrate, a second substrate and a third substrate, wherein the wafer comprises a photosurface and a non-photosurface which is arranged opposite to the photosurface; the packaging cover plate is arranged on one side of the light sensitive surface of the wafer, and the vertical projection of the packaging cover plate on the plane of the wafer covers the wafer; and the groove structure is formed on the non-photosensitive surface of the wafer. According to the technical scheme, the vertical projection of the packaging cover plate on the plane of the wafer is arranged to cover the wafer, so that the edge of the wafer cannot exceed the edge of the packaging cover plate, the wafer cannot be impacted with other objects in the process of taking and transferring, the phenomena of silicon breakage and silicon cracking cannot occur, the integrity of the wafer packaging structure is guaranteed, and the performance is stable.
The foregoing is the core idea of the present invention, and the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without making any inventive effort are intended to fall within the scope of the present invention.
Fig. 2 is a schematic structural diagram of a wafer package structure according to an embodiment of the present invention, as shown in fig. 2, the wafer package structure according to an embodiment of the present invention may include a wafer 21, including a photosurface and a non-photosurface opposite to the photosurface; the packaging cover plate 22 is arranged on one side of the light sensitive surface of the wafer 21, wherein the vertical projection of the packaging cover plate 22 on the plane of the wafer 21 covers the wafer 21; the trench structure 23 is formed on the non-photosensitive surface of the wafer 21.
For example, a package cover 22 is disposed on the photosensitive surface of the wafer 21, where the size of the package cover 22 is larger than that of the wafer 21, and as can be seen in fig. 2, the vertical projection of the package cover 22 on the plane of the wafer 21 covers the wafer 21, and the edge of the wafer 21 does not exceed the edge of the package cover 22, so that the wafer 21 will not collide with other objects during the process of picking and transferring. Specifically, in the direction perpendicular to the wafer 21, the thickness of the wafer 21 is about 100 μm, the thickness of the package cover 22 is 300 μm or 400 μm, the thickness of the package cover 22 is much greater than the thickness of the wafer 21, and the mechanical properties of the package cover 22 are much higher than those of the wafer 21. Therefore, the vertical projection of the packaging cover plate 22 on the plane of the wafer 21 covers the wafer 21, so that the edge of the wafer 21 can be prevented from exceeding the edge of the packaging cover plate 22, the wafer 21 and other objects can not be impacted in the process of taking and transferring the wafer packaging structure, the silicon breakage and silicon cracking of the wafer 21 can not occur, the integrity of the wafer packaging structure can be ensured, and the performance is stable.
Optionally, a trench structure 23 is formed on the non-photosensitive surface of the wafer 21, and the wafer package structure may be electrically connected to other devices outside through wiring in the trench structure 23.
In summary, according to the technical scheme of the embodiment of the invention, the wafer is covered by the vertical projection of the packaging cover plate on the plane of the wafer, so that the edge of the wafer is prevented from exceeding the edge of the packaging cover plate, the wafer is prevented from being impacted with other objects in the process of taking and transferring, the phenomena of silicon breakage and silicon cracking are prevented, the packaging structure of the wafer is ensured to be complete, and the performance is stable; meanwhile, the wafer packaging structure can be electrically connected with other devices outside through wiring in the groove structure, and normal use of the wafer packaging structure is guaranteed.
Optionally, with continued reference to FIG. 2, the package cover 22 has a diameter L1, wherein 199.5mm L1 is 200mm; the diameter of the wafer 21 is L2, wherein L2 which is 199mm or less is 199.5mm or less. The diameter of the packaging cover plate 22 is larger than that of the wafer 21, so that the packaging cover plate 22 can cover the wafer 21 completely, the phenomena of silicon breakage and silicon cracking of the wafer 21 are avoided, and the integrity of the wafer packaging structure and the stable performance are ensured.
Fig. 3 is an enlarged schematic view of the wafer package structure provided in fig. 2 in the area a, and as shown in fig. 2 and 3, the trench structure 23 divides the non-photosensitive surface into a plurality of center dividing regions 241 located in the center region of the wafer 21 and a plurality of edge dividing regions 242 located in the edge region of the wafer 21, where a ratio between a coverage area of each edge dividing region 242 and a coverage area of each center dividing region 241 is greater than or equal to one third. As shown in fig. 3, the plurality of edge dividing regions 242 are disposed around the center dividing region 241, and the ratio between the coverage area of each edge dividing region 242 and the coverage area of each center dividing region 241 is greater than or equal to one third, which can be understood that the wafer packaging structure provided by the embodiment of the invention removes the region with the smaller coverage area of the edge dividing region 242, specifically, removes the edge dividing region 242 with the coverage area less than one third of the coverage area of the center dividing region 241, so that the contact region with the packaging cover plate 22 is ensured to have a larger area, and has good bonding strength, the phenomenon that broken silicon chips fall in the region of the edge dividing region 242 is avoided, and the performance stability of the wafer packaging structure is ensured.
Alternatively, as shown with continued reference to fig. 2 and 3, the shape of the center segment 241 includes a rectangle, and the shape of the edge segment 242 includes at least one of a curved trapezoid, a curved polygon, and a curved triangle. It should be noted that, the shapes of the center dividing region 241 and the edge dividing region 242 are not limited in the embodiment of the present invention, only the ratio between the coverage area of each edge dividing region 242 and the coverage area of each center dividing region 241 is greater than or equal to one third, and it is ensured that the contact region with the package cover 22 is larger in both the center dividing region 241 and the edge dividing region 242, and the contact region has good bonding strength, and the broken silicon chip does not fall in the region of the edge dividing region 242.
Fig. 4 is a schematic structural diagram of forming a bump pattern on a package cover according to an embodiment of the present invention, as shown in fig. 4, a bump pattern 25 is formed on a side of a package cover 22 facing a wafer 21, a surface of the bump pattern 25 is coated with a packaging adhesive, and the package cover 22 and the wafer 21 are bonded by the packaging adhesive. The convex pattern 25 is formed on one side of the packaging cover plate 22 facing the wafer 21, and the packaging cover plate 22 and the wafer 21 are packaged by packaging glue coated on the surface of the convex pattern 25, so that the tightness of a photosensitive area on the photosensitive surface of the wafer 21 is protected, and moisture foreign matters are prevented from entering the photosensitive area.
Alternatively, the package cover 22 may be a package glass, and may also have a resin material or other optional materials, which is not limited in this embodiment of the present invention. Alternatively, the package cover 22 may be a one-layer or multi-layer structure, which is not limited in this regard as well.
Based on the same inventive concept, the embodiment of the present invention further provides a method for manufacturing a wafer package structure, as shown in fig. 5, where the method for manufacturing a wafer package structure provided by the embodiment of the present invention may include:
s110, providing a wafer, wherein the wafer comprises a photosurface and a non-photosurface which is arranged opposite to the photosurface.
S120, preparing a packaging cover plate on one side of the photosensitive surface of the wafer.
The packaging cover plate is prepared on one side of the light sensitive surface of the wafer, a convex pattern is prepared on one side of the packaging cover plate facing the light sensitive surface of the wafer, packaging glue is coated on the surface of the convex pattern, the packaging cover plate and the wafer are aligned and attached through the packaging glue, the tightness of a light sensitive area on the light sensitive surface of the wafer is protected, and moisture foreign matters are prevented from entering the light sensitive area.
And S130, etching the wafer on the non-photosensitive surface of the wafer so that the vertical projection of the packaging cover plate on the plane of the wafer covers the wafer, and forming a groove structure on the non-photosensitive surface of the wafer.
The wafer is etched on the non-photosensitive surface of the wafer, the edge area of the wafer is etched, the size of the wafer is guaranteed to be smaller than that of the packaging cover plate, the wafer can be covered by the vertical projection of the packaging cover plate on the plane of the wafer, the thickness of the wafer is about 100 mu m in the direction perpendicular to the wafer, the thickness of the packaging cover plate is 300 mu m or 400 mu m, the thickness of the packaging cover plate is far greater than that of the wafer, and meanwhile, the mechanical property of the packaging cover plate is far higher than that of the wafer. Therefore, the vertical projection of the packaging cover plate on the plane of the wafer covers the wafer, the edge of the wafer can be prevented from exceeding the edge of the packaging cover plate, the wafer packaging structure is prevented from being impacted with other objects in the process of taking and transferring, the silicon breakage and silicon cracking of the wafer are prevented, the integrity of the wafer packaging structure is ensured, and the performance is stable.
Meanwhile, a groove structure is formed on the non-photosensitive surface of the wafer, and the wafer packaging structure can be electrically connected with other external devices through wiring in the groove structure, so that the normal use of the wafer packaging structure is ensured.
According to the preparation method of the wafer packaging structure, the wafer is etched through the non-photosensitive surface of the wafer, the edge area of the wafer is etched, so that the wafer is covered by the vertical projection of the packaging cover plate on the plane of the wafer, the edge of the wafer is prevented from exceeding the edge of the packaging cover plate, the wafer and other objects are prevented from being impacted in the process of taking and transferring the wafer packaging structure, the phenomena of silicon breakage and silicon cracking of the wafer are avoided, the integrity of the wafer packaging structure is ensured, and the performance is stable; meanwhile, the wafer packaging structure can be electrically connected with other devices outside through wiring in the groove structure, and normal use of the wafer packaging structure is guaranteed.
Optionally, etching the wafer on the non-photosensitive surface of the wafer to enable the vertical projection of the packaging cover plate on the plane of the wafer to cover the wafer, and forming a groove structure on the non-photosensitive surface of the wafer may include:
coating photoresist on the non-photosensitive surface of the wafer to form a photoresist layer;
exposing the photoresist layer by using a mask, wherein the coverage size of the mask is smaller than that of the packaging cover plate, and the mask pattern of the mask is arranged corresponding to the groove structure;
developing the photoresist layer after exposure by using a developing solution;
etching the wafer to remove the edge area of the wafer, so that the vertical projection of the packaging cover plate on the plane of the wafer covers the wafer, and a groove structure is formed on the non-photosensitive surface of the wafer.
Illustratively, photoresist is coated on the whole surface of the non-photosensitive surface of the wafer to obtain a photoresist layer arranged on the whole surface. The photoresist may be either a positive photoresist or a negative photoresist, which is not limited in the embodiments of the present invention.
And carrying out exposure treatment on the photoresist layer by adopting a mask plate, wherein the covering size of the mask plate is smaller than the size of the packaging cover plate. Before the wafer is etched, the covering size of the wafer is larger than that of the packaging cover plate, and the covering size of the mask plate is smaller than that of the packaging cover plate, so that the size of the mask plate is smaller than that of the wafer, the mask plate cannot cover the non-photosensitive surface of the wafer completely, and the edge area of the wafer is not covered by the mask plate. Meanwhile, the mask pattern on the mask plate corresponds to a groove structure to be formed on the non-light-sensitive surface of the wafer, and after the mask plate is used for exposing the photoresist layer, the photoresist layer in the area which is not covered by the mask plate reacts, for example, the photoresist layer in the edge area of the wafer reacts; at the same time, the photoresist layer in the region corresponding to the trench structure also reacts. In this case, the photoresist is positive photoresist, the photoresist at the position of the transparent part of the mask plate is subjected to photochemical reaction, the photoresist at the position of the opaque part of the mask plate is not subjected to reaction, and the photoresist subjected to photochemical reaction is dissolved in the developing solution and removed.
And developing the photoresist layer after exposure by using a developing solution, so that the photoresist layer corresponding to the edge area of the wafer and the groove structure can be completely removed. After the photoresist layer is developed by using the developing solution, spin-drying operation is required, and the photoresist layer corresponding to the edge area of the wafer is completely removed in the developing process, so that photoresist damage can not occur in the spin-drying operation process, and pollution to the wafer packaging structure due to the photoresist damage can not be caused.
Etching the wafer, wherein the photoresist layer corresponding to the edge area of the wafer is completely removed, so that the edge area of the wafer can be removed by etching the wafer, and the vertical projection of the packaging cover plate on the plane of the wafer can be ensured to completely cover the wafer; meanwhile, as the wafer in the actual product is covered by the mask, namely the central functional area of the wafer, an oxide layer exists, and the photoresist layer at the position corresponding to the groove structure is completely removed, the oxide layer can block further etching because the oxide layer exists on the wafer in the mask covered area, so that the groove structure can be formed on the non-photosensitive surface of the wafer by etching the wafer, the wafer can not be completely etched and hollowed out, and the groove structure is ensured to be formed on the non-photosensitive surface of the wafer.
Because the shape and the size of the mask plate are completely controllable, the mask plate is used for carrying out exposure treatment on the photoresist layer, so that the photoresist layer at the edge area of the wafer can be ensured to be completely exposed, on one hand, the photoresist at the edge area of the wafer can be ensured to be completely removed in the subsequent etching process, the problem of edge photoresist breakage can not occur in the spin-drying operation process, and the wafer cannot be polluted; on the other hand, the groove structure can be formed on the non-photosensitive surface of the wafer at the same time, so that the normal use of the wafer packaging structure is ensured.
Optionally, the mask pattern comprises a central mask pattern located in a central region of the mask and an edge mask pattern located in an edge region of the mask, wherein the ratio between the coverage area of each edge mask region and the coverage area of each central mask region is greater than or equal to one third;
etching the wafer on the non-photosensitive surface of the wafer so that the vertical projection of the packaging cover plate on the plane of the wafer covers the wafer, and forming a groove structure on the non-photosensitive surface of the wafer, and further comprising:
the control groove structure divides the non-photosensitive surface into a plurality of center division areas positioned in the center area of the wafer and a plurality of edge division areas positioned in the edge area of the wafer, wherein the ratio of the coverage area of each edge division area to the coverage area of the center division area is more than or equal to one third.
The mask pattern on the mask plate can be further arranged to ensure that the ratio of the coverage area of each edge mask area to the coverage area of each center mask area is more than or equal to one third, so that after the mask plate is used for mask etching the photoresist layer, a plurality of center division areas positioned in the center area of the wafer and a plurality of edge division areas positioned in the edge area of the wafer can be formed on the non-photosensitive surface of the wafer, wherein the ratio of the coverage area of each edge division area to the coverage area of the center division area is more than or equal to one third, the coverage area of the edge division area of the wafer is ensured to be larger, and therefore, the contact area with a packaging cover plate is ensured to have good bonding strength, the phenomenon that broken silicon chips fall off in the edge division area is avoided, and the stability of the packaging structure of the wafer is ensured. Optionally, etching the wafer on the non-photosensitive surface of the wafer may include:
and etching the wafer on the non-photosensitive surface of the wafer by using a dry etching process.
Optionally, preparing a packaging cover plate on a photosensitive surface side of the wafer may include:
providing a packaging cover plate;
preparing a convex pattern on one side of the packaging cover plate facing the light sensitive surface of the wafer;
and coating packaging glue on the surface of the convex pattern, and packaging and bonding the packaging cover plate and the wafer through the packaging glue.
By way of example, the convex pattern is formed on one side of the packaging cover plate facing the wafer, and packaging adhesive coated on the surface of the convex pattern is used for packaging and bonding the packaging cover plate and the wafer, so as to protect the tightness of the photosensitive area on the photosensitive surface of the wafer and prevent moisture foreign matters from entering the photosensitive area.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, and that various obvious changes, rearrangements, combinations, and substitutions can be made by those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (8)
1. The wafer packaging structure is characterized by comprising:
the wafer comprises a photosensitive surface and a non-photosensitive surface which is arranged opposite to the photosensitive surface;
the packaging cover plate is arranged on one side of the light sensitive surface of the wafer, and the vertical projection of the packaging cover plate on the plane of the wafer covers the wafer;
the groove structure is formed on the non-photosensitive surface of the wafer;
the wafer packaging structure is connected with other devices outside through wiring in the groove structure;
the groove structure divides the non-photosensitive surface into a plurality of center division areas positioned in the center area of the wafer and a plurality of edge division areas positioned in the edge area of the wafer, wherein the ratio of the coverage area of each edge division area to the coverage area of each center division area is more than or equal to one third;
the wafer packaging structure removes the edge dividing region with the coverage area smaller than one third of the coverage area of the center dividing region.
2. The wafer package structure of claim 1, wherein the package cover has a diameter L1, wherein 199.5mm ∈l1 ∈200mm;
the diameter of the wafer is L2, wherein L2 which is 199mm or more is 199.5mm or less.
3. The wafer packaging structure according to claim 1, wherein a protruding pattern is formed on a side, facing the light sensitive surface of the wafer, of the packaging cover plate, packaging glue is covered on a surface layer of the protruding pattern, and packaging bonding is performed between the packaging cover plate and the wafer through the packaging glue.
4. The wafer package structure of claim 1, wherein the shape of the center split region comprises a rectangle and the shape of the edge split region comprises at least one of a curved trapezoid, a curved polygon, and a curved triangle.
5. The wafer package structure of claim 1, wherein the package cover is a package glass.
6. The preparation method of the wafer packaging structure is characterized by comprising the following steps:
providing a wafer, wherein the wafer comprises a photosurface and a non-photosurface which is arranged opposite to the photosurface;
preparing a packaging cover plate on one side of the photosensitive surface of the wafer;
etching the wafer on the non-photosensitive surface of the wafer so that the vertical projection of the packaging cover plate on the plane of the wafer covers the wafer, and forming a groove structure on the non-photosensitive surface of the wafer;
etching the wafer on the non-photosensitive surface of the wafer so that the vertical projection of the packaging cover plate on the plane of the wafer covers the wafer, and forming a groove structure on the non-photosensitive surface of the wafer, wherein the method comprises the following steps:
coating photoresist on the non-photosensitive surface of the wafer to form a photoresist layer;
exposing the photoresist layer by using a mask, wherein the covering size of the mask is smaller than that of the packaging cover plate, and the mask pattern of the mask is arranged corresponding to the groove structure;
developing the photoresist layer after exposure by using a developing solution;
etching the wafer, removing the edge area of the wafer, so that the vertical projection of the packaging cover plate on the plane of the wafer covers the wafer, and forming a groove structure on the non-photosensitive surface of the wafer;
the mask pattern comprises a central mask pattern positioned in the central region of the mask and an edge mask pattern positioned in the edge region of the mask, wherein the ratio of the coverage area of each edge mask region to the coverage area of each central mask region is more than or equal to one third;
etching the wafer on the non-photosensitive surface of the wafer so that the vertical projection of the packaging cover plate on the plane of the wafer covers the wafer, forming a groove structure on the non-photosensitive surface of the wafer, and further comprising:
and controlling the groove structure to divide the non-photosensitive surface into a plurality of center dividing areas positioned in the center area of the wafer and a plurality of edge dividing areas positioned in the edge area of the wafer, wherein the ratio of the coverage area of each edge dividing area to the coverage area of the center dividing area is more than or equal to one third.
7. The method of manufacturing as claimed in claim 6, wherein manufacturing a package cover plate on a photosensitive surface side of the wafer comprises:
providing a packaging cover plate;
preparing a convex pattern on one side of the packaging cover plate facing the light sensitive surface of the wafer;
and coating packaging glue on the surface of the convex pattern, and packaging and bonding the packaging cover plate and the wafer through the packaging glue.
8. The method of manufacturing according to claim 6, wherein etching the wafer at the non-photosensitive surface of the wafer comprises:
and etching the wafer on the non-photosensitive surface of the wafer by using a dry etching process.
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