KR20020058316A - Method for forming the Isolation Layer of Semiconductor Device - Google Patents
Method for forming the Isolation Layer of Semiconductor Device Download PDFInfo
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- KR20020058316A KR20020058316A KR1020000086382A KR20000086382A KR20020058316A KR 20020058316 A KR20020058316 A KR 20020058316A KR 1020000086382 A KR1020000086382 A KR 1020000086382A KR 20000086382 A KR20000086382 A KR 20000086382A KR 20020058316 A KR20020058316 A KR 20020058316A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
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Abstract
Description
본 발명은 얕은 트렌치 소자격리(Sallow Trench Isolation; 이하 "STI"라 한다)공정에 의해 반도체기판에 소자분리막 프로파일(profile)을 구현하는 과정에서 트렌치를 매립산화막인 고밀도플라즈마-화학기상증착-산화막으로 매립한 후 매립산화막 표면의 가운데 부분에 인을 이온주입하므로서 질화막 식각과 산화막 세정 시 가운데 부분의 식각율이 빨라져서 산화막이 평탄화되어 소자분리막 모서리 부분의 모우트 형상을 제거할 수 있는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법에 관한 것이다.The present invention provides a high-density plasma-chemical vapor deposition-oxide film as a buried oxide film in the process of implementing a device isolation film profile on a semiconductor substrate by a shallow trench isolation (STI) process. A semiconductor characterized in that the etch rate of the center portion is increased by etching the nitride film and cleaning the oxide film by implanting phosphorus into the center portion of the buried oxide film after being buried, so that the oxide film is flattened to remove the moat shape at the corners of the isolation layer. A device isolation film formation method of a device is provided.
일반적으로, 실리콘기판 상에 트렌지스터와 커패시터등을 형성하기 위하여 실리콘기판에는 전기적으로 통전이 가능한 활성영역과 전기적으로 통전되는 것을 방지하고 소자를 서로 분리하도록 하는 소자분리영역을 형성하게 된다.In general, in order to form transistors, capacitors, and the like on a silicon substrate, an silicon isolation region is formed in the silicon substrate to prevent electrically conduction from an electrically conductable active region and to separate devices from each other.
이와 같이, 실리콘기판에 일정한 깊이를 갖는 트렌치를 형성하고서 이 트렌치에 매립산화막을 증착시킨 후 화학기계적연마공정으로 매립산화막의 불필요한 부분을 식각하므로 소자분리영역을 실리콘 기판에 형성시키는 STI(Shallow Trench Isolation)공정이 최근에 많이 이용되고 있다.In this manner, a trench having a predetermined depth is formed on the silicon substrate, and a buried oxide film is deposited on the trench, and then an unnecessary portion of the buried oxide film is etched by a chemical mechanical polishing process, thereby forming an isolation region on the silicon substrate. The process is recently used a lot.
종래의 반도체장치에서 트렌치를 형성하여 소자분리막을 형성하는 상태를 개략적으로 설명하면, 실리콘 기판 상에 소정의 두께를 갖고서 절연을 하도록 패드산화막을 적층하고, 그 위에 상,하층간에 보호 역할을 하는 질화막을 적층하고서, 그 위에 감광막을 도포하여서 식각공정을 통하여 트렌치를 형성한다.In the semiconductor device according to the related art, a trench is formed to form a device isolation layer. In this case, a pad oxide film is stacked on the silicon substrate to be insulated with a predetermined thickness, and a nitride film acts as a protective layer between the upper and lower layers. Are laminated, and a photoresist film is applied thereon to form a trench through an etching process.
그리고, 상기 트렌치 내에 갭필링(Gap Filling)공정으로 갭필링산화막을 충전시킨 후에 식각으로 불필요한 부분을 제거하여 소자분리막을 형성하게 되는 것이다.In addition, after filling the gap filling oxide film by a gap filling process in the trench, an unnecessary portion is removed by etching to form an isolation layer.
도 1a 내지 도 1c는 종래에 반도체 소자의 소자분리막 형성방법을 순차적으로 나타낸 단면도이다.1A to 1C are cross-sectional views sequentially illustrating a method of forming a device isolation film of a semiconductor device in the related art.
도 1a에 도시된 바와 같이, 실리콘기판(1) 상에 패드질화막(3)을 적층한 후 감광막(5)을 적층하여서 소자분리막이 형성될 부위에 감광막(5)의 패턴을 형성하도록 한다.As shown in FIG. 1A, after the pad nitride layer 3 is laminated on the silicon substrate 1, the photoresist layer 5 is laminated to form a pattern of the photoresist layer 5 on a portion where the device isolation layer is to be formed.
그리고, 도 1b에 도시된 바와 같이, 상기 감광막(5) 패턴을 통하여 패드질화막(3)과 실리콘기판(1)을 일정 깊이로 식각한 후 그 트렌치(7) 내부에 매립산화막(9)을 매립하도록 한다.As shown in FIG. 1B, the pad nitride layer 3 and the silicon substrate 1 are etched to a predetermined depth through the photosensitive layer 5 pattern, and the buried oxide layer 9 is buried in the trench 7. Do it.
이어서, 도 1c에 도시된 바와 같이, 상기 결과물을 전체적으로 평탄화하여서 소자분리막(10)을 형성하도록 한다.Subsequently, as shown in FIG. 1C, the resultant is flattened to form the device isolation layer 10.
그런데, 종래에는 트렌치영역의 두 번에 걸친 열산화막 습식식각과 포토레지스트 제거시 사용되는 BOE 용액 사용으로 매립산화막(9)이 과도하게 식각되어서 소자구동시 트렌치영역의 끝단(A)에 전기적 집중현상(fringing field)이 유발되어서 소자의 전기적 열화를 발생하는 문제점이 있다.However, conventionally, the buried oxide layer 9 is excessively etched by using the BOE solution which is used during the wet etching of the thermal oxide and the photoresist removal twice in the trench region, so that the electric charge phenomenon occurs at the end A of the trench region when driving the device. (fringing field) is caused to cause electrical deterioration of the device.
또한, 매립산화막(9)이 과도하게 식각되면 게이트 형성시 게이트전극 물질이 잔류하게 되고 그 결과 게이트전극과 게이트전극 사이의 분리가 되지 않아서 전기적 쇼트(short)를 발생하는 문제점이 있다.In addition, when the buried oxide layer 9 is excessively etched, the gate electrode material remains during gate formation, and as a result, there is a problem in that an electrical short is generated because the gate electrode and the gate electrode are not separated.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로, 본 발명의 목적은 얕은 트렌치 소자격리(Sallow Trench Isolation; 이하 "STI"라 한다)공정에 의해 반도체기판에 소자분리막 프로파일(profile)을 구현하는 과정에서 트렌치를 고밀도플라즈마-화학기상증착-산화막으로 매립한 후 산화막 표면의 가운데 부분에 인을 이온주입하므로서 질화막 식각과 산화막 세정 시 가운데 부분의 식각율이 빨라져서 산화막을 평탄화되어 소자분리막 모서리 부분의 모우트 형상을 제거하는 것이 목적이다.The present invention has been made to solve the above problems, and an object of the present invention is to implement a device isolation film profile on a semiconductor substrate by a shallow trench isolation (STI) process. In the process, the trench is filled with high-density plasma-chemical vapor deposition-oxide, and phosphorus ion is implanted into the center of the oxide surface, thereby increasing the etch rate of the center during etching and nitride cleaning. The purpose is to remove the moat shape.
도 1a 내지 도 1c는 종래에 반도체 소자의 소자분리막 형성방법을 순차적으로 나타낸 단면도이다.1A to 1C are cross-sectional views sequentially illustrating a method of forming a device isolation film of a semiconductor device in the related art.
도 2a 내지 도 2i는 본 발명에 따른 반도체 소자의 소자분리막 형성방법을 순차적으로 나타낸 단면도이다.2A through 2I are cross-sectional views sequentially illustrating a method of forming an isolation layer in a semiconductor device according to the present invention.
-- 도면의 주요부분에 대한 부호의 설명 ---Explanation of symbols for the main parts of the drawing-
100 : 실리콘 기판 110 : 패드산화막100 silicon substrate 110 pad oxide film
120 : 패드질화막 130 : 감광막120 pad nitride film 130 photosensitive film
140 : 희생산화막 150 : 매립산화막140: sacrificial oxide film 150: buried oxide film
160 : 질화막스페이서 170 : 인(P) 이온160: nitride spacer 170: phosphorus (P) ion
상기 목적을 달성하기 위하여, 본 발명은 소정의 하부구조를 가지고 있는 실리콘 기판 상에 패드산화막과 패드질화막을 순차적으로 증착한 후 감광막 패턴을 형성하는 단계와, 상기 감광막 패턴을 마스크로 하여 트렌치를 형성하는 단계와, 상기 감광막을 제거한 후 희생산화막을 형성하는 단계와, 상기 결과물 상에 매립산화막을 증착하여 트렌치를 매립하는 단계와, 상기 매립산화막을 패드질화막 상부까지 화학기계적연마 공정을 진행한 후 매립산화막을 습식식각하는 단계와, 상기 결과물 상에 질화막을 증착하는 단계와, 상기 질화막을 식각하여 질화막스페이서를 형성하는 단계와, 상기 노출된 매립산화막에 인 이온을 주입하는 단계와, 상기 패드질화막과 질화막스페이서를 식각한 후 패드산화막과 매립산화막을 세정하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법을 제공한다.In order to achieve the above object, the present invention is a step of sequentially depositing a pad oxide film and a pad nitride film on a silicon substrate having a predetermined substructure and forming a photoresist pattern, and forming a trench using the photoresist pattern as a mask And forming a sacrificial oxide film after removing the photoresist film, depositing a buried oxide film on the resultant, filling a trench, and filling the buried oxide film to an upper surface of the pad nitride film, and then filling it. Wet etching an oxide film, depositing a nitride film on the resultant, etching the nitride film to form a nitride film spacer, implanting phosphorus ions into the exposed buried oxide film, the pad nitride film, And etching the pad oxide film and the buried oxide film after etching the nitride film spacer. It provides a device isolation film forming method of a semiconductor device characterized in that.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2j는 본 발명에 따른 반도체 소자의 소자분리막 형성방법을 순차적으로 나타낸 단면도이다.2A through 2J are cross-sectional views sequentially illustrating a method of forming an isolation layer in a semiconductor device according to the present invention.
도 2a에 도시된 바와 같이, 소정의 하부구조를 가지고 있는 실리콘 기판(100) 상에 패드산화막(110)과 패드질화막(120)을 순차적으로 증착한 후 패드질화막(120) 상에 트렌치를 형성하기 위한 감광막(130) 패턴을 형성한다.As shown in FIG. 2A, the pad oxide layer 110 and the pad nitride layer 120 are sequentially deposited on the silicon substrate 100 having a predetermined substructure, and then trenches are formed on the pad nitride layer 120. The photoresist layer 130 pattern is formed.
그리고, 도 2b에 도시된 바와 같이, 상기 감광막(130) 패턴을 마스크로 하여 트렌치영역(133)의 패드질화막(120)과 패드산화막(110) 및 실리콘기판(100)을 건식식각해서 트렌치(138)를 형성한다.As illustrated in FIG. 2B, the pad nitride layer 120, the pad oxide layer 110, and the silicon substrate 100 of the trench region 133 may be dry-etched using the photoresist layer 130 as a mask. ).
이어서, 도 2c에 도시된 바와 같이, 상기 감광막(130)을 제거한 후 트렌치(138) 형성 식각 공정에 의해 손상된 실리콘 표면의 격자구조를 보상하기 위해 실리콘 표면을 희생산화시켜서 희생산화막(140)을 형성한다.Subsequently, as shown in FIG. 2C, the sacrificial oxide layer 140 is formed by removing the photoresist layer 130 and then sacrificially oxidizing the silicon surface to compensate for the lattice structure of the silicon surface damaged by the trench 138 forming etching process. do.
도 2d에 도시된 바와 같이, 상기 결과물 상에 매립산화막(150)으로 고밀도플라즈마-화학기상증착(HDP-CVD) 산화막을 이용하여 트렌치(138)를 매립한다.As shown in FIG. 2D, the trench 138 is buried in the buried oxide film 150 using a high density plasma-chemical vapor deposition (HDP-CVD) oxide film.
이때, 상기 트렌치 매립 시에 패드질화막(120)이 충분히 덮이도록 매립산화막(150)을 도포한다.In this case, the buried oxide film 150 is coated so that the pad nitride film 120 is sufficiently covered when the trench is buried.
그리고, 도 2e에 도시된 바와 같이, 상기 매립산화막(150)을 패드질화막(120) 상부까지 화학기계적연마를 이용하여 연마한 후 매립산화막(150)이 패드질화막(120) 상부보다 낮고 패드산화막(110) 보다는 높게 습식식각을 실시하여 매립산화막(150)의 단차를 조절한다.As shown in FIG. 2E, after the buried oxide film 150 is polished to the upper surface of the pad nitride film 120 using chemical mechanical polishing, the buried oxide film 150 is lower than the pad nitride film 120 and the pad oxide film ( The wet etching is performed higher than 110 to adjust the level of the buried oxide film 150.
이어서, 도 2f에 도시된 바와 같이, 상기 결과물 상에 후속 이온주입 공정에서 이온주입 마스크 역할을 하기 위해 질화막(미도시함)을 증착한 후 다시 질화막을 식각하여 질화막스페이서(160)를 형성한다.Subsequently, as illustrated in FIG. 2F, a nitride film (not shown) is deposited on the resultant to serve as an ion implantation mask in a subsequent ion implantation process, and the nitride film is etched again to form the nitride film spacer 160.
이때, 상기 질화막 스페이서를 마스크로 하여 매립산화막의 가운데 부분에 후속 이온주입 공정을 실시할 수 있다.In this case, a subsequent ion implantation process may be performed on the center portion of the buried oxide film using the nitride spacer as a mask.
그리고, 도 2g에 도시된 바와 같이, 상기 노출된 매립산화막(150)에 인(P) 이온(170)을 주입한다.2G, phosphorus (P) ions 170 are implanted into the exposed buried oxide film 150.
이때, 상기 인 이온(170)주입 공정을 통하여 매립산화막(150)에 인 이온(170)이 주입된 부분이 인 이온(170)을 주입하지 않은 부분 보다 식각율이 더 빨라지게 된다.At this time, the portion where the phosphorus ion 170 is injected into the buried oxide film 150 through the phosphorus ion 170 injection process is faster than the portion where the phosphorus ion 170 is not injected.
도 2h에 도시된 바와 같이, 상기 패드질화막(120)과 질화막스페이서(160)를 습식식각 하여 제거한다.As shown in FIG. 2H, the pad nitride layer 120 and the nitride layer spacer 160 are wet-etched and removed.
이때, 상기 매립산화막(150)에 인(P) 이온이 주입된 가운데 부분이 인 이온이 주입되지 않은 모서리 부분보다 식각률이 빨라져 패드질화막(120)과 질화막스페이서(160) 제거 시 매립산화막(150)의 가운데 부분이 모서리 부분보다 좀더 식각된다.At this time, the etch rate is faster than the corner portion where phosphorus (P) ions are implanted into the buried oxide film 150, and thus the buried oxide film 150 is removed when the pad nitride film 120 and the nitride film spacer 160 are removed. The middle part of is more etched than the corner part.
계속하여, 도 2i에 도시된 바와 같이, 상기 매립산화막(150)과 패드산화막(110) 세정공정을 실시한다.Subsequently, as shown in FIG. 2I, the buried oxide film 150 and the pad oxide film 110 are cleaned.
이때, 상기 세정공정 시 매립산화막(150)의 모서리 부분과 가운데 부분의 식각율이 동일하기 때문에 패드산화막(110)과 매립산화막(150)이 평탄한 모양을 가지게 된다.At this time, since the etching rate of the corner portion and the center portion of the buried oxide film 150 is the same during the cleaning process, the pad oxide film 110 and the buried oxide film 150 have a flat shape.
따라서, 상기한 바와 같이, 본 발명에 따른 반도체 소자의 소자분리막 형성방법을 이용하게 되면, 얕은 트렌치 소자격리(Sallow Trench Isolation; 이하 "STI"라 한다)공정에 의해 반도체기판에 소자분리막 프로파일(profile)을 구현하는 과정에서 트렌치를 고밀도플라즈마-화학기상증착-산화막으로 매립한 후 산화막 표면의 가운데 부분에 인을 이온주입하므로서 질화막 식각과 산화막 세정 시 가운데 부분의 식각율이 빨라져서 산화막을 평탄화되어 소자분리막 모서리 부분의 모우트 형상을 제거하도록 하는 매우 유용하고 효과적인 발명이다.Therefore, as described above, when the device isolation film forming method of the semiconductor device according to the present invention is used, a device isolation film profile is formed on the semiconductor substrate by a shallow trench isolation (STI) process. In the process of realizing the trench, the trench is filled with high-density plasma-chemical vapor deposition-oxide, and phosphorus ion is implanted into the center of the oxide film surface, so that the etching rate of the center part is increased during etching of the nitride film and cleaning the oxide film. It is a very useful and effective invention for removing the corner shape of the corner part.
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