KR20020056345A - Method of packaging a semiconductor device - Google Patents

Method of packaging a semiconductor device Download PDF

Info

Publication number
KR20020056345A
KR20020056345A KR1020000085674A KR20000085674A KR20020056345A KR 20020056345 A KR20020056345 A KR 20020056345A KR 1020000085674 A KR1020000085674 A KR 1020000085674A KR 20000085674 A KR20000085674 A KR 20000085674A KR 20020056345 A KR20020056345 A KR 20020056345A
Authority
KR
South Korea
Prior art keywords
wafer
film
flexible metal
work tool
semiconductor device
Prior art date
Application number
KR1020000085674A
Other languages
Korean (ko)
Other versions
KR100390946B1 (en
Inventor
최창국
Original Assignee
박종섭
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 박종섭, 주식회사 하이닉스반도체 filed Critical 박종섭
Priority to KR10-2000-0085674A priority Critical patent/KR100390946B1/en
Publication of KR20020056345A publication Critical patent/KR20020056345A/en
Application granted granted Critical
Publication of KR100390946B1 publication Critical patent/KR100390946B1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49572Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE: A method for packing a semiconductor device is provided to reduce manufacturing cost caused by the use of u-BGA package method, and to use a film including a flexible metal instead of elastomer for electrical connection. CONSTITUTION: After positioning a wafer(1) on a work tool. A film(2) comprising a flexible metal(3) and a ball land(4) is set on the wafer. By using a bonding tool, the flexible metal is connected to the wafer. The wafer and the film are separated by manipulating the work tool and then an encapsulant(8) is inserted between the wafer and the film. The wafer and the film are taken out the work tool to separate single chips by using a dicing wheel. A solder ball(13) is set on the ball land.

Description

반도체 소자의 패키지 방법{Method of packaging a semiconductor device}Method of packaging a semiconductor device

본 발명은 반도체 소자의 패키지 방법에 관한 것으로서, 특히 웨이퍼와 필름을 접착하기 위해 사용되는 엘라스토머 대신 전기적인 접속을 가능하게 하는 플렉시블 메탈을 포함한 필름을 사용함으로써, 웨이퍼 상태에서 직접 패키지를 제작할 수 있어 공정비용 및 공정 시간을 단축 할 수 있는 반도체 소자의 패키지 방법에 관한 것이다.BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a method for packaging a semiconductor device, and in particular, a package can be manufactured directly in a wafer state by using a film including a flexible metal that enables electrical connection instead of an elastomer used for bonding a wafer and a film. The present invention relates to a method for packaging a semiconductor device that can reduce cost and process time.

통상, 반도체 소자의 패키지 방법에는 QFP 타입(Quad Flat Package type) 이나 BGA(Ball Grid Array) 형태의 패키지가 널리 사용되고 있다. 특히, 팬 아웃(Fan out) 구조의 u-BGA를 이용한 반도체 소자의 패키지 방법은 다른 패키지 방법에 의해 높은 효율성을 보여 그에 대한 연구가 활발히 진행되고 있다.In general, a package of a QFP type (Quad Flat Package type) or BGA (Ball Grid Array) type is widely used as a method of packaging a semiconductor device. In particular, the packaging method of a semiconductor device using a fan-out u-BGA shows a high efficiency by another packaging method, and research on it is being actively conducted.

BGA를 이용한 반도체 소자의 패키지 방법을 간략하게 설명하면, 우선 소정의 구조로 형성된 반도체 칩 상부에 엘라스토머(elastomer)의 접착층이 붙어 있는 PI 필름(PI film)이 위치된 후, 소정의 열처리공정에 의해 접착층이 녹아 반도체 칩과 PI 필름이 접착되게 된다. 또한, PI 필름의 중앙에는 홀이 형성되어 있고 그 최상단에는 리드(lead)가 위치된다. 이후, 리드 본딩 기구를 이용하여 반도체 칩과 PI 필름간의 전기적 신호가 가능하도록 리드본딩이 이루어진다.Briefly describing a method for packaging a semiconductor device using a BGA, a PI film having an adhesive layer of an elastomer is placed on a semiconductor chip formed in a predetermined structure and then subjected to a predetermined heat treatment process. The adhesive layer melts to bond the semiconductor chip and the PI film. In addition, a hole is formed in the center of the PI film, and a lead is positioned at the top thereof. Thereafter, lead bonding is performed to enable an electrical signal between the semiconductor chip and the PI film by using a lead bonding mechanism.

리드본딩후, 인캡슐레이션(encapsulation)공정을 통해 리드 및 홀로 노출된 내부회로를 보호하기 위해 인캡슐런트로 PI 필름의 중앙에 형성된 홀이 몰딩된다.이후, PI 필름 상부에 다수의 솔더 볼(solder ball)이 부착되어 BGA의 반도체 소자가 패키지화된다.After lead bonding, an encapsulation process encapsulates the holes formed in the center of the PI film with encapsulants to protect the internal circuits exposed by the leads and holes. A solder ball is attached to package the BGA semiconductor device.

전술한 바와 같이, 종래 기술에 따른 u-BGA 패키지 방법은 반도체 칩 상부에 엘라스토머의 접착층을 접착한 후, 리드본딩 공정이 이루어진다. 이후, 인캡슐레이션을 한 후, 솔더 볼을 부착하여 패키지하는 방법으로 이루어진다.As described above, in the u-BGA package method according to the prior art, after bonding the adhesive layer of the elastomer on the semiconductor chip, a lead bonding process is performed. Thereafter, after encapsulation, a solder ball is attached and packaged.

그러나 u-BGA 패키지 방법은 반도체 칩과 PI 필름을 접착하기 위한 엘라스토머가 고가이어서 이를 대처할 만한 기술연구가 활발히 진행중에 있다.However, the u-BGA package method is expensive because the elastomer for bonding the semiconductor chip and the PI film is expensive.

따라서, 본 발명의 목적은 u-BGA 패키지 방법을 이용한 반도체 소자를 패키지화공정중 문제가 되는 제조 비용을 줄이기 위한 반도체 소자의 패키지 방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method of packaging a semiconductor device for reducing the manufacturing cost, which is a problem during the packaging process of the semiconductor device using the u-BGA packaging method.

본 발명의 또 다른 목적은 웨이퍼와 필름을 접착하기 위해 종래 기술에서 사용되는 엘라스토머 대신 전기적인 접속을 가능하게 하는 플렉시블 메탈을 포함한 필름을 사용함으로써, 웨이퍼 상태에서 직접 패키지를 제작할 수 있어 공정비용 및 공정 시간을 단축 할 수 있는 반도체 소자의 패키지 방법을 제공함에 있다.Another object of the present invention is to use a film containing a flexible metal that allows electrical connection instead of the elastomers used in the prior art to bond the wafer and the film, it is possible to manufacture the package directly in the wafer state, the process cost and process It is to provide a method of packaging a semiconductor device that can reduce the time.

도 1(a) 내지 도 1(e)는 본 발명의 일 실시예에 따른 반도체 소자의 패키지 방법을 설명하기 위해 순서적으로 도시한 단면도.1 (a) to 1 (e) are cross-sectional views sequentially illustrating the method of packaging a semiconductor device according to an embodiment of the present invention.

도 2는 도 1에 도시된 필름을 확대하여 도시한 평면도.FIG. 2 is an enlarged plan view of the film shown in FIG. 1. FIG.

도 3은 도 1에 도시된 플렉시블 메탈과 볼랜드를 확대하여 도시한 평면도.3 is an enlarged plan view of the flexible metal and the borland illustrated in FIG. 1;

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

1 : 웨이퍼 2 : 필름1: wafer 2: film

3 : 플렉시블 메탈 4 : 볼 랜드3: flexible metal 4: ball land

5 : 작업 툴 6 : 본딩 툴5: work tool 6: bonding tool

7 : 접촉부 8 : 인캡슐런트7 contact portion 8 encapsulant

9 : 칩 패드 10 : 유입구9: chip pad 10: inlet

11 : 유출구 12 : 다이싱 휠11: outlet 12: dicing wheel

13 : 솔더 볼13: solder ball

본 발명은 소정의 작업 툴내에 웨이퍼를 위치한 후, 그 상부에 플렉시블 메탈과 볼랜드가 형성된 필름을 안착시키는 단계와; 본딩 툴을 이용하여 상기 플렉시블 메탈과 웨이퍼를 전기적으로 접속하는 단계와; 상기 작업 툴을 조작하여 상기 웨이퍼와 필름을 분리한 후, 그 사이에 인캡슐런트를 주입하는 단계와; 상기 작업 툴로부터 상기 웨이퍼와 필름을 꺼낸후, 다이싱 휠을 이용하여 단일 칩으로 분리하는 단계와; 상기 볼랜드 상부에 솔더 볼을 안착시키는 단계를 포함한다.The present invention comprises the steps of placing a film in which a flexible metal and a ball land is formed thereon after placing the wafer in a predetermined work tool; Electrically connecting the flexible metal and the wafer using a bonding tool; Operating the work tool to separate the wafer and the film, and injecting an encapsulant therebetween; Removing the wafer and the film from the work tool and separating them into a single chip using a dicing wheel; And mounting a solder ball on the ball land.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

도 1(a) 내지 도 1(e)는 본 발명의 일 실시예에 따른 반도체 소자의 패키지 방법을 설명하기 위해 도시한 반도체 소자의 패키지 단면도이다.1 (a) to 1 (e) are cross-sectional views of a semiconductor device for explaining a method of packaging a semiconductor device according to an embodiment of the present invention.

도 1(a)를 참조하면, 우선, 패키지화하기 위한 소정의 웨이퍼(1) 및 웨이퍼(1)와 접속되기 위한 필름(2)이 마련된다.Referring to FIG. 1A, first, a predetermined wafer 1 for packaging and a film 2 for connecting with the wafer 1 are provided.

도 2 및 도 3에 도시된 바와 같이, 필름(2)은 웨이퍼(1) 상단에 위치한 칩 패드(chip pad; 9)와 전기적인 접속을 가능하게 하는 접촉부(7)를 포함한 플렉시블 메탈(flexible metal; 3)과 후에 인쇄회로보드(printed circuit board; PCB)에 실장이 가능하게 하기 위해 솔더 볼(solder ball; 13)이 위치할 볼 랜드(ball land; 4)로 구성된다. 여기서, 플렉시블 메탈(3)은 웨이퍼(1)와 필름(2)의 높이를 조절할 수 있도록 스프링형태의 원형 또는 다각형으로 이루어짐과 아울러 금 또는 구리와 같은 전도성 물질로 형성된다.As shown in FIGS. 2 and 3, the film 2 is a flexible metal including a contact portion 7 which enables electrical connection with a chip pad 9 located on top of the wafer 1. 3) and a ball land 4 on which solder balls 13 will be placed to enable mounting on a printed circuit board (PCB) later. Here, the flexible metal 3 is made of a spring-like circular or polygonal shape and a conductive material such as gold or copper to adjust the height of the wafer 1 and the film 2.

도 1(b)를 참조하면, 이후, 작업 툴(5) 내의 소정 부위에 웨이퍼(1)가 배치됨과 아울러 그 상부에 필름(2)이 배치된다. 이후, 열압착 방식의 본딩 툴(bonding tool; 6)에 의해 플렉시블 메탈(3)의 접촉부(7)와 웨이퍼(1) 상단에 위치된 칩 패드(9)가 전기적으로 접속하기 위한 플렉시블 메탈(3) 본딩작업이 이루어진다.Referring to FIG. 1B, the wafer 1 is disposed at a predetermined portion of the work tool 5 and the film 2 is disposed thereon. Subsequently, the flexible metal 3 for electrically connecting the contact portion 7 of the flexible metal 3 to the chip pad 9 positioned on the upper surface of the wafer 1 by a thermocompression bonding tool 6. ) Bonding works.

도 1(c)를 참조하면, 이후, 작업 툴(5)을 조작하여 웨이퍼(1) 상부에 위치된 필름(2)을 들어올려 웨이퍼(1)와 필름(2) 간에 소정의 공간을 형성한다. 이후, 공간은 작업 툴(5)의 유입구(10)를 통해 유입되는 인캡슐런트(8)에 의해 채워진다. 이때, 인캡슐런트(8) 주입공정시 발생되는 공기는 유출구(11)를 통해 외부로 배기된다.Referring to FIG. 1C, a work tool 5 is then operated to lift a film 2 positioned on the wafer 1 to form a predetermined space between the wafer 1 and the film 2. . The space is then filled by the encapsulant 8 entering through the inlet 10 of the work tool 5. At this time, the air generated during the encapsulant 8 injection process is exhausted to the outside through the outlet 11.

도 1(d)를 참조하면, 이후, 작업 툴(5)로부터 웨이퍼(1)와 필름(2)을 꺼낸 후, 다이싱 휠(dicing wheel; 12)을 이용한 절단 작업에 의해 단일 칩이 형성된다.Referring to FIG. 1 (d), after the wafer 1 and the film 2 are removed from the work tool 5, a single chip is formed by a cutting operation using a dicing wheel 12. .

도 1(e)를 참조하면, 이후, 필름(2) 상단에 형성된 볼랜드(4)에 솔더 볼(13)이 위치된다.Referring to FIG. 1E, the solder balls 13 are then positioned on the ball lands 4 formed on the top of the film 2.

전술한 바와 같이, 본 발명은 웨이퍼와 필름을 전기적으로 접속하기 위해 종래 기술에서 사용되는 엘라스토머 대신 전기적인 접속을 가능하게 하는 플렉시블 메탈을 포함한 필름을 사용하게 된다.As mentioned above, the present invention uses a film containing a flexible metal that enables electrical connection instead of the elastomers used in the prior art to electrically connect the wafer and the film.

상술한 바와 같이, 본 발명은 웨이퍼와 필름을 접착하기 위해 사용되는 엘라스토머 대신 전기적인 접속을 가능하게 하는 플렉시블 메탈을 포함한 필름을 사용함으로써, 웨이퍼 상태에서 직접 패키지를 제작할 수 있어 공정비용 및 공정 시간을 단축 할 수 있다.As described above, the present invention uses a film containing a flexible metal that allows electrical connection instead of the elastomer used to bond the wafer and the film, thereby making it possible to manufacture the package directly in the wafer state, thereby reducing the process cost and processing time. Can be shortened.

Claims (2)

소정의 작업 툴내에 웨이퍼를 위치한 후, 그 상부에 플렉시블 메탈과 볼랜드가 형성된 필름을 안착시키는 단계와;Placing the wafer in a predetermined work tool, and then seating a film having a flexible metal and a ballland formed thereon; 본딩 툴을 이용하여 상기 플렉시블 메탈과 웨이퍼를 전기적으로 접속하는 단계와;Electrically connecting the flexible metal and the wafer using a bonding tool; 상기 작업 툴을 조작하여 상기 웨이퍼와 필름을 분리한 후, 그 사이에 인캡슐런트를 주입하는 단계와;Operating the work tool to separate the wafer and the film, and injecting an encapsulant therebetween; 상기 작업 툴로부터 상기 웨이퍼와 필름을 꺼낸후, 다이싱 휠을 이용하여 단일 칩으로 분리하는 단계와;Removing the wafer and the film from the work tool and separating them into a single chip using a dicing wheel; 상기 볼랜드 상부에 솔더 볼을 안착시키는 단계를 포함하는 것을 특징으로 반도체 소자의 패키지 방법.And depositing solder balls on the ball lands. 제 1 항에 있어서,The method of claim 1, 상기 플렉시블 메탈은 상기 웨이퍼와 필름의 높이를 조절할 수 있도록 스프링형태의 원형 또는 다각형으로 이루어짐과 아울러 금 또는 구리와 같은 전도성 물질로 형성되는 것을 특징으로 하는 반도체 소자의 패키지 방법.The flexible metal is a package method of a semiconductor device, characterized in that formed of a conductive material such as gold or copper as well as made of a circular or polygonal spring shape to adjust the height of the wafer and the film.
KR10-2000-0085674A 2000-12-29 2000-12-29 Method of packaging a semiconductor device KR100390946B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR10-2000-0085674A KR100390946B1 (en) 2000-12-29 2000-12-29 Method of packaging a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR10-2000-0085674A KR100390946B1 (en) 2000-12-29 2000-12-29 Method of packaging a semiconductor device

Publications (2)

Publication Number Publication Date
KR20020056345A true KR20020056345A (en) 2002-07-10
KR100390946B1 KR100390946B1 (en) 2003-07-10

Family

ID=27688839

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2000-0085674A KR100390946B1 (en) 2000-12-29 2000-12-29 Method of packaging a semiconductor device

Country Status (1)

Country Link
KR (1) KR100390946B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100492626B1 (en) * 2003-06-02 2005-06-03 앰코 테크놀로지 코리아 주식회사 Method for Reworking an Elastmoer-Delaminated Wafer

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100222299B1 (en) * 1996-12-16 1999-10-01 윤종용 Wafer level chip scale package and method of manufacturing the same
KR100302594B1 (en) * 1998-10-14 2001-09-22 김영환 Member for semiconductor package, and semiconductor package and fabrication thereof
JP3506029B2 (en) * 1999-02-18 2004-03-15 日立電線株式会社 Tape-shaped wiring board and semiconductor device using the same
JP2000216202A (en) * 1999-01-21 2000-08-04 Hitachi Cable Ltd Tape carrier for bga and semiconductor device using the same
US6426241B1 (en) * 1999-11-12 2002-07-30 International Business Machines Corporation Method for forming three-dimensional circuitization and circuits formed

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100492626B1 (en) * 2003-06-02 2005-06-03 앰코 테크놀로지 코리아 주식회사 Method for Reworking an Elastmoer-Delaminated Wafer

Also Published As

Publication number Publication date
KR100390946B1 (en) 2003-07-10

Similar Documents

Publication Publication Date Title
US9117815B2 (en) Method of fabricating a packaged semiconductor
JP5723153B2 (en) Packaged integrated circuit device with through-body conductive vias and method of manufacturing the same
US7361533B1 (en) Stacked embedded leadframe
US6975038B1 (en) Chip scale pin array
US6790710B2 (en) Method of manufacturing an integrated circuit package
US6376277B2 (en) Semiconductor package
US20070254409A1 (en) Method of forming stackable package
KR100842915B1 (en) Stack package and manufacturing method of the same
KR101119708B1 (en) Land grid array packaged device and method of forming same
JP2007088453A (en) Method of manufacturing stack die package
US6245598B1 (en) Method for wire bonding a chip to a substrate with recessed bond pads and devices formed
US6284566B1 (en) Chip scale package and method for manufacture thereof
JPH0677398A (en) Overmolded semiconductor device and its manufacture
KR100390946B1 (en) Method of packaging a semiconductor device
JP4497304B2 (en) Semiconductor device and manufacturing method thereof
KR100871379B1 (en) Method of manufacturing semiconductor package
KR101028573B1 (en) Chip scale package and method for fabricating the same
JP2006049694A (en) Dual gauge lead frame
JPH10154768A (en) Semiconductor device and its manufacturing method
KR100351920B1 (en) semiconductor device and method for fabricating the same
KR100520443B1 (en) Chip scale package and its manufacturing method
US20030214019A1 (en) Packaging system for semiconductor devices
KR100444175B1 (en) ball grid array of stack chip package
KR20020056283A (en) Structure of stack type muli chip semiconductor package and manufacture method the same
WO2003017328A2 (en) Encapsulated integrated circuit package and method of manufacturing an integrated circuit package

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20110526

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee