KR20020056287A - method for manufacturing of SRAM of semiconductor device - Google Patents
method for manufacturing of SRAM of semiconductor device Download PDFInfo
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- KR20020056287A KR20020056287A KR1020000085610A KR20000085610A KR20020056287A KR 20020056287 A KR20020056287 A KR 20020056287A KR 1020000085610 A KR1020000085610 A KR 1020000085610A KR 20000085610 A KR20000085610 A KR 20000085610A KR 20020056287 A KR20020056287 A KR 20020056287A
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- 238000000034 method Methods 0.000 title claims abstract description 31
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title description 6
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000010438 heat treatment Methods 0.000 claims abstract description 5
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 238000002955 isolation Methods 0.000 abstract description 8
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 4
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001878 scanning electron micrograph Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/903—FET configuration adapted for use as static memory cell
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
본 발명은 반도체 메모리 셀에 관한 것으로, 특히 SRAM 셀의 웰 마스크(Well Mask) 진행시 CD 변화를 감소시킬 수 있는 반도체 장치의 SRAM 셀 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory cell, and more particularly, to a method of fabricating an SRAM cell of a semiconductor device capable of reducing CD change during a well mask process of an SRAM cell.
일반적으로 SRAM은 리플레쉬(refresh) 동작이 필요없고, 동작 타이밍이 용이하다는 편리함 때문에 마이크로 컴퓨터와 엑세스 시간 및 싸이클 시간을 같게 할 수 있고 바이폴라 램과 같이 고속 동작을 실현할 수 있도록 되어있다. 그리고 대형 계산기의 버퍼 메모리, 슈퍼컴퓨터의 메인 메모리, 제어 메모리 등에 광범위하게 사용되고 있다.In general, SRAM does not require refresh operation, and is easy to operate, so that the access time and cycle time can be the same as that of a microcomputer, and high speed operation such as bipolar RAM can be achieved. It is widely used in buffer memory of large calculators, main memory of supercomputers, and control memory.
이와 같은 SRAM은 플립-플롭을 기본으로 하고 있으며, 그 부하소자에 따라 D형 SRAM, CMOS SRAM, 고저항 부하형 SRAM으로 구분된다.Such SRAMs are based on flip-flops, and are classified into D type SRAMs, CMOS SRAMs, and high resistance load type SRAMs according to their load elements.
이중 CMOS SRAM은 부하소자로 PMOS를 사용하고 있으며 소비전력은 가장 적고 전지백업에 대한 불휘발성 메모리의 역할을 용이하게 달성할 수 있다.Dual CMOS SRAMs use PMOS as the load element, with the lowest power consumption and can easily achieve the role of nonvolatile memory for battery backup.
그러나 셀내에 PMOS, NMOS를 혼재시키지 않으면 안되고, 소자간 분리가 필요하므로 셀 면적이 커지는 결점이 있다.However, PMOS and NMOS must be mixed in the cell, and separation between elements is required, resulting in a large cell area.
이하, 첨부된 도면을 참조하여 종래의 CMOS 에스램 셀을 설명하면 다음과 같다.Hereinafter, a conventional CMOS SRAM cell will be described with reference to the accompanying drawings.
도 1은 일반적인 CMOS 에스램 셀의 회로 구성도이다.1 is a circuit diagram of a typical CMOS SRAM cell.
도 1에 도시한 바와 같이 2개의 억세스 트랜지스터(TA1, TA2)와 드라이버 트랜지스터(TD1, TD2)는 앤모스(NMOS)로 구성되고 로드 트랜지스터(TL1, TL2)는 피모스(PMOS)로 구성되어 6개의 트랜지스터가 서로 교차 접속되는 플립-플롭을 이룬다.As shown in FIG. 1, the two access transistors TA1 and TA2 and the driver transistors TD1 and TD2 are composed of NMOS, and the load transistors TL1 and TL2 are composed of PMOS. The two transistors form a flip-flop that is cross-connected with each other.
상기 기본 셀의 NMOS 엑세스 트랜지스터(TA1, TA2)는 비트라인(B/L, B/L)과 콘택(G1, G2)되고, 그 게이트는 워드라인(W/L)에 연결된다.The NMOS access transistors TA1 and TA2 of the base cell are in contact with the bit lines B / L and B / L and G 1 and G 2 , and their gates are connected to the word lines W / L.
또한, 제 1 드라이버 트랜지스터(TD1)와 제 1 로드 트랜지스터(TL1)의 게이트가 연결되고, 제 2 드라이버 트랜지스터(TD2)와 제 2 로드 트랜지스터(TL2)의 게이트가 연결된다.In addition, the gates of the first driver transistor TD1 and the first load transistor TL1 are connected, and the gates of the second driver transistor TD2 and the second load transistor TL2 are connected.
그리고 PMOS 제 1, 제 2 로드 트랜지스터(TL1, TL2)는 공급전원(Vdd)에 접속(C3,C4)되고 NMOS 제 1, 제 2 드라이버 트랜지스터(TD1, TD2)는 접지전압(Vss)에 접속(C7, C8)된다.The PMOS first and second load transistors TL1 and TL2 are connected to the supply power supply Vdd (C 3 , C 4 ), and the NMOS first and second driver transistors TD1 and TD2 are connected to the ground voltage Vss. Connections C 7 and C 8 are made.
그러나 CMOS 에스램 셀내에 P형 웰과 N형 웰이 동시에 존재하므로 셀 내에서 웰 펀치(well punch) 특성이 굉장히 취약하다.However, since the P type well and the N type well exist in the CMOS SRAM cell at the same time, the well punch characteristic is very weak in the cell.
따라서, 웰 마스크 레이어(layer) 형성을 명확하게 컨트롤(control)할 필요가 있으므로 웰 마스크 진행 후 CD를 측정(measure)하면서 진행한다.Therefore, since it is necessary to clearly control the well mask layer formation, the process proceeds while measuring the CD after the well mask progression.
상기 CD의 측정은 0.17±0.05를 타겟(target)으로 진행한다. 즉, 0.17(좌)/0.17(우)이 나오면 CD 및 오버레이(overlay)가 정확하게 컨트롤된 것이다.The measurement of CD proceeds with a target of 0.17 ± 0.05. In other words, when 0.17 (left) /0.17 (right) comes out, the CD and overlay are precisely controlled.
그러나 실제 공정진행의 데이터는 표 1과 같다.However, the actual process progress data is shown in Table 1.
따라서, 기판 상부에서 CD가 벗어나는 것을 확인할 수 있다.Therefore, it can be seen that the CD is released from the top of the substrate.
이러한 결과는 하나의 구역(lot)에서 이상현상이 나오는 것이 아니라 재현성 있게 후속 구역(lot)에서도 상부위치에서 CD가 벗어난다.This result is not anomaly in one lot, but reproducibly deviates from the upper position of CD in subsequent slots.
도 2a와 도 2b는 종래의 상부와 중앙에 대한 CD SEM 사진이다.2A and 2B are CD SEM images of a conventional top and center.
즉, 도 2a와 도 2b에 도시한 바와 같이 상부에서 소자분리 영역의 프로파일(profile)이 중앙에 비해 희미하게 나타난다.That is, as shown in FIGS. 2A and 2B, the profile of the device isolation region appears faintly compared to the center at the top.
따라서, 포토공정의 마진(margin)이 감소한다.Thus, the margin of the photo process is reduced.
본 발명은 상기와 같은 문제점을 해결하기 위하여 안출한 것으로 토폴로지(topology)가 없는 기판에 웰 마스크를 형성한 후 소자분리 영역을 형성하므로 웰 마스크(Well Mask) 형성시 발생하는 CD 및 오버레이 변화를 감소시킬 수 반도체 장치의 에스램 셀 제조방법을 제공하는데 그 목적이 있다.In order to solve the above problems, the present invention reduces the change of CD and overlay that occurs when forming a well mask, since a device isolation region is formed after a well mask is formed on a substrate without a topology. It is an object of the present invention to provide a method for manufacturing an SRAM cell of a semiconductor device.
도 1은 일반적인 CMOS 에스램 셀의 회로 구성도1 is a circuit diagram of a typical CMOS SRAM cell
도 2a와 도 2b는 종래의 상부와 중앙에 대한 CD SEM 사진2A and 2B are CD SEM photographs of a conventional top and center
도 3a 내지 도 3d는 본 발명의 일실시예에 따른 셜로우 트랜치 아이솔레이션 형성방법을 나타낸 공정단면도3A to 3D are cross-sectional views illustrating a method of forming a shallow trench isolation according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
21 : 반도체 기판 22 : N형 웰21 semiconductor substrate 22 N-type well
23 : P형 웰 24 : 제 1 절연막23 p-type well 24 first insulating film
25 : 트랜치 26 : 제 2 절연막25 trench 26 second insulating film
27 : 제 3 절연막27: third insulating film
상기와 같은 목적을 달성하기 위한 본 발명의 반도체 장치의 에스램 셀 제조방법은 반도체 기판에 얼라인 키 패턴을 형성하는 단계와, 상기 기판에 제 1 도전형 웰과 제 2 도전형 웰을 형성하는 단계와, 상기 기판 전면에 제 1 절연막을 형성하고, 상기 제 1, 제 2 도전형 웰의 소정영역에 소정깊이로 트랜치를 형성하는 단계와, 상기 트랜치를 포함한 전면에 제 2 절연막과 제 3 절연막을 차례로 형성하는 단계와, 상기 제 3 절연막이 트랜치 부분에만 남도록 한 후, 상기 제 1, 제 2 절연막을 제거하는 공정을 포함하여 이루어짐을 특징으로 한다.In order to achieve the above object, an SRAM cell manufacturing method of a semiconductor device of the present invention includes forming an alignment key pattern on a semiconductor substrate, and forming a first conductive well and a second conductive well on the substrate. Forming a first insulating film on the entire surface of the substrate, forming a trench in a predetermined region of the first and second conductivity type wells, and forming a second insulating film and a third insulating film on the entire surface including the trench; And sequentially removing the first and second insulating films after leaving the third insulating film only in the trench portion.
상기 특징의 바람직한 실시예는 상기 제 1 도전형 웰과 제 2 도전형 웰 형성시 상기 기판은 토폴로지가 없는 상태임을 특징으로 한다.According to a preferred embodiment of the present invention, the substrate has no topology when the first conductive well and the second conductive well are formed.
상기 특징의 바람직한 실시예는 상기 제 1 도전형 웰과 제 2 도전형 웰 형성후 열처리 공정을 실시하는 것을 더 포함하여 이루어짐을 특징으로 한다.A preferred embodiment of the feature is characterized in that it further comprises the step of performing a heat treatment process after the first conductivity type well and the second conductivity type well.
상기 특징의 바람직한 실시예는 상기 제 1 절연막은 질화막을 사용하는 것을 특징으로 한다.A preferred embodiment of the above feature is characterized in that the first insulating film uses a nitride film.
상기 특징의 바람직한 실시예는 상기 제 3 절연막은 고밀도 플라즈마 공정을 통해 증착하고 CMP 공정을 이용하여 상기 트랜치 내부에만 남도록 하는 것을 특징으로 한다.According to a preferred embodiment of the present invention, the third insulating film is deposited through a high density plasma process and remains only inside the trench using a CMP process.
이하, 첨부된 도면을 참조하여 본 발명의 반도체 장치의 에스램 셀 제조방법에 대하여 보다 상세히 설명하면 다음과 같다.Hereinafter, a method of manufacturing an SRAM cell of a semiconductor device of the present invention will be described in detail with reference to the accompanying drawings.
도 3a 내지 도 3d는 본 발명의 일실시예에 따른 반도체 장치의 셜로우 트랜치 아이솔레이션 형성방법을 나타낸 공정단면도이다.3A to 3D are cross-sectional views illustrating a method of forming a shallow trench isolation in a semiconductor device according to an embodiment of the present invention.
도 3a에 도시한 바와 같이 도면에 도시하지 않았지만 반도체 기판(21)에 얼라인 키 패턴을 위한 에치 공정을 실시한 후, 마스크시 얼라인을 위한 얼라인 키 패턴을 형성한다.Although not illustrated in FIG. 3A, an etch process for an alignment key pattern is performed on the semiconductor substrate 21, and then an alignment key pattern for alignment at the time of masking is formed.
이어, 상기 토폴로지가 없는 상태의 평탄 반도체 기판(21) 전면에 포토레지스트를 증착하고 노광 및 현상공정을 통해 상기 기판(21) 소정영역이 노출되도록 제 1 포토레지스트 패턴(PR1)을 형성한다.Subsequently, a photoresist is deposited on the entire surface of the flat semiconductor substrate 21 without the topology, and a first photoresist pattern PR1 is formed to expose a predetermined region of the substrate 21 through an exposure and development process.
그리고 상기 제 1 포토레지스트 패턴(PR1)을 마스크로 하여 불순물 이온주입 공정을 통해 N형 웰(22)을 형성한다.The N-type well 22 is formed through the impurity ion implantation process using the first photoresist pattern PR1 as a mask.
도 3b에 도시한 바와 같이 상기 제 1 포토레지스트 패턴(PR1)을 제거한 후, 전면에 포토레지스트를 증착하고 노광 및 현상공정을 통해 상기 N형 웰(22)상에 제2 포토레지스트 패턴(PR2)을 형성한다.After removing the first photoresist pattern PR1 as shown in FIG. 3B, a photoresist is deposited on the entire surface, and the second photoresist pattern PR2 is formed on the N-type well 22 through an exposure and development process. To form.
그리고 상기 제 2 포토레지스트 패턴(PR2)을 마스크로 하여 불순물 이온주입 공정을 통해 P형 웰(23)을 형성한다.The P type well 23 is formed through the impurity ion implantation process using the second photoresist pattern PR2 as a mask.
이어, 상기 제 2 포토레지스트 패턴(PR2)을 제거한 후, 열처리 공정을 실시한다.Subsequently, after the second photoresist pattern PR2 is removed, a heat treatment process is performed.
도 3c에 도시한 바와 같이 상기 N형 웰(22) 및 P형 웰(23)을 포함한 기판(21) 전면에 제 1 절연막(24)을 형성한다. 이때, 상기 제 1 절연막(24)은 질화막을 사용한다.As shown in FIG. 3C, a first insulating film 24 is formed on the entire surface of the substrate 21 including the N type well 22 and the P type well 23. In this case, a nitride film is used as the first insulating film 24.
이어서, 상기 반도체 기판(21)의 소정영역에 포토리소그래피 공정을 이용하여 상기 반도체 기판(21)을 소정깊이로 식각하여 트랜치(25)를 형성한 후, 상기 트랜치(25)을 포함한 기판(21)상에 제 2 절연막(26)을 형성한다. 이때, 상기 제 2 절연막(26)은 산화막(high temperature oxide : HTO)을 사용한다.Subsequently, the trench 25 is formed by etching the semiconductor substrate 21 to a predetermined depth in a predetermined region of the semiconductor substrate 21 by using a photolithography process, and then the substrate 21 including the trench 25. The second insulating film 26 is formed on it. In this case, the second insulating layer 26 uses a high temperature oxide (HTO).
도 3d에 도시한 바와 같이 상기 트랜치(25)를 포함한 상기 제 2 절연막(26)상에 고밀도 플라즈마(High Density Plasma : HDP)증착 공정으로 제 3 절연막(27)을 증착한 후, 화학기계적 폴리싱(Chemical Mechanical Polishing : CMP) 공정으로 에치백(etch-back)하여 상기 제 3 절연막(27)이 상기 트랜치(25)에만 남도록 하여 소자격리구조를 완성한다.As shown in FIG. 3D, a third insulating film 27 is deposited on the second insulating film 26 including the trench 25 by a high density plasma (HDP) deposition process, followed by chemical mechanical polishing ( The mechanical isolation structure is completed by etching back the chemical mechanical polishing (CMP) process so that the third insulating layer 27 remains only in the trench 25.
여기서, 상기 제 3 절연막(27) 증착한 후 열처리 공정을 실시하여 상기 N형 웰(22) 및 P형 웰(23)의 열처리 공정을 생략할 수 있다.Here, the heat treatment process of the N-type well 22 and the P-type well 23 may be omitted by depositing the third insulating layer 27.
이어, 노출된 상기 2 절연막(26)을 제거한 후, 상기 제 1 절연막(24)을 제거한다.Subsequently, after the exposed second insulating layer 26 is removed, the first insulating layer 24 is removed.
이상에서 설명한 바와 같이 본 발명의 반도체 장치의 에스램 셀 제조방법에 있어서는 다음과 같은 효과가 있다.As described above, the method of manufacturing the SRAM cell of the semiconductor device of the present invention has the following effects.
셜로우 트랜치 아이솔레이션 공정 이전에 N형 웰과 P형 웰을 형성하므로 웰 마스크 진행시 발생하는 CD 및 오버레이의 위치 변화원인이 되는 언더 레이 토폴로지(under layer topology)를 제거한다.Since the N-type wells and the P-type wells are formed before the shallow trench isolation process, the under layer topology, which is a cause of the positional change of the CD and the overlay generated during the well mask process, is removed.
따라서, 평판에서 웰 마스크를 진행할 수 있어 정확하게 진행하는 웰 마스크의 CD 및 오버레이의 마진을 확보할 수 있다.Therefore, the well mask can be advanced on the flat plate to secure the margin of the CD and the overlay of the well mask which proceeds correctly.
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