KR20020055118A - A method for forming capacitor in semiconductor device - Google Patents

Abstract

PURPOSE: A method for fabricating a capacitor of a semiconductor device is provided to maximize the surface area of the lower electrode of ruthenium without increasing the height of a capacitor structure, and to guarantee stable capacitance by preventing oxygen from being diffused from the lower electrode of ruthenium to a capacitor lower structure like a polysilicon plug and a barrier metal layer. CONSTITUTION: A lower layer having a predetermined conductive structure and a predetermined insulation structure is formed on a semiconductor substrate. A buffer layer is formed on the lower layer. A chemical vapor deposition(CVD) process is performed to form a ruthenium layer for a lower electrode on the buffer layer. A heat treatment process is performed to cause crystallization and conglomeration of the ruthenium layer for the lower electrode so that the ruthenium layer for the lower electrode is transformed into a hemispherical shape. A dielectric thin film(18) and an upper electrode are formed.

Description

A method for forming capacitor in semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a capacitor forming process in a semiconductor device manufacturing process, and more particularly, to a capacitor forming process of a semiconductor device using a Ru bottom electrode.

As semiconductor memory devices become more integrated, efforts have been made to secure larger capacitances in the same layout area.

Since the capacitance of the capacitor is proportional to the dielectric constant (ε) and the effective surface area of the electrode, and is inversely proportional to the distance between the electrodes, conventionally, many studies have been conducted mainly to secure the surface area of the capacitor lower electrode or to minimize the distance between electrodes by thinning the dielectric. Has been going on. However, thinning of the dielectric has a problem of increasing leakage current. Accordingly, the capacitor structure is formed into a three-dimensional structure such as a planar stack, a concave, and a cylinder to form a capacitor. The method of increasing the effective surface area has been mainly used.

However, with the reduction of design rules associated with high integration of semiconductor devices, the method of securing capacitance through such structural improvements has faced limitations in the process.

Accordingly, research is currently being conducted in the direction of replacing a conventional dielectric material NO (nitride / oxide) thin film with a high dielectric thin film such as Ta ₂ O ₅ , BST, or a ferroelectric thin film such as SBT, PZT, or BLT.

As such, when using a high dielectric film or a ferroelectric thin film, top and bottom electrodes and peripheral processes should be optimized in order to secure dielectric properties. As a result, top and bottom electrode materials such as Ru, Pt, Ir, etc. noble metal) is used. Among these, Ru is used as a representative lower electrode material because it has a property of maintaining conductivity even during oxidation.

However, even when using a dielectric film having a high dielectric constant as described above, it is obvious that it will be difficult to obtain a capacitance that corresponds to future ultra-high density devices, and for this purpose, increasing the height of the capacitor structure makes the subsequent process more difficult. Entails.

The present invention has been proposed to solve the above problems of the prior art, and in particular, it provides a method of forming a capacitor of a semiconductor device capable of securing the capacitance without increasing the height of the capacitor structure using the Ru lower electrode. There is a purpose.

1A-1E are process diagrams of forming a concave capacitor in accordance with one embodiment of the present invention.

2A is a scanning electron microscope (SEM) photograph of the CVD Ru film immediately after deposition.

2B is a scanning electron micrograph of a clustered Ru film formed by a post heat treatment.

3A shows the results of AES analysis of a CVD Ru film immediately after deposition.

Fig. 3B is a view showing the result of AES analysis of the CVD Ru film after the post heat treatment in an oxygen reducing atmosphere.

* Explanation of symbols for the main parts of the drawings

16: TiCl ₄ -TiN film

17: Clustered Ru Layer

18: dielectric thin film

19: metal film for the upper electrode

In order to achieve the above technical problem, the present invention provides a method of forming a capacitor of a semiconductor device, comprising: a first step of forming a lower layer having a predetermined conductive structure and an insulating structure on a semiconductor substrate; Forming a buffer layer on the lower layer; Performing a chemical vapor deposition process to form a Ru film for a lower electrode on the buffer layer; Performing a heat treatment to induce crystallization and agglomeration of the lower electrode Ru film to change the lower electrode Ru film into a hemispherical shape; And a fifth step of forming the dielectric thin film and the upper electrode.

In addition, it is preferable to use a TiCl ₄ -TiN film as the buffer layer.

In addition, the heat treatment is preferably carried out in a rapid heat treatment method at a temperature of 500 ~ 650 ℃.

Further, the heat treatment is preferably carried out in H ₂ / Ar atmosphere or an NH ₃ atmosphere.

In addition, the buffer layer is preferably formed to a thickness of 100 ~ 200Å.

Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

1A to 1E illustrate a process of forming a concave capacitor according to an embodiment of the present invention, which will be described below with reference to the drawings.

First, as shown in FIG. 1A, the lower layer 11 having a predetermined insulating structure and a conductive structure is formed on the silicon substrate 10. The lower layer 11 includes a word line, a bit line, and a plurality of interlayer insulating layers, and forms a lower electrode contact hole through a photo process using a lower electrode contact mask and an interlayer insulating layer etching process. Subsequently, a polysilicon film is deposited on the entire structure and etched back to form a polysilicon plug 12 in the lower electrode contact hole, and then a barrier metal film 13 is deposited on the entire structure and etched back. The polysilicon plug 12 remains on top.

Next, as shown in FIG. 1B, a silicon nitride film 14 and a sacrificial oxide film 15 are deposited on the entire structure.

Subsequently, as shown in FIG. 1C, a photolithography process and an etching process using a charge storage electrode mask are performed to define the charge storage electrode formation region, and the TiCl ₄ -TiN film 16 is 100 to 200 Å thick along the entire structure surface. To be deposited. At this time, the TiCl ₄ -TiN film 16 improves the adhesion between the oxide film and the subsequent CVD Ru film, improves step coverage of the subsequent CVD Ru film, and improves the pore resulting from aggregation of the subsequent CVD Ru film. It is deposited as a buffer layer to act as an electrode for the.

Subsequently, as shown in FIG. 1D, a Ru film of about 500 mV is deposited through a chemical vapor deposition process using Ru precursors such as Ru (od) ₃ and Ru (etcp) ₂ , and 500 to 500 by rapid thermal treatment (RTP). The post-heat treatment is performed at 650 ° C. to coagulate the Ru film simultaneously with crystallization to form a hemispherical clustered Ru layer 17. At this time, the Ru film deposition process is carried out in a low temperature O ₂ atmosphere of 230 ~ 260 ℃, it is preferable to perform the post-heat treatment in an oxygen reduction atmosphere such as NH ₃ atmosphere or Ar / H ₂ atmosphere.

Next, as shown in FIG. 1E, the dielectric thin film 18 and the metal film 19 for the upper electrode are deposited, and a subsequent process is performed.

2A is a scanning electron microscope (SEM) photograph of a CVD Ru film immediately after deposition, and FIG. 2B is a scanning electron microscope photograph of a clustered Ru film formed by a post-heat treatment, and has a shape like a hemispherical silicon grain (HSG). It can be seen that the surface state is formed to increase the lower electrode surface area.

On the other hand, Figure 3a is a view showing the results of the AES analysis of the CVD Ru film immediately after the deposition, Figure 3b is a view showing the results of the AES analysis of the CVD Ru film after the post-heat treatment in the oxygen reduction atmosphere, By post-heat treatment, it is confirmed that the oxygen remaining in the thin film is added to aid source decomposition during CVD Ru film deposition. Thus, by using the oxygen-removed Ru film as the lower electrode, it is possible to prevent the oxidation of the barrier metal or polysilicon plug by the diffusion of oxygen.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

For example, in the above-described embodiment, a capacitor having a concave structure has been described as an example, but the present invention can also be applied to a capacitor forming process having another structure such as a simple stack, a planar stack, a cylinder, and the like.

The present invention described above maximizes the surface area of the Ru lower electrode without increasing the height of the capacitor structure, and prevents the diffusion of oxygen from the Ru lower electrode to the capacitor lower structure, that is, the polysilicon plug and the barrier metal layer, thereby ensuring stable capacitance. It works.

Claims (5)

In the method of forming a capacitor of a semiconductor device, Forming a lower layer having a predetermined conductive structure and an insulating structure on the semiconductor substrate; Forming a buffer layer on the lower layer; Performing a chemical vapor deposition process to form a Ru film for a lower electrode on the buffer layer; Performing a heat treatment to induce crystallization and agglomeration of the lower electrode Ru film to change the lower electrode Ru film into a hemispherical shape; And Fifth Step of Forming Dielectric Thin Film and Upper Electrode Capacitor formation method of a semiconductor device comprising a. The method of claim 1, The buffer layer, A method of forming a capacitor of a semiconductor device, characterized in that the TiCl ₄ -TiN film. The method according to claim 1 or 2, The heat treatment is, A method for forming a capacitor of a semiconductor device, characterized in that the rapid heat treatment at a temperature of 500 ~ 650 ℃. The method of claim 3, The heat treatment is, A method of forming a capacitor of a semiconductor device, characterized in that carried out in H ₂ / Ar atmosphere or NH ₃ atmosphere. The method according to claim 1 or 2, The buffer layer, A capacitor forming method of a semiconductor device, characterized in that formed to a thickness of 100 ~ 200Å.