KR20020054846A - EPROM device and method for manufacturing the same - Google Patents
EPROM device and method for manufacturing the same Download PDFInfo
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- KR20020054846A KR20020054846A KR1020000084070A KR20000084070A KR20020054846A KR 20020054846 A KR20020054846 A KR 20020054846A KR 1020000084070 A KR1020000084070 A KR 1020000084070A KR 20000084070 A KR20000084070 A KR 20000084070A KR 20020054846 A KR20020054846 A KR 20020054846A
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- 238000000034 method Methods 0.000 title abstract description 10
- 238000004519 manufacturing process Methods 0.000 title description 13
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 239000004065 semiconductor Substances 0.000 claims abstract description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 15
- 229920005591 polysilicon Polymers 0.000 claims abstract description 15
- 239000012535 impurity Substances 0.000 claims abstract description 11
- 238000000059 patterning Methods 0.000 claims description 3
- 230000008878 coupling Effects 0.000 abstract description 9
- 238000010168 coupling process Methods 0.000 abstract description 9
- 238000005859 coupling reaction Methods 0.000 abstract description 9
- 238000009413 insulation Methods 0.000 abstract 2
- 235000019592 roughness Nutrition 0.000 abstract 1
- 238000005530 etching Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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Abstract
Description
본 발명은 반도체 메모리 소자의 제조방법에 관한 것으로, 특히 커플링 비(coupling ratio)를 증가시키는데 적당한 EPROM 소자 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to an EPROM device suitable for increasing a coupling ratio and a method of manufacturing the same.
일반적으로 반도체 기억 소자 중에서 EPROM(Erasable Programmable ROM)은 구조상 플로팅(floating) 게이트와 콘트롤(control) 게이트를 갖는 것에 특징이 있으며, 이들 게이트들은 불순물 원소로서 인등이 도핑(doping)된 폴리 실리콘막으로 형성된다.In general, EPROM (Erasable Programmable ROM) is characterized by having a floating gate and a control gate in structure, and these gates are formed of a doped polysilicon film as an impurity element. do.
한편, 상기 플로팅 게이트는 게이트 산화막에 의해서 기판 영역과 분리되고 기판 영역은 채널을 형성하는 소오스와 드레인을 포함하고 있다.Meanwhile, the floating gate is separated from the substrate region by a gate oxide film, and the substrate region includes a source and a drain forming a channel.
그리고 플로팅 게이트와 콘트롤 게이트는 절연층, 예를 들면 산화막과 같은 절연물질로 분리되어 있다.The floating gate and the control gate are separated by an insulating layer, for example, an insulating material such as an oxide film.
상기와 같은 EPROM이 동작하는 주요 원리는 게이트 전극과 드레인에 정의 고전압을 인가하여 드레인 부근에서 발생하는 고에너지를 가진 전자를 게이트 산화막의 포텐셜 웰을 넘게 하여 플로팅 게이트에 주입시켜 이렇게 해서 플로팅 게이트 전극에 주입된 전자의 전하량에 의하여 셀 트랜지스터의 드레시 홀드 값이 변화하여 프로그램 된다.The main principle of the operation of the EPROM is to apply a positive high voltage to the gate electrode and the drain and inject electrons with high energy generated near the drain into the floating gate beyond the potential well of the gate oxide film. The threshold value of the cell transistor is changed and programmed according to the charge amount of the injected electrons.
그리고 게이트 산화막의 포텐셜 웰 이상의 에너지를 가진 자외선을 셀에 조사하면 플로팅 게이트에 축적된 전자는 다시 기판으로 돌아가 프로그램 소거되는 동작원리를 갖는다.When the ultraviolet rays having energy above the potential well of the gate oxide film are irradiated to the cell, electrons accumulated in the floating gate return to the substrate and have a program principle of erasing.
한편, EPROM 셀의 동작에 있어서, 커플링 비(coupling ratio)는 중요한 요소로 작용한다.On the other hand, in the operation of the EPROM cell, the coupling ratio (coupling ratio) acts as an important factor.
보통 IPO(Inter Poly Oxide)로서는 산화막이나 ONO(Oxide Nitride Oxide)막을 사용한다.Usually, as an IPO (Inter Poly Oxide), an oxide film or an ONO (Oxide Nitride Oxide) film is used.
상기 ONO막을 IPO막으로 사용하는 경우는 산화막만으로 IPO막으로 사용하는 경우보다 캐패시턴스(capacitance) 측면에서 잇점이 있다.The use of the ONO film as an IPO film has an advantage in terms of capacitance compared to the case of using only an oxide film as an IPO film.
일반적으로 커플링 비(CR)는 수학식 1과 같다.In general, the coupling ratio CR is represented by Equation 1 below.
즉, Vpp는 제어 게이트에 인가되는 전압이고, VFG는 부유 게이트에 걸리는 전압이다.That is, Vpp is the voltage applied to the control gate, and V FG is the voltage across the floating gate.
또한, 커플링 비는 수학식 2와 같이 표현된다.In addition, the coupling ratio is expressed by Equation (2).
그러므로 ONO막에 전자를 효과적으로 트랩(trap)시키기 위해서는 CIPO의 증가가 필요하다.Therefore, in order to effectively trap electrons in the ONO film, an increase in C IPO is required.
이하, 첨부된 도면을 참고하여 종래의 EPROM 소자의 제조방법을 설명하면 다음과 같다.Hereinafter, a manufacturing method of a conventional EPROM device will be described with reference to the accompanying drawings.
도 1a 내지 도 1b는 종래의 EPROM 소자의 제조방법을 나타낸 공정단면도이다.1A to 1B are process cross-sectional views showing a conventional method for manufacturing an EPROM device.
도 1a에 도시한 바와 같이, 반도체 기판(11)상에 게이트 절연막(12)을 형성하고, 상기 게이트 절연막(12)상에 부유 게이트(floating gate)용 제 1 폴리 실리콘막(13)을 증착한다.As shown in FIG. 1A, a gate insulating film 12 is formed on a semiconductor substrate 11, and a first polysilicon film 13 for floating gate is deposited on the gate insulating film 12. .
이어, 상기 제 1 폴리 실리콘막(13)상에 ONO(Oxide Nitride Oxide)막(14)을 형성하고, 상기 ONO막(14)상에 제어 게이트용 제 2 폴리 실리콘막(15)을 증착한다.Next, an ONO (Oxide Nitride Oxide) film 14 is formed on the first polysilicon film 13, and a second polysilicon film 15 for a control gate is deposited on the ONO film 14.
도 1b에 도시한 바와 같이, 포토 및 식각공정을 통해 상기 제 2 폴리 실리콘막(15), ONO막(14), 제 1 폴리 실리콘막(13), 게이트 절연막(12)을 선택적으로 제거하여 제어 게이트(15a)와 부유 게이트(13a)를 형성한다.As shown in FIG. 1B, the second polysilicon film 15, the ONO film 14, the first polysilicon film 13, and the gate insulating film 12 are selectively removed through photo and etching processes. The gate 15a and the floating gate 13a are formed.
이후 공정은 도면에 도시하지 않았지만, 상기 제어 게이트(15a)를 마스크로 이용하여 반도체 기판(11)의 전면에 소오스/드레인용 불순물 이온을 주입하여 상기 부유 게이트(13a) 양측의 반도체 기판(11) 표면내에 소오스/드레인 불순물 영역을 형성한다.Since the process is not shown in the drawing, the source / drain impurity ions are implanted into the entire surface of the semiconductor substrate 11 using the control gate 15a as a mask so that the semiconductor substrate 11 on both sides of the floating gate 13a is formed. Source / drain impurity regions are formed in the surface.
그러나 상기와 같은 종래의 EPROM 소자의 제조방법에 있어서 다음과 같은 문제점이 있었다.However, in the conventional method of manufacturing the EPROM device as described above has the following problems.
즉, 단위 면적 당 커플링 비를 증가시키는데 그 한계가 있다.That is, there is a limit to increasing the coupling ratio per unit area.
본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로 단위 면적 당 커플링 비를 증가시키도록 한 EPROM 소자 및 그 제조방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide an EPROM device and a method of manufacturing the same, which have been devised to solve the above-mentioned conventional problems and to increase the coupling ratio per unit area.
도 1a 내지 도 1b는 종래의 EPROM 소자의 제조방법을 나타낸 공정단면도1A to 1B are cross-sectional views illustrating a method of manufacturing a conventional EPROM device.
도 2는 본 발명에 의한 EPROM 소자를 나타낸 단면도2 is a cross-sectional view showing an EPROM device according to the present invention;
도 3a 내지 도 3c는 본 발명에 의한 EPROM 소자의 제조방법을 나타낸 공정단면도3A to 3C are cross-sectional views illustrating a method of manufacturing an EPROM device according to the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
21 : 반도체 기판 22 : 게이트 절연막21 semiconductor substrate 22 gate insulating film
23 : 부유 게이트 24 : 감광막23: floating gate 24: photosensitive film
25 : 트랜치 26 : ONO막25: trench 26: ONO film
27 : 제어 게이트27: control gate
상기와 같은 목적을 달성하기 위한 본 발명에 의한 EPROM 소자는 반도체 기판상에 형성되는 게이트 절연막과, 상기 게이트 절연막상에 복수개의 요철(凹凸)을갖고 형성되는 부유 게이트와, 상기 부유 게이트상에 형성되는 ONO막과, 상기 ONO막상에 형성되는 제어 게이트와, 상기 부유 게이트 양측의 반도체 기판 표면내에 형성되는 소오스/드레인 불순물 영역을 포함하여 구성됨을 특징으로 한다.An EPROM device according to the present invention for achieving the above object comprises a gate insulating film formed on a semiconductor substrate, a floating gate formed with a plurality of irregularities on the gate insulating film, and formed on the floating gate. And an ONO film, a control gate formed on the ONO film, and a source / drain impurity region formed in a surface of the semiconductor substrate on both sides of the floating gate.
또한, 상기와 같은 목적을 달성하기 위한 본 발명에 의한 EPROM 소자의 제조방법은 반도체 기판상에 게이트 절연막 및 폴리 실리콘막을 형성하는 단계와, 상기 폴리 실리콘막 및 게이트 절연막을 길이 방향으로 패터닝하여 부유 게이트를 형성하는 단계와, 상기 부유 게이트를 폭 방향으로 선택적으로 제거하여 소정 깊이를 갖는 복수개의 요철을 형성하는 단계와, 상기 부유 게이트를 포함한 반도체 기판의 전면에 ONO막 및 제어 게이트를 형성하는 단계와, 상기 부유 게이트 양측의 반도체 기판 표면내에 소오스/드레인 불순물 영역을 형성하는 단계를 포함하여 형성함을 특징으로 한다.In addition, the method for manufacturing an EPROM device according to the present invention for achieving the above object is a step of forming a gate insulating film and a polysilicon film on a semiconductor substrate, by patterning the polysilicon film and the gate insulating film in the longitudinal direction floating gate Forming a plurality of irregularities having a predetermined depth by selectively removing the floating gate in a width direction, and forming an ONO film and a control gate on the entire surface of the semiconductor substrate including the floating gate; And forming a source / drain impurity region in a surface of the semiconductor substrate at both sides of the floating gate.
이하, 첨부된 도면을 참고하여 본 발명에 의한 EPROM 소자 및 그 제조방법을 상세히 설명하면 다음과 같다.Hereinafter, an EPROM device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.
도 2는 본 발명에 의한 EPROM 소자의 채널 폭 방향을 나타낸 단면도이다.2 is a cross-sectional view showing a channel width direction of an EPROM device according to the present invention.
도 2에 도시된 바와 같이, 소자 격리막(도시되지 않음)이 형성된 반도체 기판(21)상에 형성되는 게이트 절연막(22)과, 상기 게이트 절연막(22)상에 복수개의 요철(凹凸)을 갖고 형성되는 부유 게이트(23)와, 상기 부유 게이트(23)상에 형성되는 ONO막(26)과, 상기 ONO막(26)상에 형성되는 제어 게이트(27)와, 상기 부유 게이트(23) 양측의 반도체 기판(21) 표면내에 형성되는 소오스/드레인 불순물 영역(도시되지 않음)을 포함하여 구성된다.As shown in FIG. 2, a gate insulating film 22 is formed on a semiconductor substrate 21 on which an element isolation film (not shown) is formed, and a plurality of irregularities are formed on the gate insulating film 22. Floating gate 23, the ONO film 26 formed on the floating gate 23, the control gate 27 formed on the ONO film 26, and both sides of the floating gate 23. And a source / drain impurity region (not shown) formed in the surface of the semiconductor substrate 21.
도 3a 내지 도 3c는 본 발명에 의한 EPROM 셀의 제조방법을 나타낸 공정단면도이다.3A to 3C are cross-sectional views illustrating a method of manufacturing an EPROM cell according to the present invention.
도 3a에 도시한 바와 같이, 필드 영역과 활성 영역으로 정의된 반도체 기판(21)의 필드 영역에 필드 산화막(도시되지 않음)을 형성하고, 상기 반도체 기판(21)상에 게이트 절연막(22)을 형성하고, 상기 게이트 절연막(22)상에 부유 게이트용 제 1 폴리 실리콘막을 증착한다.As shown in FIG. 3A, a field oxide film (not shown) is formed in the field region of the semiconductor substrate 21 defined as the field region and the active region, and a gate insulating film 22 is formed on the semiconductor substrate 21. The first polysilicon film for the floating gate is deposited on the gate insulating film 22.
이어, 포토 및 식각공정을 통해 채널 길이(channel length) 방향으로 제 1 폴리 실리콘막 및 게이트 절연막(22)을 패터닝하여 부유 게이트(23)를 형성한다.Subsequently, the floating gate 23 is formed by patterning the first polysilicon layer and the gate insulating layer 22 in a channel length direction through photo and etching processes.
도 3b에 도시한 바와 같이, 상기 부유 게이트(23)상에 감광막(24)을 도포한 후, 노광 및 현상공정으로 감광막(24)을 채널 폭(width) 방향으로 패터닝(patterning)한다.As shown in FIG. 3B, the photoresist film 24 is coated on the floating gate 23, and then the photoresist film 24 is patterned in the channel width direction by an exposure and development process.
그리고 상기 패터닝된 감광막(24)을 마스크로 이용하여 상기 부유 게이트(23)를 선택적으로 제거하여 소정깊이를 갖는 복수개의 트랜치(25)를 형성하여 부유 게이트(23)의 표면에 요철(凹凸)을 형성한다.By using the patterned photoresist 24 as a mask, the floating gate 23 is selectively removed to form a plurality of trenches 25 having a predetermined depth, thereby forming irregularities on the surface of the floating gate 23. Form.
도 3c에 도시한 바와 같이, 상기 감광막(24)을 제거하고, 상기 트랜치(25)를 포함한 부유 게이트(23)의 전면에 ONO막(26)을 형성하며, 상기 ONO막(26)상에 제 2 폴리 실리콘막을 증착한 후 패터닝하여 제어 게이트(27)를 형성한다.As shown in FIG. 3C, the photosensitive film 24 is removed, and an ONO film 26 is formed on the entire surface of the floating gate 23 including the trench 25, and on the ONO film 26. 2 polysilicon film is deposited and then patterned to form the control gate 27.
이후 공정은 도면에 도시하지 않았지만 상기 제어 게이트(27a)를 마스크로 이용하여 상기 반도체 기판(21)의 전면에 소오스/드레인용 불순물 이온을 주입하여 상기 부유 게이트(23) 양측의 반도체 기판(21) 표면내에 소오스/드레인 불순물 영역을 형성한다.Since the process is not shown in the drawing, the source / drain impurity ions are implanted into the entire surface of the semiconductor substrate 21 using the control gate 27a as a mask, thereby forming the semiconductor substrate 21 on both sides of the floating gate 23. Source / drain impurity regions are formed in the surface.
본 발명의 EPROM 소자는 부유 게이트(23)가 채널 폭 방향으로만 선택적으로 식각됨으로 게이트 길이 방향으로는 종래와 아무런 차이가 없다.In the EPROM device of the present invention, since the floating gate 23 is selectively etched only in the channel width direction, there is no difference in the gate length direction.
일반적으로 캐패시턴스 용량을 증대시키기 위해서는 면적을 넓히는 방법이 필요하다. 보통의 경우 칩 자체의 면적이 증가되는 것을 피할 수 없다.In general, in order to increase capacitance capacity, a method of enlarging an area is required. Normally, the area of the chip itself is unavoidable.
그러나 본 발명은 부유 게이트의 채널 길이 방향으로는 변화없이 폭 방향으로만 선택적으로 식각함으로 높은 캐패시턴스를 얻을 수 있다. 즉 CIPO를 증가시킬 수 있다.However, the present invention can obtain high capacitance by selectively etching only in the width direction without change in the channel length direction of the floating gate. That is, it can increase the C IPO .
이상에서 설명한 바와 같이 본 발명에 의한 EPROM 소자 및 그의 제조방법은 다음과 같은 효과가 있다.As described above, the EPROM device and its manufacturing method according to the present invention have the following effects.
즉, 단위 면적 당 CIPO를 증가시키어 커플링 비를 증가시킬 수 있다.That is, the coupling ratio may be increased by increasing C IPO per unit area.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040022489A (en) * | 2002-09-07 | 2004-03-16 | 아남반도체 주식회사 | Method for manufacturing flash device in semiconductor |
| CN102282651A (en) * | 2009-01-29 | 2011-12-14 | 国际商业机器公司 | Memory transistor with a non-planar floating gate and manufacturing method thereof |
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2000
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040022489A (en) * | 2002-09-07 | 2004-03-16 | 아남반도체 주식회사 | Method for manufacturing flash device in semiconductor |
| CN102282651A (en) * | 2009-01-29 | 2011-12-14 | 国际商业机器公司 | Memory transistor with a non-planar floating gate and manufacturing method thereof |
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