KR20020054630A - DRAM cell and Method for manufacturing the same - Google Patents

Abstract

PURPOSE: A DRAM(Dynamic Random Access Memory) cell is provided to simplify manufacturing processes by forming an MISSM(Metal-Insulator-Semi-Semi-Metal) shaped diode-type structure. CONSTITUTION: A pad oxide(43), a nitride(45), a tungsten layer(47) as a bit line, and a first semiconductor substrate(31) having a p-type dopants region(51) are sequentially formed on a second semiconductor substrate(41). Isolation layers(49) are formed on both sidewalls of the resultant structure. Then, a word line(55) is formed on the upper portion of the resultant structure, after forming a gate oxide(53). At this time, the diode-type resultant structure has an MISSM shape from the tungsten layer(47) to the word line(55).

Description

DDR cell and method for manufacturing the same {DRAM cell and Method for manufacturing the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DRAM (Dynamic Random Access Memory) cell and a method of manufacturing the same. In particular, a diode-type DRAM cell having a metal-insulator-semi-semi-metal (MISSM) structure is formed to form a device. The present invention relates to a DRAM cell and a method for manufacturing the same, which reduce cost and improve device integration and characteristics.

In general, a DRAM cell consists of one bit line, one word line, one access transistor, and one storage capacitor. The drain of the access transistor is connected to the line and forms the so-called horizontal structure connected to the bit line.

In order to increase the integration of such DRAM cells, many types of cell arrays and structures thereof have been proposed.

Hereinafter, a method of manufacturing a DRAM cell according to the prior art will be described with reference to the accompanying drawings.

As shown in FIG. 1A, a gate oxide film 12, a first polycrystalline silicon, a first oxide film, and a first photoresist film are sequentially formed on the semiconductor substrate 11, and then the first photoresist film is formed so that only the portion where the gate electrode is to be formed remains. After the selective exposure and development, the first and second gate electrodes having a larger width than the vertical length by selectively etching the first polycrystalline silicon and the first oxide film using the selectively exposed and developed first photoresist layer as a mask ( 13 and 14 and a gate cap oxide film 15 are formed to remove the first photoresist film.

In addition, impurity ions are implanted and drive-in diffused into the semiconductor substrate 11 by using the first and second gate electrodes 13 and 14 as masks, so that both sides of the first and second gate electrodes 13 and 14 are provided. A plurality of impurity regions 16 are formed in the surface of the semiconductor substrate 11.

As shown in FIG. 1B, a nitride layer is formed on the surface of the gate oxide layer 12 including the first and second gate electrodes 13 and 14 and the gate cap oxide layer 15 and then etched back to form the first and second gate electrodes. After the nitride film sidewalls 17 are formed on both sides of the gate electrodes 13 and 14 and the gate cap oxide film 15, the second oxide film 18 is formed on the entire surface, and then first planarized by a planarization process.

As shown in FIG. 1C, after the second photoresist layer 19 is sequentially formed on the second oxide layer 18, only the portion where the storage node contact of the capacitor is to be formed is formed. After selectively exposing and developing to be removed, the first contact hole is formed by selectively etching the second oxide film 18 and the gate oxide film 12 using the selectively exposed and developed second photosensitive film 19 as a mask. do.

As shown in FIG. 1D, the second photoresist film 19 is removed, and a second polycrystalline silicon and a third photoresist film 20 are sequentially formed on the exposed semiconductor substrate 11 and the second oxide film 18. And selectively exposing and developing the third photoresist film 20 so as to remain only at a portion where the storage node is to be formed, and then selectively using the second exposed photosensitive film 20 as a mask to selectively select the second polycrystalline silicon. Etching forms a storage node 21 electrically connected to the impurity region 16.

As shown in FIG. 1E, the third photoresist layer 20 is removed, and then a dielectric layer 22 is formed on the surface of the storage node 21. Subsequently, a third polycrystalline silicon and a fourth photoresist layer 23 are sequentially formed on the second oxide layer 18 including the dielectric layer 22. The fourth photoresist layer 23 is formed only at a portion where a plate electrode is to be formed. After selectively exposing and developing to remain, the plate electrode 24 is formed by selectively etching the third polycrystalline silicon using the selectively exposed and developed fourth photosensitive film 23 as a mask. Here, a capacitor is formed of the storage node 21, the dielectric layer 22, and the plate electrode 24.

As shown in FIG. 1F, the fourth photoresist film 23 is removed, a third oxide film 25 is formed on the second oxide film 18 including the capacitor, and then second planarized by a planarization process. Subsequently, after the fifth photoresist layer 26 is coated on the third oxide layer 25, the fifth photoresist layer 26 is selectively exposed and developed to remove only a portion where a bit line contact is to be formed, and then selectively A second contact hole is formed by selectively etching the third oxide film 25, the second oxide film 18, and the gate oxide film 12 using the exposed and developed fifth photosensitive film 26 as a mask.

As shown in FIG. 1G, after removing the fifth photosensitive film 26, a conventional DRAM cell is formed by forming a metal layer 27 on the exposed semiconductor substrate 11 and the third oxide film 25. Here, a bit line is formed of the metal layer 27.

The conventional DRAM cell and its manufacturing method are difficult to form a small size capacitor because the DRAM cell is composed of one bit line, one word line, one access transistor, and one storage capacitor. As a result, it is difficult to proceed with subsequent processes, the process in the peripheral region is complicated, and there is a limit in the size reduction of the transistor, thereby degrading the high integration of the device.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a DRAM cell and a method of manufacturing the same, which form a diode-type DRAM cell having a MISSM structure.

1A to 1G are cross-sectional views illustrating a method of forming a DRAM cell according to the prior art.

2 is a cross-sectional view illustrating a DRAM cell according to an embodiment of the present invention.

3A to 3F are cross-sectional views illustrating a method of forming a DRAM cell according to an embodiment of the present invention.

4A and 4B are diagrams illustrating tunneling currents according to states of a depletion layer and an inversion layer of the present invention.

5 is a view showing a switching voltage and a switching current according to the thickness of the gate oxide film of the present invention.

<Description of Symbols for Main Parts of Drawings>

31: first semiconductor substrate 33: hydrogen ions

41 second semiconductor substrate 43 pad oxide film

45 nitride film 47 tungsten layer

49 device isolation layer 51 p-type impurity region

53 gate oxide film 55 word line

A DRAM cell according to the present invention is a laminate formed by sequentially stacking an intrinsic semiconductor substrate having a pad oxide film, a nitride film, a metal layer serving as a bit line, and a second conductive impurity region on a first conductive semiconductor substrate in an active region, And a word isolation layer formed on the first conductive semiconductor substrate on both sides of the stack and a word line formed on the stack with a gate insulating film interposed therebetween.

The method for manufacturing a DRAM cell according to the present invention is to form a diode-type DRAM cell having a MISSM structure, the method comprising: preparing a first semiconductor substrate having a etch stop layer and an intrinsic first semiconductor substrate, Sequentially forming a pad insulating film, an insulating film, and a bit line on the second semiconductor substrate, bonding the first and second semiconductor substrates, and placing the first semiconductor substrate on the bit line, the etch stop Etching the first semiconductor substrate with a layer as an etch endpoint, forming a device isolation layer in the device isolation region on the second semiconductor substrate, and forming a second conductivity type impurity region in the surface of the first semiconductor substrate in the active region. Forming a word line via a gate insulating film on the first semiconductor substrate of the active region. It features.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of a DRAM cell and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a cross-sectional view illustrating a DRAM cell according to an embodiment of the present invention, and FIGS. 3A to 3G are cross-sectional views illustrating a method of forming a DRAM cell according to an embodiment of the present invention.

The DRAM cell according to the embodiment of the present invention has a MISSM structure, as shown in FIG. 2, wherein tungsten acts as a pad oxide film 43, a nitride film 45, and a bit line in an active region on an n-type second semiconductor substrate 41. A stack formed by sequentially stacking a first semiconductor substrate 31 having a layer 47 and a p-type impurity region 51 thereon, and an isolation layer 49 formed on the semiconductor substrate 41 on both sides of the stack. And a word line 55 formed on the stack with a gate oxide film 53 interposed therebetween.

A method of forming a DRAM cell according to an embodiment of the present invention is to form a diode-type DRAM cell having a MISSM structure, as shown in FIG. 3A, wherein the first semiconductor substrate 31 and the n-type second semiconductor, which are not doped with impurities, are formed. The substrate 41 is prepared.

As shown in FIG. 3B, a high concentration of hydrogen (H) ions 33 are ion implanted into the first semiconductor substrate 31.

Here, the region in which the hydrogen (H) ions 33 are ion-implanted serves as an etch stop layer.

In addition, a pad oxide film 43, a nitride film 45, and the like are sequentially formed on the second semiconductor substrate 41.

Here, the tungsten layer 47 serves as a bit line of the DRAM cell.

As illustrated in FIG. 3C, the first and second semiconductor substrates 31 and 41 are bonded to the first tungsten layer 47 so that the first semiconductor substrate 31 is positioned.

As shown in FIG. 3D, the first semiconductor substrate 31 is etched by a smart-cut method or a chemical mechanical polishing method using the etch stop layer as an etch end point.

An amorphous silicon layer may be formed instead of the first semiconductor substrate 31 on the first tungsten layer 47.

As shown in FIG. 3E, the device isolation layer 49 is formed in the device isolation region by a general shallow trench isolation (STI) process.

The p-type impurity region 51 is formed in the surface of the first semiconductor substrate 31 by performing ion implantation and drive-in of the p-type impurity on the entire surface.

Here, the second semiconductor substrate 41 and the p-type impurity region 51 are used as electrodes of a junction capacitor of a DRAM cell, and the pad oxide film 43, the nitride film 45, and the tungsten layer 47 which are layers therebetween. ) And the first semiconductor substrate 31 are used as the dielectric film of the junction capacitor of the DRAM cell.

As shown in FIG. 3F, a thermal oxide film is grown on the entire surface, and then a polycrystalline silicon layer and a photoresist film are sequentially formed on the thermal oxide film.

After selectively exposing and developing the photoresist film so as to remain only at the portion where the gate electrode is to be formed, the polycrystalline silicon layer and the thermal oxide film are selectively etched using the selectively exposed and developed photoresist mask as a mask to form a gate oxide 53 and a word. Line 55 is formed and the photoresist film is removed.

The operation of the DRAM cell according to the embodiment of the present invention described above is as follows.

When data is present in the tungsten layer 47 which is the bit line, the word line 55 is formed according to a carrier stored in the junction capacitor between the p-type impurity region 51 and the second semiconductor substrate 41. ), The width of the depletion layer formed in the p-type impurity region 51 below changes.

That is, the data is sensed by the tunneling current flowing toward the word line 55 when the depletion layer and the reverse anti-lamination of the p-type impurity region 51 are formed by the bias of the word line 55.

First, as shown in FIG. 4A, when the depletion layer is wider than the inverting layer and the threshold voltage is small, that is, when the depletion layer is a depletion layer, the state is “o”.

In addition, as shown in FIG. 4B, in the case of the reverse inversion layer, more current flows through the tunneling current through the word line 55 than in the case of the depletion layer.

At this time, the switching voltage and the switching current according to the thickness of the gate oxide film 53 are as shown in FIG. 5.

In other words, the thicker the gate oxide layer 53 is, the smaller the switching voltage and the switching current become.

In FIG. 5, the holding voltage senses the difference between the switching current by the switching voltage and the current in which the voltage is applied to the word line 55 to maintain the voltage applied to the bit line.

The diode-type DRAM cell of the MISSM structure of the present invention described above is applied to a sensing element for sensing the degree of bias applied to the tungsten layer 47 through the word line 55 by a tunneling diode sensing method or a general Zener ( Zener) can be used in a device capable of maintaining a reference voltage at all times by a bias applied to the tungsten layer 47 in the same manner as a diode.

Alternatively, the device may be used as an element for discharging electric charges through the tungsten layer 47 or the word line 55 in the ESD (Elector Static Discharge).

Since the DRAM cell of the present invention and a method of manufacturing the same form a diode type DRAM cell having a MISSM structure, there is an effect of reducing the cost of device formation and improving the integration and characteristics of the device for the following reasons.

First, it does not form a capacitor, which simplifies the process of the peripheral circuit, facilitates the subsequent process by reducing the step height of the device, and reduces the area occupied by the device, thereby improving the chip generation rate per wafer.

Second, since the bit line is formed of a tungsten layer, the resistance of the bit line is lowered.

Claims (2)

A stack formed by sequentially stacking an intrinsic semiconductor substrate having a pad oxide film, a nitride film, a metal layer serving as a bit line, and a second conductive impurity region on a first conductive semiconductor substrate in an active region; An isolation layer formed on the first conductive semiconductor substrate on both sides of the stack; And a word line formed on the stack with a gate insulating film interposed therebetween. By forming a diode-type DRAM cell of the MISSM structure, Preparing an intrinsic first semiconductor substrate and an intrinsic second semiconductor substrate with an etch stop layer; Sequentially forming a pad insulating film, an insulating film, and a bit line on the second semiconductor substrate; Bonding the first and second semiconductor substrates, wherein the first semiconductor substrate is positioned on the bit line; Etching the entire first semiconductor substrate with the etch stop layer as an etch endpoint; Forming an isolation layer in the isolation region on the second semiconductor substrate; Forming a second conductivity type impurity region in the surface of the first semiconductor substrate of the active region; And forming a word line on the first semiconductor substrate in the active region via a gate insulating film.