KR20020053947A - Method for forming metal pad of semiconductor device - Google Patents
Method for forming metal pad of semiconductor device Download PDFInfo
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- KR20020053947A KR20020053947A KR1020000081926A KR20000081926A KR20020053947A KR 20020053947 A KR20020053947 A KR 20020053947A KR 1020000081926 A KR1020000081926 A KR 1020000081926A KR 20000081926 A KR20000081926 A KR 20000081926A KR 20020053947 A KR20020053947 A KR 20020053947A
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- metal
- film
- interlayer insulating
- pad
- insulating film
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 93
- 239000002184 metal Substances 0.000 title claims abstract description 93
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000000034 method Methods 0.000 title claims abstract description 14
- 239000011229 interlayer Substances 0.000 claims abstract description 31
- 239000010410 layer Substances 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 5
- 239000000853 adhesive Substances 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 5
- 239000010936 titanium Substances 0.000 description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 238000012858 packaging process Methods 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000011806 microball Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H01L24/03—Manufacturing methods
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
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- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 상세하게는, 패키징 공정에서 금속 패드의 벗겨짐(peel-off) 현상을 효과적으로 방지할 수 있는 반도체 소자의 금속 패드 형성방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a metal pad of a semiconductor device that can effectively prevent the peel-off phenomenon of the metal pad in the packaging process.
적층 구조로 이루어진 반도체 소자에 있어서, 통상, 최상부에는 금속 패드가 배치된다. 이러한 금속 패드는 제조 완료된 반도체 소자, 즉, 웨이퍼 상태로 제작된 수 개의 반도칩들에 대한 패키징 공정에서 외부 회로와의 전기적 접속을 위해 구비되는 것이며, 그 종래의 구조는 다음과 같다.In a semiconductor device having a laminated structure, a metal pad is usually disposed at the top. The metal pad is provided for electrical connection with an external circuit in a packaging process for fabricated semiconductor devices, that is, several semiconductor chips manufactured in a wafer state. The conventional structure is as follows.
도 1은 종래의 금속 패드 구조를 도시한 단면도로서, 도시된 바와 같이, 금속 패드는 개략적으로 제1금속막(2)과 제2금속막(6) 사이에 층간절연막(3, 4)이 개재되어 있는 구조를 갖는다. 여기서, 상기 제1 및 제2금속막(2, 6)은, 바람직하게, 알루미늄(Al)막, 또는 티타늄/알루미늄(Ti/Al)막이다.1 is a cross-sectional view showing a conventional metal pad structure, and as shown, the metal pad is roughly interposed between the first metal film 2 and the second metal film 6 with interlayer insulating films 3 and 4 interposed therebetween. It has a structure. Here, the first and second metal films 2 and 6 are preferably aluminum (Al) films or titanium / aluminum (Ti / Al) films.
도 1에서, 미설명된 도면부호 1은 PE-TEOS(Plasma Enhanced Tetra Ethyl Ortho Silicate)막, 3은 SOG(Spin On Glass)막, 4는 PE-TEOS막, 5는 티타늄/티타늄질화(Ti/TiN)막의 베리어막, 7은 티타늄질화(TiN)막의 반사방지막, 그리고, 8은 FP-TEOS의 보호막을 각각 나타낸다.In FIG. 1, reference numeral 1 denotes a Plasma Enhanced Tetra Ethyl Ortho Silicate (PE-TEOS) film, 3 is a spin on glass (SOG) film, 4 is a PE-TEOS film, and 5 is titanium / titanium nitride (Ti / The barrier film of the TiN) film, 7 represents an antireflection film of a titanium nitride (TiN) film, and 8 represents a protective film of FP-TEOS.
그러나, 상기와 같은 구조의 금속 패드를 갖는 반도체 소자는 후속의 패키징 공정에서 마이크로 볼 그리드 어레이(μ-Ball Grid Array : 이하, μ-BGA) 패키지 구조에 적용할 경우, 상기 금속 패드의 벗겨짐(peel-off) 현상에 기인된 불량이 빈번하게 발생되는 문제점이 있다.However, when the semiconductor device having the metal pad of the above structure is applied to a micro-ball grid array (μ-BGA) package structure in a subsequent packaging process, the metal pad may be peeled off. -off) There is a problem that the defect caused by the phenomenon frequently occurs.
여기서, 상기 금속 패드의 벗겨짐 현상은 제1금속막과 층간절연막, 그리고, 제2금속막간의 물성 차이에 기인한 것으로, 예컨데, 제2금속막과 SOG막 사이의 접착력(Adhesion)이 작은 것에 기인해서 와이어 본딩시에 리드(lead)로부터 인가된 데미지에 의해서 상기 제2금속막이 금속 패드 구조로부터 쉽게 떨어져 나가기 때문이다.Here, the peeling phenomenon of the metal pad is caused by the difference in physical properties between the first metal film, the interlayer insulating film, and the second metal film, for example, due to the small adhesion between the second metal film and the SOG film. This is because the second metal film is easily separated from the metal pad structure by the damage applied from the lead at the time of wire bonding.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위하여 안출된 것으로서, 제2금속막의 접착력을 향상시키는 것에 의해 금속 패드의 벗겨짐 현상을 효과적으로 방지할 수 있는 반도체 소자의 금속 패드 형성방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a metal pad of a semiconductor device which can be effectively prevented from peeling of the metal pad by improving the adhesive force of the second metal film as to solve the above problems. There is this.
도 1은 종래의 금속 패드를 도시한 단면도.1 is a cross-sectional view showing a conventional metal pad.
도 2a 내지 도 2d는 본 발명의 실시예에 따른 금속 패드 형성방법을 설명하기 위한 각 공정 단면도.2A to 2D are cross-sectional views of respective processes for explaining a method for forming a metal pad according to an embodiment of the present invention.
도 3은 도 2a에 대응하는 평면도.3 is a plan view corresponding to FIG. 2A;
도 4는 본 발명의 금속 패드와 리드가 본딩된 상태를 보여주는 단면도.4 is a cross-sectional view showing a state in which a metal pad and a lead of the present invention are bonded.
도 5는 본 발명의 다른 실시예에 따른 금속 패드 형성방법을 설명하기 위한 단면도.Figure 5 is a cross-sectional view for explaining a metal pad forming method according to another embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
11 : 반도체 기판 12 : 제1금속막11 semiconductor substrate 12 first metal film
13 : 층간절연막 14 : 비아홀13: interlayer insulating film 14: via hole
15 : 금속 플러그 16 : 제2금속막15 metal plug 16 second metal film
20,20a : 금속 패드 30 : 리드20,20a: metal pad 30: lead
상기와 같은 목적을 달성하기 위한 본 발명의 금속 패드 형성방법은, 반도체 기판 상에 패드 형상으로 금속막을 형성하는 단계; 상기 금속막 상에 소정 두께로 층간절연막을 증착하는 단계; 상기 층간절연막의 소정 부분을 선택적으로 식각해서, 상기 층간절연막에 수 개의 비아홀을 형성하는 단계; 상기 비아홀 내에 금속막을 매립시켜, 금속 플러그를 형성하는 단계; 및 상기 금속 플러그의 소정 높이가 돌출되도록, 상기 층간절연막의 표면을 소정 두께만큼 식각하는 단계를 포함한다.Metal pad forming method of the present invention for achieving the above object comprises the steps of forming a metal film in the shape of a pad on a semiconductor substrate; Depositing an interlayer insulating film with a predetermined thickness on the metal film; Selectively etching a predetermined portion of the interlayer insulating film to form several via holes in the interlayer insulating film; Embedding a metal film in the via hole to form a metal plug; And etching the surface of the interlayer insulating layer by a predetermined thickness so that a predetermined height of the metal plug protrudes.
또한, 본 발명은 상기 층간절연막의 표면을 식각하는 단계 후, 돌출된 금속 플러그와 층간절연막 상에 패드 형상으로 금속막을 증착하는 단계를 더 포함한다.The present invention may further include depositing a metal film in a pad shape on the protruding metal plug and the interlayer insulating film after etching the surface of the interlayer insulating film.
본 발명에 따르면, 금속 기둥을 이용해서 제2금속막의 접착력을 향상시키기 때문에, 리드(lead) 본딩시, 금속 패드, 특히, 상기 제2금속막의 벗겨짐 현상을 효과적으로 방지할 수 있다.According to the present invention, since the adhesive force of the second metal film is improved by using the metal pillar, the peeling phenomenon of the metal pad, in particular, the second metal film can be effectively prevented during lead bonding.
(실시예)(Example)
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 소자의 금속 패드 형성방법을 설명하기 위한 각 공정별 단면도로서, 이를 설명하면 다음과 같다.2A to 2D are cross-sectional views of respective processes for explaining a method of forming a metal pad of a semiconductor device according to an embodiment of the present invention.
먼저, 도 2a에 도시된 바와 같이, 소정의 하부 패턴들(도시안됨)이 구비된 반도체 기판(11) 상에 패드 구조의 일부로서 제1금속막(12)을 형성한다. 여기서, 상기 반도체 기판(11)은 실제의 기판이 아닌, 기판 상에 형성된 절연막, 예컨데, PE-TEOS막으로 이해함이 바람직하다. 또한, 상기 제1금속막(12)은 바람직하게 박스 형상을 갖도록 형성한다.First, as shown in FIG. 2A, the first metal film 12 is formed as a part of the pad structure on the semiconductor substrate 11 provided with predetermined lower patterns (not shown). Here, it is preferable that the semiconductor substrate 11 is not an actual substrate but an insulating film formed on the substrate, for example, a PE-TEOS film. In addition, the first metal film 12 is preferably formed to have a box shape.
그 다음, 상기 제1금속막(12) 상에 층간절연막(13)을 증착하고, 상기 층간절연막(13)의 소정 부분들을 선택적으로 식각해서, 상기 층간절연막(13)에 상기 제1금속막(12)을 노출시키는 수 개의 비아홀(14)을 형성한다.Thereafter, an interlayer insulating film 13 is deposited on the first metal film 12, and predetermined portions of the interlayer insulating film 13 are selectively etched to form the first metal film on the interlayer insulating film 13. Several via holes 14 exposing 12 are formed.
도 3은 상기 도 2a에 대응하는 평면도로서, 도시된 바와 같이, 상기 층간절연막(13)에 수 개의 비아홀(14)이 형성되며, 이러한 비아홀(14)에 의해 상기 제1금속막(12)의 소정 부분들이 노출된다.FIG. 3 is a plan view corresponding to FIG. 2A, and as illustrated, several via holes 14 are formed in the interlayer insulating layer 13, and the via holes 14 may be used to form the first metal layer 12. Certain portions are exposed.
다음으로, 도 2b에 도시된 바와 같이, 상기 비아홀들(14)이 완전 매립되도록, 상기 층간절연막(13) 상에 소정의 금속막을 증착하고, 상기 층간절연막이 노출되도록, 상기 금속막을 에치백 또는 연마해서, 상기 비아홀들(14) 내에 각각 금속 플러그(15)를 형성한다.Next, as shown in FIG. 2B, a predetermined metal film is deposited on the interlayer insulating film 13 so that the via holes 14 are completely filled, and the metal film is etched back or exposed so that the interlayer insulating film is exposed. By grinding, metal plugs 15 are formed in the via holes 14, respectively.
그 다음, 도 2c에 도시된 바와 같이, 층간절연막(13)의 표면을 소정 두께만큼, 예컨데, 금속 플러그(15)의 전체 높이에 대해 1/3∼1/4에 해당하는 만큼의 두께를 식각하여, 상기 금속 플러그(15)의 소정 높이 만큼을 돌출시킨다.Next, as shown in FIG. 2C, the surface of the interlayer insulating film 13 is etched by a predetermined thickness, for example, 1/3 to 1/4 of the total height of the metal plug 15. Thus, the predetermined height of the metal plug 15 is projected.
그리고나서, 도 2d에 도시된 바와 같이, 상기 돌출된 금속 플러그(15) 및 층간절연막 상에 패드 형상으로 제2금속막(16)을 증착함으로써, 본 발명에 따른 금속 패드(20)를 완성한다.Then, as shown in FIG. 2D, the metal pad 20 according to the present invention is completed by depositing the second metal film 16 in the shape of a pad on the protruding metal plug 15 and the interlayer insulating film. .
상기와 같은 구조를 갖는 본 발명의 금속 패드(20)에 있어서, 제2금속막(16)이 금속 플러그(15)를 덮도록 증착되는 것에 기인해서, 상기 제2금속막(16)의 접착 면적은 확대되며, 이에 따라, 상기 제2금속막(16)의 접착력은 향상된다.In the metal pad 20 of the present invention having the above structure, the adhesion area of the second metal film 16 is due to the deposition of the second metal film 16 to cover the metal plug 15. Is enlarged, whereby the adhesive force of the second metal film 16 is improved.
따라서, 도 4에 도시된 바와 같이, 리드(lead : 30)의 본딩시, 상기 제2금속막(16)의 접착력이 향상된 것으로 인해, 금속 패드(20), 즉, 상기 제2금속막(16)의 벗겨짐 현상은 억제되며, 그래서, 본 발명의 금속 패드(20)는 벗겨짐 현상을 방지하는데 매우 효과적이다.Therefore, as shown in FIG. 4, when bonding the lead 30, the adhesive force of the second metal layer 16 is improved, so that the metal pad 20, that is, the second metal layer 16 is improved. The peeling phenomenon of) is suppressed, so that the metal pad 20 of the present invention is very effective in preventing the peeling phenomenon.
한편, 본 발명의 다른 실시예로서, 도 5에 도시된 바와 같이, 제2금속막의 증착 공정을 생략할 수 있다. 이 경우, 리드(30)는 제2금속막이 아닌, 기둥 형상을 갖으면서 돌출되어진 금속 플러그(15)와 층간절연막(13) 상에 본딩된다. 이와 같은 구조에 있어서, 상기 리드(30)는 금속 플러그(15)와의 접착 면적이 증대되기 때문에, 그 접착력이 향상된다.Meanwhile, as another embodiment of the present invention, as illustrated in FIG. 5, the deposition process of the second metal film may be omitted. In this case, the lead 30 is bonded on the interlayer insulating film 13 and the metal plug 15 protruding while having a columnar shape, not the second metal film. In this structure, since the adhesion area with the lead 30 is increased, the adhesion force is improved.
따라서, 금속 패드(20a)의 벗겨짐 현상은 전술한 실시예에서와 마찬가지로 효과적으로 방지되며, 아울러, 리드의 떨어짐 현상도 방지된다.Therefore, the peeling phenomenon of the metal pad 20a is effectively prevented as in the above-described embodiment, and the fall of the lead is also prevented.
이상에서와 같이, 본 발명은 층간절연막 내에 금속 플러그를 형성함과 동시에, 상기 금속 플러그의 표면이 소정 높이만큼 돌출되도록 함으로써, 이러한 금속 플러그 상에 증착되는 금속막의 접착 면적의 확대를 통해 접착력을 향상시킬 수 있으며, 그래서, 후속의 패키징 공정에서 금속 패드, 즉, 금속막의 벗겨짐 현상을 효과적으로 억제시킬 수 있고, 결과적으로는, 소자 자체의 신뢰성은 물론, 패키지의 신뢰성도 확보할 수 있다.As described above, the present invention forms a metal plug in the interlayer insulating film, and at the same time, the surface of the metal plug protrudes by a predetermined height, thereby improving the adhesive force through the expansion of the adhesion area of the metal film deposited on the metal plug Therefore, the peeling phenomenon of the metal pad, that is, the metal film, can be effectively suppressed in the subsequent packaging step, and as a result, the reliability of the device itself as well as the reliability of the package can be secured.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2000-0081926A KR100372649B1 (en) | 2000-12-26 | 2000-12-26 | Method for forming metal pad of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR10-2000-0081926A KR100372649B1 (en) | 2000-12-26 | 2000-12-26 | Method for forming metal pad of semiconductor device |
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| KR20020053947A true KR20020053947A (en) | 2002-07-06 |
| KR100372649B1 KR100372649B1 (en) | 2003-02-15 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100605194B1 (en) * | 2004-12-29 | 2006-07-31 | 동부일렉트로닉스 주식회사 | Method for forming the pad layer of semiconductor device |
| KR100763709B1 (en) * | 2005-12-28 | 2007-10-04 | 동부일렉트로닉스 주식회사 | Method for forming pad of semiconductor device |
| KR100933685B1 (en) * | 2007-12-18 | 2009-12-23 | 주식회사 하이닉스반도체 | Bonding pad to prevent peeling and forming method thereof |
| US8610277B2 (en) | 2007-07-31 | 2013-12-17 | Samsung Electronics Co., Ltd. | Bridge type pad structure of a semiconductor device |
-
2000
- 2000-12-26 KR KR10-2000-0081926A patent/KR100372649B1/en not_active IP Right Cessation
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100605194B1 (en) * | 2004-12-29 | 2006-07-31 | 동부일렉트로닉스 주식회사 | Method for forming the pad layer of semiconductor device |
| KR100763709B1 (en) * | 2005-12-28 | 2007-10-04 | 동부일렉트로닉스 주식회사 | Method for forming pad of semiconductor device |
| US8610277B2 (en) | 2007-07-31 | 2013-12-17 | Samsung Electronics Co., Ltd. | Bridge type pad structure of a semiconductor device |
| KR100933685B1 (en) * | 2007-12-18 | 2009-12-23 | 주식회사 하이닉스반도체 | Bonding pad to prevent peeling and forming method thereof |
| US8119515B2 (en) | 2007-12-18 | 2012-02-21 | Hynix Semiconductor Inc. | Bonding pad for anti-peeling property and method for fabricating the same |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100372649B1 (en) | 2003-02-15 |
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