KR20020052582A - Semiconductor package - Google Patents
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- KR20020052582A KR20020052582A KR1020000081976A KR20000081976A KR20020052582A KR 20020052582 A KR20020052582 A KR 20020052582A KR 1020000081976 A KR1020000081976 A KR 1020000081976A KR 20000081976 A KR20000081976 A KR 20000081976A KR 20020052582 A KR20020052582 A KR 20020052582A
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- semiconductor package
- die
- die paddle
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
본 발명은 반도체패키지에 관한 것으로, 더욱 상세하게 설명하면 다이패들의 하면이 봉지부 외측으로 노출된 반도체패키지에 관한 것이다.The present invention relates to a semiconductor package, and more particularly, to a semiconductor package in which a lower surface of the die pack is exposed to the outside of the encapsulation unit.
최근 열방출 성능을 향상시키기 위해, 다이패들을 봉지부 외측으로 노출시킨 반도체패키지가 출시되어 있으며, 이러한 반도체패키지(100')가 도1에 도시되어 있다.Recently, in order to improve heat dissipation performance, a semiconductor package is disclosed in which the die pads are exposed to the outside of the encapsulation unit, and such a semiconductor package 100 'is shown in FIG.
도시된 바와 같이 대략 판상의 다이패들(2')이 위치되어 있고, 상기 다이패들(2')의 상부에는 에폭시 접착제(4') 등이 개재되어 다수의 입출력패드(6a')가 형성된 반도체칩(6')이 접착 및 고정되어 있다. 또한, 상기 다이패들(2')의 상부로서 상기 반도체칩(6')의 외주연에는 다수의 리드(8')가 배열되어 있으며, 상기 리드(8')는 반도체칩(6')의 입출력패드(6a')와 도전성와이어(10')에 의해 상호 연결되어 있다. 더불어, 상기 다이패들(2')의 하면을 제외한 상면, 반도체칩(6'), 도전성와이어(10') 및 리드(8')의 일정영역은 에폭시몰딩컴파운드(Epoxy Molding Compound)와 같은 봉지재로 봉지됨으로써, 일정 형태의 봉지부(12')가 형성되어 있다.As shown, a substantially plate-shaped die paddle 2 'is positioned, and a plurality of input / output pads 6a' is formed by interposing an epoxy adhesive 4 'on top of the die paddle 2'. The semiconductor chip 6 'is bonded and fixed. In addition, a plurality of leads 8 'are arranged on the outer circumference of the semiconductor chip 6' as the upper portion of the die paddle 2 ', and the leads 8' are formed of the semiconductor chip 6 '. The input / output pads 6a 'and the conductive wires 10' are connected to each other. In addition, certain areas of the upper surface except for the lower surface of the die paddle 2 ', the semiconductor chip 6', the conductive wire 10 'and the lead 8' are encapsulated such as an epoxy molding compound. By sealing with ash, the sealing part 12 'of a certain form is formed.
그러나, 이러한 종래의 반도체패키지는 다이패들과 봉지부 사이(도1에서 부호 "A"로 표시됨)의 결합력이 비교적 약함으로써, 외부 충격에 의해 쉽게 상기 다이패들과 봉지부 사이의 간격이 벌어지는 단점이 있다.However, such a conventional semiconductor package has a relatively weak coupling force between the die paddle and the encapsulation portion (indicated by symbol “A” in FIG. 1), so that the gap between the die paddle and the encapsulation portion is easily opened by external impact. There are disadvantages.
또한, 상기와 같은 이유 외에도 상기 다이패들의 측단이 비교적 평탄하게 형성됨으로써, 봉지부와의 계면을 통해 수분이 쉽게 침투되고, 또 이 수분은 반도체칩의 계면까지 흘러, 결국에는 고온의 환경에서 반도체패키지가 크랙되거나 또는팝콘 현상에 의해 계면박리가 심하게 발생하는 문제가 있다.In addition, the side ends of the die pads are formed relatively flat in addition to the above reasons, so that moisture easily penetrates through the interface with the encapsulation portion, and the moisture flows to the interface of the semiconductor chip. There is a problem in that the interface is severely generated due to cracking of the package or popcorn phenomenon.
따라서 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로, 다이패들의 표면적을 최대한 넓힘과 동시에 봉지부와의 결합력을 증대시켜, 다이패들과 봉지부 사이의 계면박리를 억제함은 물론, 수분의 침투를 최대한 억제할 수 있는 반도체패키지를 제공하는데 있다.Therefore, the present invention has been made to solve the above-mentioned conventional problems, and to increase the surface area of the die pad as much as possible and at the same time to increase the bonding force with the encapsulation portion, to suppress the interfacial separation between the die paddle and the encapsulation portion is Of course, to provide a semiconductor package that can suppress the penetration of moisture as much as possible.
도1a는 종래의 반도체패키지를 도시한 단면도이고, 도1b는 봉지부가 제거된 상태의 저면도이다.1A is a cross-sectional view showing a conventional semiconductor package, and FIG. 1B is a bottom view of a state in which an encapsulation portion is removed.
도2a는 본 발명에 의한 반도체패키지를 도시한 단면도이고, 도2b는 도2a에서 봉지부가 제거된 상태의 다이패들 저면도이다.Figure 2a is a cross-sectional view showing a semiconductor package according to the present invention, Figure 2b is a bottom view of the die paddle with the sealing portion removed in Figure 2a.
도3a는 본 발명에 의한 다른 반도체패키지를 도시한 단면도이고, 도3b는 도3a에서 봉지부가 제거된 상태의 다이패들 저면도이다.3A is a cross-sectional view showing another semiconductor package according to the present invention, and FIG. 3B is a bottom view of the die paddle with the encapsulation portion removed in FIG. 3A.
- 도면중 주요 부호에 대한 설명 --Description of the main symbols in the drawings-
101,102; 본 발명에 의한 반도체패키지101,102; Semiconductor package according to the present invention
2; 다이패들2a; 돌출라인2; Die paddle 2a; Extrusion Line
2b; 요홈라인2c; 요홈2b; Groove line 2c; Groove
4; 접착제6; 반도체칩4; Adhesive 6; Semiconductor chip
6a; 입출력패드8; 리드6a; Input / output pad 8; lead
10; 도전성와이어12; 봉지부10; Conductive wires 12; Encapsulation
상기한 목적을 달성하기 위해 본 발명은 대략 판상의 다이패들과, 상기 다이패들에 접착제가 개재되어 접착된 동시에 상면에 다수의 입출력패드가 형성된 반도체칩과, 상기 다이패들 및 반도체칩의 외주연에 위치된 다수의 리드와, 상기 반도체칩의 입출력패드와 상기 리드를 상호 전기적으로 연결하는 다수의 도전성와이어와, 상기 다이패들은 외부로 노출되도록 하고, 상기 반도체칩, 도전성와이어 및 리드는 봉지재로 봉지되어 형성된 봉지부로 이루어진 반도체패키지에 있어서,In order to achieve the above object, the present invention provides a semiconductor chip including a plate-shaped die paddle, a plurality of input / output pads formed on an upper surface of the die paddle and an adhesive interposed therebetween, and the die paddle and the semiconductor chip. A plurality of leads located at an outer circumference, a plurality of conductive wires electrically connecting the input / output pads of the semiconductor chip and the leads, and the die pads to be exposed to the outside, and the semiconductor chip, the conductive wires and the leads In the semiconductor package consisting of an encapsulation portion formed by encapsulation with an encapsulant,
상기 다이패들은 상기 봉지부와 접하는 하측면의 내주연을 따라 소정두께로 돌출된 돌출라인이 형성되고, 상기 돌출라인의 내주연을 따라서 일정깊이 함몰된 요홈라인이 형성된 동시에, 상기 돌출라인 및 요홈라인은 봉지부와 결합된 것을 특징으로 한다.The die pad is formed with a protruding line protruding to a predetermined thickness along an inner circumference of the lower side in contact with the encapsulation portion, and a concave recess line having a predetermined depth along the inner circumference of the protruding line is formed. The line is characterized in that combined with the encapsulation.
여기서, 상기 다이패들의 상면으로부터 상기 돌출라인 및 요홈라인의 두께는 다이패들의 두께보다 작고, 상기 돌출라인의 두께는 상기 요홈라인의 두께보다 크게 되도록 함이 바람직하다.Here, the thickness of the protrusion line and the recess line from the upper surface of the die pad is preferably smaller than the thickness of the die pad, the thickness of the protrusion line is preferably larger than the thickness of the groove line.
상기 돌출라인 및 요홈라인은 단면상 소정 반경을 갖도록 라운드 처리된 것이 바람직하다.The protrusion line and the groove line are preferably rounded to have a predetermined radius in cross section.
상기 다이패들의 하측면 내주연을 따라서는, 상기 돌출라인과 요홈라인에 걸치어 대략 원형의 요홈이 복수개로 더 형성될 수 있다.Along the inner circumference of the lower side of the die paddle, a plurality of roughly circular grooves may be further formed over the protrusion line and the groove line.
상기와 같이 하여 본 발명에 의한 반도체패키지에 의하면, 다이패들의 하측면 내주연에 돌출라인 및 요홈라인을 더 형성함으로써 봉지부와의 결합 면적이 증대됨은 물론, 인터락킹(Interlocking)에 의한 결합력이 증대되는 장점이 있다.According to the semiconductor package according to the present invention as described above, by further forming a protruding line and groove line on the inner peripheral edge of the die face, the bonding area with the encapsulation is increased, as well as the coupling force due to interlocking (interlocking) There is a growing advantage.
따라서, 외부의 기계적 충격에 의해 봉지부와 다이패들의 계면 간격이 벌어지기 어려우며, 더불어 수분의 침투가 어렵고 그 수분 침투 길이가 길어짐으로써, 계면박리 현상이나, 반도체패키지의 크랙 내지 팝콘 현상을 억제할 수 있게 된다.Therefore, the interface gap between the encapsulation portion and the die pad is difficult to open due to external mechanical impact, and it is difficult to penetrate moisture and the water penetration length becomes long, thereby suppressing the interface peeling phenomenon and the crack or popcorn phenomenon of the semiconductor package. It becomes possible.
이하 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art can easily implement the present invention.
도2a는 본 발명에 의한 반도체패키지(101)를 도시한 단면도이고, 도2b는 도2a에서 봉지부(12)가 제거된 상태의 다이패들(2)에 대한 저면도이다.FIG. 2A is a cross-sectional view of the semiconductor package 101 according to the present invention, and FIG. 2B is a bottom view of the die paddle 2 with the encapsulation portion 12 removed in FIG. 2A.
도시된 바와 같이 대략 판상의 다이패들(2)이 구비되어 있고, 상기 다이패들(2)에는 접착제(4)가 개재되어 접착된 동시에 상면에 다수의 입출력패드(6a)가 형성된 반도체칩(6)이 구비되어 있다. 상기 다이패들(2) 및 반도체칩(6)의 외주연에는 다수의 리드(8)가 위치되어 있고, 상기 반도체칩(6)의 입출력패드(6a)와 상기 리드(8)는 도전성와이어(10)에 의해 상호 접속되어 있다. 상기다이패들(2)은 외부로 노출되도록 하고, 상기 반도체칩(6), 도전성와이어(10) 및 리드(8)는 봉지재로 봉지되어 일정 형상의 봉지부(12)가 형성되어 있다. 이러한 구조는 종래와 동일하다.As shown, a substantially chip-shaped die paddle 2 is provided, and the die paddle 2 is bonded to the die paddle 2 with an adhesive 4 interposed therebetween, and a plurality of input / output pads 6a formed on an upper surface thereof. 6) is provided. A plurality of leads 8 are positioned at the outer circumference of the die paddle 2 and the semiconductor chip 6, and the input / output pad 6a and the lead 8 of the semiconductor chip 6 are conductive wires ( 10) are interconnected. The die paddle 2 is exposed to the outside, and the semiconductor chip 6, the conductive wire 10, and the lead 8 are encapsulated with an encapsulant to form an encapsulation portion 12 having a predetermined shape. This structure is the same as before.
본 발명은 상기 다이패들(2)에 있어서, 상기 봉지부(12)와 접하는 하측면의 내주연을 따라 소정 두께로 돌출된 돌출라인(2a)이 형성되어 있고, 상기 돌출라인(2a)의 내주연을 따라서는 일정깊이로 함몰된 요홈라인(2b)이 더 형성되어 있다.In the die paddle (2), a protruding line (2a) protruding to a predetermined thickness is formed along the inner circumference of the lower side in contact with the encapsulation portion (12), the protrusion of the protruding line (2a) Along the inner circumference, the recessed recess line 2b is further formed.
또한, 상기 돌출라인(2a) 및 요홈라인(2b)은 봉지부(12)와 결합되어 있음으로, 인터락킹 효과를 유발시켜, 상기 돌출라인(2a) 및 요홈라인(2b)과 봉지부(12)와의 결합력은 더욱 향상된다.In addition, the protruding line 2a and the concave line 2b are coupled to the encapsulation part 12, thereby causing an interlocking effect, such that the protruding line 2a and the concave line 2b and the encapsulation part 12 are provided. ) Bond strength is further improved.
한편, 상기 다이패들(2)의 상면으로부터 상기 돌출라인(2a) 및 요홈라인(2b)의 두께는 다이패들(2)의 두께(A)보다 작게 되어 있고, 상기 돌출라인(2a)의 두께(B)는 상기 요홈라인(2b)의 두께(C)보다 크게 되어 있다.Meanwhile, the thickness of the protrusion line 2a and the recess line 2b from the upper surface of the die paddle 2 is smaller than the thickness A of the die paddle 2, and the thickness of the protrusion line 2a is increased. The thickness B is larger than the thickness C of the groove line 2b.
또한, 상기 돌출라인(2a) 및 요홈라인(2b)은 단면상 소정 반경을 갖도록 라운드 처리 또는 곡선 처리되어 있으며, 이와 같은 라운드 또는 곡선 형태는 상기 돌출라인(2a) 및 요홈라인(2b)이 화학적 에칭에 의해 형성되기 때문이다.In addition, the protruding line 2a and the concave line 2b are rounded or curved so as to have a predetermined radius in cross section. Such round or curved shape is chemically etched by the protruding line 2a and the concave line 2b. Because it is formed by.
도3a는 본 발명에 의한 다른 반도체패키지(101)를 도시한 단면도이고, 도3b는 도3a에서 봉지부(12)가 제거된 상태의 다이패들(2)에 대한 저면도이다. 이는 상기 도2a 및 도2b에 도시된 것과 거의 유사하므로 그 차이점만을 설명하기로 한다.3A is a cross-sectional view showing another semiconductor package 101 according to the present invention, and FIG. 3B is a bottom view of the die paddle 2 with the encapsulation portion 12 removed in FIG. 3A. This is almost similar to that shown in Figs. 2A and 2B, so only the differences will be described.
도시된 바와 같이 상기 다이패들(2)의 하측면 내주연을 따라서는돌출라인(2a) 및 요홈라인(2b)이 형성된 동시에, 상기 돌출라인(2a) 및 요홈라인(2b)에 걸치어서는 대략 원형의 요홈(2c)이 복수개로 형성되어 있다. 상기 요홈(2c)은 원형외에도 타원형, 사각형, 삼각형 등 다양한 형상으로 형성 가능하다.As shown, the protrusion line 2a and the recess line 2b are formed along the inner circumference of the lower side of the die paddle 2, and the protrusion line 2a and the recess line 2b A plurality of substantially circular grooves 2c are formed. The grooves 2c may be formed in various shapes, such as oval, square, and triangle, in addition to circular.
상기와 같이 요홈(2c)을 형성하게 되면, 상기 요홈(2c)의 면적만큼, 봉지부(12)와의 접착 면적이 커지고, 또한 인터락킹 및 결합력도 향상된다.When the grooves 2c are formed as described above, the adhesion area with the encapsulation portion 12 is increased by the area of the grooves 2c, and the interlocking and coupling force is also improved.
이상에서와 같이 본 발명은 비록 상기의 실시예에 한하여 설명하였지만 여기에만 한정되지 않으며, 본 발명의 범주 및 사상을 벗어나지 않는 범위내에서 여러가지로 변형된 실시예도 가능할 것이다.As described above, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto, and various modified embodiments may be possible without departing from the scope and spirit of the present invention.
따라서, 본 발명에 의한 반도체패키지에 의하면, 다이패들의 하측면 내주연에 돌출라인 및 요홈라인을 더 형성함으로써 봉지부와의 접착 면적이 증대됨은 물론, 인터락킹(Interlocking)에 의한 결합력도 증대되는 효과가 있다.Therefore, according to the semiconductor package according to the present invention, by further forming a protruding line and a groove line on the inner circumferential side of the die face, the adhesive area with the encapsulation portion is increased, and the bonding force due to interlocking is also increased. It works.
또한, 외부의 기계적 충격에 의해 봉지부와 다이패들의 계면 간격이 벌어지기 어려우며, 더불어 수분의 침투가 어렵고 그 수분 침투 길이가 길어짐으로써, 계면박리 현상이나, 반도체패키지의 크랙 내지 팝콘 현상을 억제할 수 있는 효과가 있다.In addition, the interface gap between the encapsulation portion and the die pad is difficult to open due to external mechanical impact, and the penetration of moisture is difficult and the length of the moisture penetration is increased, thereby preventing interfacial peeling or cracking or popcorn of the semiconductor package. It can be effective.
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