KR20020052462A - Manufacturing method for semiconductor device - Google Patents
Manufacturing method for semiconductor device Download PDFInfo
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- KR20020052462A KR20020052462A KR1020000081751A KR20000081751A KR20020052462A KR 20020052462 A KR20020052462 A KR 20020052462A KR 1020000081751 A KR1020000081751 A KR 1020000081751A KR 20000081751 A KR20000081751 A KR 20000081751A KR 20020052462 A KR20020052462 A KR 20020052462A
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- insulating film
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- polysilicon layer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 49
- 229920005591 polysilicon Polymers 0.000 claims abstract description 42
- 238000000034 method Methods 0.000 claims abstract description 28
- 239000002184 metal Substances 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000002955 isolation Methods 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims description 10
- 239000012535 impurity Substances 0.000 claims description 10
- 238000005468 ion implantation Methods 0.000 claims description 7
- 230000004888 barrier function Effects 0.000 claims description 2
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 238000005498 polishing Methods 0.000 claims 1
- 230000009977 dual effect Effects 0.000 abstract description 10
- 239000012212 insulator Substances 0.000 abstract 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 abstract 1
- 238000006731 degradation reaction Methods 0.000 abstract 1
- 238000002513 implantation Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 62
- 238000000151 deposition Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 보다 상세하게 로직 및DRAM의 듀얼 게이트(dual gate)의 제조공정에서 다마신 구조와 카운터 도핑(counter doping)을 이용하여 듀얼 게이트전극을 형성함으로써 도핑농도에 따른 식각속도의 차이에 의해 식각프로파일이 차이가 나는 것을 방지하고, 그에 따른 소자의 동작 특성 및 신뢰성을 향상시키는 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a doping concentration by forming a dual gate electrode using a damascene structure and counter doping in a manufacturing process of a dual gate of logic and DRAM. The present invention relates to a method of manufacturing a semiconductor device, which prevents a difference in etching profile due to a difference in etching speeds and improves operating characteristics and reliability of the device.
종래의 듀얼 게이트 전극을 제조하는 방법은 언도프(undoped)된 폴리실리콘층 상부에 마스크(Mask)를 사용하여 듀얼 임플란트(implant)하거나, 인-시튜 도핑(in-situ doping)방법에 의하여 n+ 게이트와 p+ 게이트를 각각 증착하고, 패터닝(patterning)하는 방법이 주로 사용되었다.The conventional method of manufacturing a dual gate electrode is a dual implant (implant) using a mask on the undoped polysilicon layer, or n + gate by an in-situ doping method The method of depositing and patterning the and p + gates respectively was mainly used.
그러나, 전자의 방법은 공정이 간편한 편이나 하이 도핑(high doping)이 어렵고, 도판트 프로파일(dopant profile) 특성 상 게이트 공핍(depletion)이 일어나기 쉽다.However, the former method is easy to process, but high doping is difficult, and gate depletion is likely to occur due to the dopant profile.
또한, 후자의 방법은 n+/p+ 다결정실리콘 게이트를 증착해야 하므로 각각의 공정을 셋-업 해야 되는 문제점이 있으며, 또한 각각의 게이트를 증착한 다음, 디파인하고 패터닝해야 되는 복잡성이 있다.In addition, the latter method requires the deposition of n + / p + polysilicon gates, so that each process has to be set up, and there is also a complexity of defining and patterning each gate after deposition.
이하, 첨부된 도면을 참고로 하여 종래 기술에 따른 반도체소자의 제조방법을 설명하기로 한다.Hereinafter, a method of manufacturing a semiconductor device according to the prior art will be described with reference to the accompanying drawings.
도 1a 내지 도 1c 는 종래기술에 따른 반도체소자의 제조방법에 의한 공정 단면도이다.1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
먼저, PMOS영역(Ⅰ)과 NMOS영역(Ⅱ)이 구비되는 반도체기판(11)에 활성영역을 정의하는 소자분리절연막(12)을 형성한다. (도 1a 참조)First, a device isolation insulating film 12 defining an active region is formed in a semiconductor substrate 11 having a PMOS region I and an NMOS region II. (See Figure 1A)
다음, PMOS영역(Ⅰ)과 NMOS영역(Ⅱ)에 n웰(13)과 p웰(14)을 각각 형성한다.Next, n wells 13 and p wells 14 are formed in the PMOS region I and the NMOS region II, respectively.
그 다음, 전체표면 상부에 게이트절연막(15)과 언도프트 다결정실리콘층(16)을 순차적으로 형성한다.Next, the gate insulating film 15 and the undoped polysilicon layer 16 are sequentially formed over the entire surface.
다음, 도시되어 있지는 않지만 PMOS영역(Ⅰ)과 NMOS영역(Ⅱ)을 노출시키는 이온주입마스크를 각각 사용하여 p형 불순물인 붕소(B)와 n형 불순물인 인(P)을 이온주입함으로써 p+ 다결정실리콘층과 n+ 다결정실리콘층을 형성한다. (도 1b 참조)Next, although not shown, p + polycrystals are ion-implanted with boron (P) and p (phosphorus) as n-type impurities using ion implantation masks exposing the PMOS region (I) and NMOS region (II), respectively. A silicon layer and an n + polysilicon layer are formed. (See FIG. 1B)
그 다음, 전체표면 상부에 게이트전극으로 사용되는 금속층과 마스크절연막을 순차적으로 형성한다. 상기 금속층은 W막이 사용된다.Next, a metal layer and a mask insulating film used as gate electrodes are sequentially formed over the entire surface. As the metal layer, a W film is used.
다음, 게이트전극을 정의하는 게이트전극 마스크를 식각마스크로 상기 마스크절연막, 금속층, n+ 다결정실리콘층, p+다결정실리콘층 및 게이트절연막(15)을 식각하여 마스크절연막패턴(20) PMOS영역(Ⅰ)에는 p+다결정실리콘층패턴(18)과 금속층패턴(19)으로 되는 게이트전극과 NMOS영역(Ⅱ)에는 n+ 다결정실리콘층패턴(17)과 금속층패턴(19)으로 되는 듀얼 게이트전극을 형성한다. (도 1c 참조)Next, the mask insulating layer, the metal layer, the n + polysilicon layer, the p + polysilicon layer, and the gate insulating layer 15 are etched using the gate electrode mask defining the gate electrode in the mask insulating layer pattern 20 in the PMOS region (I). A gate electrode serving as the p + polysilicon layer pattern 18 and the metal layer pattern 19 and a dual gate electrode serving as the n + polysilicon layer pattern 17 and the metal layer pattern 19 are formed in the NMOS region II. (See Figure 1C)
상기와 같이 종래기술에 따른 반도체소자의 제조방법은, NMOS영역 및 PMOS영역에 게이트전극용 도전층은 각각 서로 다른 종류의 불순물이 이온주입되어 있기 때문에 게이트전극을 정의하는 식각공정에서 식각속도 차이에 의해 반도체기판의 활성영역이 손상될 수 있고, PMOS영역의 언도프트 다결정실리콘층에 p+불순물을 이온주입하여 p+ 다결정실리콘층을 형성하는 경우, 상기 p+다결정실리콘층에서 게이트절연막으로 p+불순물이 침투하여 소자의 플랫밴드(flat band) 및 문턱전압을 변경시키는 등의 소자 특성을 열화시키는 문제점이 있다.As described above, in the method of manufacturing a semiconductor device according to the related art, since the different types of impurities are ion-implanted into the NMOS region and the PMOS region, the etching rate is different from the etching rate in the etching process of defining the gate electrode. As a result, the active region of the semiconductor substrate may be damaged, and when the p + polysilicon layer is formed by ion implantation of p + impurity into the undoped polysilicon layer of the PMOS region, the p + impurity penetrates into the gate insulating film from the p + polysilicon layer. There is a problem of deteriorating device characteristics such as changing a flat band and a threshold voltage of the device.
본 발명은 상기한 종래기술의 문제점들을 해결하기 위하여, PMOS영역 및 NMOS영역에 듀얼 게이트전극을 형성하는 공정에서 반도체기판 상부에 게이트전극으로 예정되는 부분을 노출시키는 홈이 구비되는 층간절연막을 형성하고, 전체표면 상부에 p+다결정실리콘층을 형성하여 PMOS영역에 PMOS소자를 형성한 다음, NMOS영역에 n+ 불순물의 카운터 도핑으로 n+다결정실리콘층을 형성하여 NMOS 소자를 형성함으로써 동작특성 및 신뢰성을 향상시키는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, in the process of forming a dual gate electrode in the PMOS region and the NMOS region, forming an interlayer insulating film having a groove for exposing a predetermined portion as a gate electrode on the semiconductor substrate; To form a PMOS device in the PMOS region by forming a p + polysilicon layer on the entire surface, and then to form an NMOS device by forming an n + polycrystalline silicon layer by counter doping of n + impurities in the NMOS region. Its purpose is to provide a method for manufacturing a semiconductor device.
도 1a 내지 도 1c 는 종래기술에 따른 반도체소자의 제조방법에 의한 공정 단면도.1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
도 2a 내지 도 2f 는 본 발명에 따른 반도체소자의 제조방법에 의한 공정 단면도.2A to 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
11, 21 : 반도체기판 12, 23 : 소자분리절연막11, 21: semiconductor substrate 12, 23: device isolation insulating film
13, 25 : n웰 14, 27 : p웰13, 25: n well 14, 27: p well
15, 31 : 게이트절연막 16 : 언도프트 다결정실리콘층15, 31: gate insulating film 16: undoped polysilicon layer
17, 39 : n+다결정실리콘층패턴 18, 37 : p+다결정실리콘층패턴17, 39: n + polysilicon layer pattern 18, 37: p + polysilicon layer pattern
19, 41 : 금속층패턴 20, 43 : 마스크절연막패턴19, 41: metal layer pattern 20, 43: mask insulating film pattern
29 : 희생절연막 33 : p+다결정실리콘층29 sacrificial insulating film 33 p + polysilicon layer
35 : 감광막패턴 45 : 절연막 스페이서35 photosensitive film pattern 45 insulating film spacer
이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 제조방법은,Method for manufacturing a semiconductor device according to the present invention for achieving the above object,
PMOS영역 및 NMOS영역이 구비되는 반도체기판에 활성영역을 정의하는 소자분리절연막을 형성하는 공정과,Forming a device isolation insulating film defining an active region on a semiconductor substrate having a PMOS region and an NMOS region;
상기 PMOS영역과 NMOS영역에 n웰과 p웰을 형성하는 공정과,Forming n wells and p wells in the PMOS and NMOS regions;
전체표면 상부에 게이트전극으로 예정되는 부분을 노출시키는 홈이 구비되는 희생절연막을 형성하는 공정과,Forming a sacrificial insulating film having a groove exposing a portion intended as a gate electrode on an entire surface thereof;
상기 홈의 저부에 게이트절연막을 형성하는 공정과,Forming a gate insulating film at the bottom of the groove;
전체표면 상부에 p+ 다결정실리콘층을 소정 두께 형성하는 공정과,Forming a predetermined thickness of the p + polysilicon layer on the entire surface;
상기 p+ 다결정실리콘층 상부에 상기 NMOS영역을 노출시키는 절연막패턴을 형성하는 공정과,Forming an insulating film pattern exposing the NMOS region on the p + polysilicon layer;
상기 절연막패턴을 이온주입마스크로 상기 p+다결정실리콘층에 n+불순물을카운터 도핑하여 n+다결정실리콘층을 형성하는 공정과,Forming an n + polysilicon layer by doping n + impurities to the p + polysilicon layer using the insulating layer pattern as an ion implantation mask;
상기 절연막패턴을 제거하는 공정과,Removing the insulating film pattern;
전체표면 상부에 상기 홈이 매립되도록 금속층을 형성하는 공정과,Forming a metal layer such that the groove is buried in the entire upper surface;
상기 금속층과 p+다결정실리콘층 및 n+다결정실리콘층을 상기 희생절연막을 식각장벽으로 이용한 식각공정으로 제거하여 상기 홈을 매립하는 금속층패턴과 p+다결정실리콘층패턴의 적층구조와 금속층패턴과 n+다결정실리콘층패턴의 적층구조로 되는 게이트전극을 형성하는 공정과,The metal layer, the p + polysilicon layer, and the n + polysilicon layer were removed by an etching process using the sacrificial insulating layer as an etch barrier, and the stacked structure of the metal layer pattern and the p + polycrystalline silicon layer pattern, the metal layer pattern, and the n + polycrystalline silicon layer Forming a gate electrode having a pattern stack structure;
상기 희생절연막을 제거하는 공정을 포함하는 것을 특징으로 한다.And removing the sacrificial insulating film.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2f 는 본 발명에 따른 반도체소자의 제조방법에 의한 공정 단면도로서, 듀얼 게이트전극을 형성하는 방법에 관한 것이다.2A to 2F are cross-sectional views of a process of manufacturing a semiconductor device according to the present invention, and a method of forming a dual gate electrode.
먼저, PMOS영역(Ⅰ)과 NMOS영역(Ⅱ)이 구비되는 반도체기판(21)에 활성영역을 정의하는 소자분리절연막(23)을 형성한다. (도 2a 참조)First, a device isolation insulating film 23 defining an active region is formed in a semiconductor substrate 21 having a PMOS region I and an NMOS region II. (See Figure 2A)
다음, 상기 PMOS영역(Ⅰ) 및 NMOS영역(Ⅱ)에 각각 n웰(25) 및 p웰(27)을 형성한다.Next, n wells 25 and p wells 27 are formed in the PMOS region I and the NMOS region II, respectively.
그 다음, 전체표면 상부에 희생절연막(29)을 형성한다. 이때, 상기 희생절연막(29)은 다결정실리콘층과 식각선택비 차이를 갖는 BPSG막을 이용하여 형성한다. (도 2b 참조)Next, a sacrificial insulating film 29 is formed over the entire surface. In this case, the sacrificial insulating film 29 is formed using a BPSG film having a difference in etching selectivity from the polysilicon layer. (See Figure 2b)
다음, 상기 PMOS영역(Ⅰ) 및 NMOS영역(Ⅱ)에서 게이트전극으로 예정되는 부분을 노출시키는 게이트전극마스크를 식각마스크로 상기 희생절연막(29)을 식각하여 홈을 형성한다.Next, the sacrificial insulating layer 29 is etched using a gate electrode mask that exposes a portion of the PMOS region I and the NMOS region II that is intended as a gate electrode to form a groove.
그 다음, 상기 구조를 세정하여 불순물 및 자연산화막 등을 제거하고, 산화공정을 실시하여 상기 홈 저부에 게이트절연막(31)을 형성한다.Next, the structure is cleaned to remove impurities, a natural oxide film, and the like, and an oxidation process is performed to form a gate insulating film 31 at the bottom of the groove.
그 다음, 전체표면 상부에 p+다결정실리콘층(33)을 소정 두께 형성한다. (도 2c 참조)Then, the p + polysilicon layer 33 is formed on the entire surface by a predetermined thickness. (See Figure 2c)
다음, 전체표면 상부에 산화막을 형성한다.Next, an oxide film is formed over the entire surface.
그 다음, 상기 산화막 상붕에 상기 NMOS영역(Ⅱ)을 노출시키는 감광막패턴(도시 안됨)을 형성한다.Next, a photoresist pattern (not shown) for exposing the NMOS region (II) is formed on the oxide film roof.
다음, 상기 감광막패턴을 식각마스크로 상기 산화막을 식각하여 상기 NMOS영역(Ⅱ)을 노출시키는 산화막패턴(35)을 형성한다.Next, the oxide layer is etched using the photoresist pattern as an etch mask to form an oxide layer pattern 35 exposing the NMOS region II.
그 다음, 상기 감광막패턴을 제거한다. (도 2d 참조)Then, the photoresist pattern is removed. (See FIG. 2D)
다음, 상기 산화막패턴(35)을 이온주입 마스크로 사용하여 상기 노출된 NMOS영역(Ⅱ) 상의 p+다결정실리콘층(33)에 n+불순물을 카운터도핑시켜 n+다결정실리콘층으로 형성한다. 이때, 상기 카운터 도핑공정은 650 ∼ 850℃의 Ph3분위기에서 열처리하거나, Ph3이온을 이온주입하여 실시된다.Next, n + impurity is counter-doped to p + polysilicon layer 33 on the exposed NMOS region (II) using the oxide film pattern 35 as an ion implantation mask to form n + polycrystalline silicon layer. At this time, the counter doping step is carried out by heat treatment in 650 ~ 850 ℃ Ph 3 atmosphere, or by implanting Ph 3 ions.
그 다음, 상기 산화막패턴(35)을 제거한다.Next, the oxide film pattern 35 is removed.
다음, 전체표면 상부에 금속층을 형성한다. 이때, 상기 금속층은 W막으로 형성한다.Next, a metal layer is formed on the entire surface. In this case, the metal layer is formed of a W film.
그 다음, 상기 금속층, p+다결정실리콘층(33) 및 n+다결정실리콘층을 전면식각공정 또는 화학적 기계적 연마(chemical mechanical polishin, CMP)공정으로 제거하여 상기 PMOS영역(Ⅰ)에는 p+다결정실리콘층패턴(37)과 금속층패턴(41)의 적층구조, 상기 NMOS영역(Ⅱ)에는 n+다결정실리콘층패턴(39)과 금속층패턴(41)의 적층구조로 되는 게이트전극을 형성한다. (도 2e 참조)Then, the metal layer, the p + polysilicon layer 33 and the n + polysilicon layer are removed by a front etching process or a chemical mechanical polish (CMP) process, so that the p + polysilicon layer pattern (P) is formed in the PMOS region (I). 37) and a gate electrode having a stacked structure of the n + polycrystalline silicon layer pattern 39 and the metal layer pattern 41 are formed in the stacked structure of the metal layer pattern 41 and the NMOS region (II). (See Figure 2E)
다음, 상기 희생절연막(29)을 제거하여 상기 게이트전극을 노출시킨다.Next, the sacrificial insulating layer 29 is removed to expose the gate electrode.
그 다음, 상기 게이트전극의 금속층패턴(41) 상부에 마스크절연막패턴(43)을 형성한다.Next, a mask insulating layer pattern 43 is formed on the metal layer pattern 41 of the gate electrode.
그 후, 상기 마스크절연막패턴(43)과 게이트전극의 측벽에 절연막 스페이서(45)를 형성한다. (도 2f 참조)Thereafter, insulating film spacers 45 are formed on sidewalls of the mask insulating film pattern 43 and the gate electrode. (See Figure 2f)
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 제조방법은, 듀얼 게이트전극 제조공정에서 듀얼 다마신(dual damascene) 구조를 이용하여 게이트전극이 형성될 영역을 노출시키는 절연막패턴을 형성하고, 전체표면 상부에 p+ 다결정실리콘층을 형성하여 PMOS 소자를 구현하고, NMOS영역에 형성되어 있는 p+ 다결정실리콘층에 n+ 불순물을 이용한 카운터 도핑으로 NMOS소자를 구현함으로써 p+ 이온주입공정에 의해 게이트절연막의 특성이 저하되는 것을 방지할 수 있고, 게이트전극으로 구성되는 다결정실리콘층의 두께 조절을 용이하게 하는 이점이 있다.As described above, in the method of manufacturing a semiconductor device according to the present invention, a dual damascene structure is used in a dual gate electrode manufacturing process to form an insulating film pattern that exposes an area where a gate electrode is to be formed, and the entire surface thereof. The PMOS device is formed by forming a p + polysilicon layer on the top, and the NMOS device is implemented by counter doping using n + impurities in the p + polysilicon layer formed in the NMOS region, thereby degrading the characteristics of the gate insulating film by the p + ion implantation process. Can be prevented, and the thickness of the polysilicon layer composed of the gate electrode can be easily controlled.
Claims (8)
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