KR20020051536A - Method for fabricating bonding pad in semiconductor device - Google Patents
Method for fabricating bonding pad in semiconductor device Download PDFInfo
- Publication number
- KR20020051536A KR20020051536A KR1020000080890A KR20000080890A KR20020051536A KR 20020051536 A KR20020051536 A KR 20020051536A KR 1020000080890 A KR1020000080890 A KR 1020000080890A KR 20000080890 A KR20000080890 A KR 20000080890A KR 20020051536 A KR20020051536 A KR 20020051536A
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- Prior art keywords
- bonding pad
- teos
- film
- layer
- metal
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
Abstract
Description
본 발명은 반도체소자의 제조 방법에 관한 것으로, 특히 기계적 스트레스(Mechnical stress)에 의한 본딩(Bonding)시 필오프(Peel-off) 현상을 방지하도록 한 본딩 패드(Bonding pad)의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a bonding pad to prevent peel-off when bonding is caused by mechanical stress. .
도 1은 종래기술에 따라 제조된 본딩패드의 구조를 나타낸 단면도이다.1 is a cross-sectional view showing the structure of a bonding pad manufactured according to the prior art.
도 1에 도시된 바와 같이, 소정 공정이 완료된 층간절연막(11)상에 소정 간격을 두고 다수의 금속배선(12)을 형성한 후, 금속배선(12)상에 IMD(Inter Metal Dielectric)로서 TEOS/SOG/TEOS(13/14/15)을 순차적으로 형성한다. 이 때, SOG(14)는 자체 평탄화가 가능하므로 금속배선(12)간 매립되는 TEOS(13)로 인한 단차를 완화시키며 후속 TEOS(15) 형성시 평탄화가 가능하다.As shown in FIG. 1, after forming a plurality of metal wires 12 at predetermined intervals on the interlayer insulating film 11 in which a predetermined process is completed, TEOS as IMD (Inter Metal Dielectric) on the metal wires 12. / SOG / TEOS (13/14/15) are formed sequentially. At this time, since the SOG 14 is capable of self-planarization, the step difference caused by the TEOS 13 embedded between the metal lines 12 may be alleviated, and the SOG 14 may be planarized in the formation of the subsequent TEOS 15.
TEOS(15)상에 본딩패드용 금속을 증착한 후, 선택적으로 식각하여 본딩패드(16)를 형성한다.After depositing the bonding pad metal on the TEOS 15, the bonding pad 16 is selectively etched to form the bonding pad 16.
그러나, 상술한 종래기술에서는 본딩패드(16) 하부의 금속배선(12)을 막대 모양으로 한정하므로써 USG(14) 형성시 단차에 의해 두껍게 매립되는 부분과 얇게 매립되는 부분이 발생되므로서, 본딩패드(16)에 본딩시 USG(14)에 스트레스를 전달하여 전체적으로 본딩패드(16) 하부의 층간절연막에 크랙 또는 파괴가 발생된다.However, in the above-described prior art, by limiting the metal wiring 12 below the bonding pad 16 to the shape of a rod, a portion that is thickly embedded and a portion that is thinly buried due to a step occurs when the USG 14 is formed. When bonding to the (16), the stress is transmitted to the USG (14), the crack or breakage occurs in the interlayer insulating film under the bonding pad 16 as a whole.
이로 인해 층간절연막의 필오프 현상이 발생하는 문제점이 있다.As a result, a peel-off phenomenon of the interlayer insulating film occurs.
본 발명은 상기 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 기계적 스트레스에 의한 층간절연막의 크랙 및 파괴를 방지하고, 필오프 현상을 방지하는데 적합한 본딩패드의 제조 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the problems of the prior art, an object of the present invention is to provide a method of manufacturing a bonding pad suitable for preventing the crack and breakage of the interlayer insulating film due to mechanical stress, and to prevent the peel off phenomenon.
도 1은 종래기술에 따라 제조된 본딩패드의 구조 단면도,1 is a structural cross-sectional view of a bonding pad manufactured according to the prior art,
도 2a 내지 도 2c는 본 발명의 실시예에 따른 본딩패드의 제조 방법을 나타낸 공정 단면도.2A to 2C are cross-sectional views illustrating a method of manufacturing a bonding pad according to an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21 : 층간절연막 22 : 하부 금속막21: interlayer insulating film 22: lower metal film
23 : TEOS 24 : USG23: TEOS 24: USG
25 : TEOS 26 : 보호막25: TEOS 26: protective film
상기의 목적을 달성하기 위한 본 발명의 본딩패드의 제조 방법은 소정 공정이 완료된 하부층상에 금속막을 형성하는 단계, 상기 금속막상에 층간절연막을 형성하는 단계, 상기 층간절연막상에 보호막을 형성하는 단계, 상기 보호막을 선택적으로 식각하되, 상기 층간절연막까지 과도식각하는 단계, 및 상기 보호막을 하드마스크로 하여 상기 층간절연막을 식각하여 상기 금속막을 노출시키는 단계를 포함하여 이루어짐을 특징으로 한다.The method of manufacturing a bonding pad of the present invention for achieving the above object comprises the steps of forming a metal film on the lower layer, a predetermined process is completed, forming an interlayer insulating film on the metal film, forming a protective film on the interlayer insulating film And selectively etching the passivation layer, overetching the interlayer insulation layer, and etching the interlayer insulation layer using the passivation layer as a hard mask to expose the metal layer.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 2a 내지 도 2c는 본 발명의 실시예에 따른 본딩 패드의 제조 방법을 나타낸 공정 단면도이다.2A to 2C are cross-sectional views illustrating a method of manufacturing a bonding pad according to an embodiment of the present invention.
도 2a에 도시된 바와 같이, 반도체기판이나 층간절연막과 같은 하부층(21)상에 본딩패드부 하부 금속막(22)을 형성한 후, 하부 금속막(22)상에 IMD으로서 TEOS/USG/TEOS(23/24/25) 적층막을 형성한다.As shown in FIG. 2A, after forming the bonding pad portion lower metal film 22 on the lower layer 21 such as a semiconductor substrate or an interlayer insulating film, TEOS / USG / TEOS as an IMD on the lower metal film 22 is formed. (23/24/25) A laminated film is formed.
도 2b에 도시된 바와 같이, IMD의 최상층인 TEOS(25)상에 보호막(26)을 형성한다. 이 때, 보호막(26)은 질화막을 이용할 수 있다.As shown in FIG. 2B, a protective film 26 is formed on the TEOS 25, which is the uppermost layer of the IMD. At this time, the protective film 26 may use a nitride film.
보호막(26)을 포토 및 식각하여 TEOS(25)까지 과도 식각하여 본딩패드 영역을 노출시킨다.The protective layer 26 is photo-etched and over-etched to TEOS 25 to expose the bonding pad region.
도 2c에 도시된 바와 같이, 보호막(26)을 하드마스크로 하여 하부 금속막(22)이 드러날때까지 TEOS/USG/TEOS(23/24/25) 적층막을 식각한다. 이 때, 드러난 하부 금속막(22)을 본딩패드로 이용한다.As shown in FIG. 2C, the TEOS / USG / TEOS (23/24/25) laminated film is etched using the protective film 26 as a hard mask until the lower metal film 22 is exposed. At this time, the exposed lower metal film 22 is used as a bonding pad.
상술한 바와 같이 본 발명의 실시예에서는 금속막(22)상부에 IMD를 완전히 제거하여 금속막(22)을 노출시키므로 후속 본딩시 스트레스에 의한 필오프 현상을 방지한다.As described above, in the embodiment of the present invention, the IMD is completely removed on the metal film 22 to expose the metal film 22, thereby preventing the peel-off phenomenon due to stress during subsequent bonding.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명의 본딩패드의 제조 방법은 통상의 공정으로 적용가능하면서도 본딩패드 하부의 금속막상에 존재하던 IMD을 제거하므로써 하부 금속막을 이용하는 본딩패드 구조로 필오프 현상을 방지할 수 있는 효과가 있다.The method of manufacturing the bonding pad of the present invention as described above is applicable to a conventional process, but by removing the IMD existing on the metal film under the bonding pad, the effect of preventing the peel-off phenomenon by the bonding pad structure using the lower metal film. There is.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2000-0080890A KR100399059B1 (en) | 2000-12-22 | 2000-12-22 | Method for fabricating bonding pad in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2000-0080890A KR100399059B1 (en) | 2000-12-22 | 2000-12-22 | Method for fabricating bonding pad in semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20020051536A true KR20020051536A (en) | 2002-06-29 |
| KR100399059B1 KR100399059B1 (en) | 2003-09-26 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-2000-0080890A KR100399059B1 (en) | 2000-12-22 | 2000-12-22 | Method for fabricating bonding pad in semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100591159B1 (en) * | 2004-09-17 | 2006-06-19 | 동부일렉트로닉스 주식회사 | Method of opening pad in semiconductor device |
-
2000
- 2000-12-22 KR KR10-2000-0080890A patent/KR100399059B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100591159B1 (en) * | 2004-09-17 | 2006-06-19 | 동부일렉트로닉스 주식회사 | Method of opening pad in semiconductor device |
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| Publication number | Publication date |
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| KR100399059B1 (en) | 2003-09-26 |
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