KR20020050486A - Method for fabricating capacitor - Google Patents
Method for fabricating capacitor Download PDFInfo
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- KR20020050486A KR20020050486A KR1020000079642A KR20000079642A KR20020050486A KR 20020050486 A KR20020050486 A KR 20020050486A KR 1020000079642 A KR1020000079642 A KR 1020000079642A KR 20000079642 A KR20000079642 A KR 20000079642A KR 20020050486 A KR20020050486 A KR 20020050486A
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- lower electrode
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- 238000000034 method Methods 0.000 title claims abstract description 21
- 239000003990 capacitor Substances 0.000 title claims abstract description 16
- 229910052751 metal Inorganic materials 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 15
- 238000004544 sputter deposition Methods 0.000 claims abstract description 7
- 239000002131 composite material Substances 0.000 claims abstract description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 9
- 229910052707 ruthenium Inorganic materials 0.000 claims description 3
- 229910052727 yttrium Inorganic materials 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 230000009977 dual effect Effects 0.000 claims description 2
- 229910052741 iridium Inorganic materials 0.000 claims description 2
- 229910052697 platinum Inorganic materials 0.000 claims 1
- 229910052718 tin Inorganic materials 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 11
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 abstract description 8
- 230000003647 oxidation Effects 0.000 abstract description 8
- 238000007254 oxidation reaction Methods 0.000 abstract description 8
- 239000011229 interlayer Substances 0.000 abstract description 7
- 230000004888 barrier function Effects 0.000 abstract description 5
- 229910021341 titanium silicide Inorganic materials 0.000 abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 3
- 229920005591 polysilicon Polymers 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 229910052814 silicon oxide Inorganic materials 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 반도체소자에 대한 것으로, 특히 커패시터의 제조방법에 관한 것이다.The present invention relates to a semiconductor device, and more particularly to a method of manufacturing a capacitor.
기가 비트(Giga bit)급 디램에서는 유전율이 큰 BST를 유전체막으로 사용하는 MIM(Metal Insulator Metal) 구조의 커패시터를 형성한다.In the giga bit DRAM, a capacitor having a metal insulator metal (MIM) structure using a high dielectric constant BST as a dielectric film is formed.
이때 하부전극과 기판의 불순물영역을 연결해주기 위한 폴리플러그를 사용하고, 폴리플러그와 하부전극의 사이에 티타늄 실리사이드막(TiSi2)과 티타늄 나이트라이드막(TiN)을 형성한다. TiSi2와 TiN은 충분히 내산화성을 갖지 못한다.In this case, a polyplug is used to connect the lower electrode and the impurity region of the substrate, and a titanium silicide layer (TiSi2) and a titanium nitride layer (TiN) are formed between the polyplug and the lower electrode. TiSi2 and TiN do not have sufficient oxidation resistance.
그리고 상기에 하부전극과 BST 유전체막과 상부전극을 형성한다.A lower electrode, a BST dielectric film, and an upper electrode are formed thereon.
이때 BST를 증착한 후에 결정화를 위한 열처리 공정을 진행한다.At this time, after the BST is deposited, a heat treatment process for crystallization is performed.
상기와 같은 BST의 결정화를 위한 열처리 공정을 진행하므로 하부전극은 2중 또는 3중(Pt/IrO2/Ir 또는 RuO2/Ru/Pt)의 다층막으로 형성한다.Since the heat treatment process for the crystallization of the BST as described above is carried out, the lower electrode is formed of a multilayer film of double or triple (Pt / IrO 2 / Ir or RuO 2 / Ru / Pt).
상기와 같은 종래 커패시터는 다음과 같은 문제가 있다.The conventional capacitor as described above has the following problems.
첫째, BST 유전체막을 열처리할 때 하부전극과 베리어금속막인 TiN이 산화되어 커패시터의 내산화성을 확보하기가 어렵다.First, when the BST dielectric film is heat-treated, the lower electrode and the barrier metal film TiN are oxidized, and thus it is difficult to secure oxidation resistance of the capacitor.
둘째, 하부전극을 2중 또는 3중막으로 형성하므로 공정이 복잡해지고 제조원가도 높아져서 시장 경쟁력이 떨어진다.Second, since the lower electrode is formed of a double or triple film, the process is complicated and the manufacturing cost is high, resulting in poor market competitiveness.
본 발명은 상기와 같은 문제를 해결하기 위하여 안출한 것으로 특히, 고온에서도 내산화 특성이 우수하며 공정을 단순화 시키기에 알맞은 커패시터의 제조방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, and in particular, an object of the present invention is to provide a method for producing a capacitor suitable for simplifying the process and excellent oxidation resistance even at high temperatures.
도 1a 내지 도 1d는 본 발명 실시예에 따른 커패시터의 제조방법을 나타낸 공정단면도1A to 1D are cross-sectional views illustrating a method of manufacturing a capacitor according to an embodiment of the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
1 : 실리콘기판 2 : 층간절연막1 silicon substrate 2 interlayer insulating film
3 : 폴리 플러그 4 : 티타늄 실리사이드막3: poly plug 4: titanium silicide film
5 : 티타늄 나이트라이드막 6 : 실리콘질화막5: titanium nitride film 6: silicon nitride film
7 : 실리콘산화막 8 : 하부전극7: silicon oxide film 8: lower electrode
9 : 유전체막 10 : 상부전극9 dielectric film 10 upper electrode
상기와 같은 목적을 달성하기 위한 본 발명 커패시터의 제조방법은 금속을 스퍼터링하는 공정 중에 산화 자유에너지가 상기 금속보다 큰 원소를 상기 금속에 도핑하여 커패시터의 하부전극을 형성하는 단계, 상기 하부전극상에 유전체막을 형성하는 단계, 상기 유전체막상에 상부전극을 형성하는 단계를 포함함을 특징으로한다.According to another aspect of the present invention, there is provided a method of manufacturing a capacitor, in which a lower electrode of a capacitor is formed by doping an element having an oxidative free energy greater than the metal to the metal during the sputtering of the metal. Forming a dielectric film, and forming an upper electrode on the dielectric film.
첨부 도면을 참조하여 본 발명 커패시터의 제조방법에 대하여 설명하면 다음과 같다.Referring to the accompanying drawings, a method of manufacturing the capacitor of the present invention will be described.
도 1a 내지 도 1d는 본 발명 실시예에 따른 커패시터의 제조방법을 나타낸 공정단면도이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a capacitor according to an exemplary embodiment of the present invention.
본 발명 실시예에 따른 커패시터의 제조방법은 도 1a에 도시한 바와 같이 기판(1)상에 층간절연막(2)을 증착하고, 사진 식각공정으로 기판(1)의 일영역이 드러나도록 층간절연막(2)내에 콘택홀을 형성한다.In the method of manufacturing a capacitor according to the embodiment of the present invention, as shown in FIG. 2) Contact holes are formed.
콘택홀 형성후 비오이(BOE:Buffer Oxide Etchant)로 세정한다.After the contact hole is formed, it is washed with BOE (Buffer Oxide Etchant).
이후에 콘택홀을 포함한 층간절연막(2)상에 화학기상증착법이나 에피텍셜로 폴리실리콘을 증착한 후 콘택홀내에만 남도록 폴리실리콘을 식각해서 폴리플러그(3)를 형성한다.After that, polysilicon is deposited on the interlayer insulating film 2 including the contact hole by chemical vapor deposition or epitaxially, and then polysilicon is etched to remain only in the contact hole to form a poly plug 3.
이때 폴리플러그(3)은 층간절연막(2)상부와 일정 거리 떨어진 높이만큼 남는다.At this time, the poly plug 3 remains at a height apart from the upper portion of the interlayer insulating film 2 by a predetermined distance.
그리고 폴리플러그(3)상에 티타늄(Ti)막을 5~50nm의 두께를 갖도록 증착하고, 600~750℃범위의 온도에서 급속열처리하여 폴리플러그(3)와의 계면에 티타늄 실리사이드막(TiSi2)(4)을 형성한다. 이후에 미반응한 Ti막을 습식각으로 제거한다.Then, a titanium (Ti) film was deposited on the polyplug 3 to have a thickness of 5 to 50 nm, and rapidly heat-treated at a temperature in the range of 600 to 750 ° C. to form a titanium silicide film (TiSi 2) (4) at the interface with the poly plug 3. ). Thereafter, the unreacted Ti film is removed by wet etching.
다음에 콘택홀을 포함한 층간절연막(2)상에 50~90nm의 두께를 갖도록 티타늄 나이트라이드막(TiN)(5)을 형성한다.Next, a titanium nitride film (TiN) 5 is formed on the interlayer insulating film 2 including the contact hole to have a thickness of 50 to 90 nm.
이후에 화학적 기계적 연마공정으로 층간절연막(2)상부의 티타늄 나이트라이드막(TiN)(5)을 제거하여 콘택홀내에만 티타늄 나이트라이드막(TiN)(5)이 남도록 한다.Thereafter, the titanium nitride film (TiN) 5 on the interlayer insulating film 2 is removed by a chemical mechanical polishing process so that the titanium nitride film (TiN) 5 remains only in the contact hole.
그리고 도 1b에 도시한 바와 같이 티타늄 나이트라이드막(TiN)(5)을 포함한 층간절연막(5)상에 식각스톱층으로 실리콘 질화막(Si3N4)(6)을 증착하고, 실리콘질화막(6)상에 실리콘 산화막(SiO2)(7)을 차례로 증착한다.As shown in FIG. 1B, a silicon nitride film (Si 3 N 4) 6 is deposited on the interlayer insulating film 5 including the titanium nitride film (TiN) 5 as an etch stop layer, and on the silicon nitride film 6. A silicon oxide film (SiO 2) 7 is deposited in sequence.
이때 실리콘 질화막(6)은 50~150nm의 두께를 갖도록 증착하고, 실리콘산화막(7)은 1000~2000nm의 두께를 갖도록 증착한다.In this case, the silicon nitride film 6 is deposited to have a thickness of 50 to 150 nm, and the silicon oxide film 7 is deposited to have a thickness of 1000 to 2000 nm.
이후에 스토리지 노드 콘택홀을 형성하기 위한 마스크를 이용해서 실리콘산화막(7)과 실리콘질화막(6)을 식각해서 요면(凹面)(Concave)을 갖는 스토리지 노드 콘택홀을 형성하는 사이드월이 형성한다.Thereafter, a sidewall is formed to etch the silicon oxide film 7 and the silicon nitride film 6 by using a mask for forming the storage node contact hole to form a storage node contact hole having a concave.
그리고 도 1c에 도시한 바와 같이 상기 식각된 실리콘산화막(7)과 실리콘질화막(6)을 포함한 스토리지 노드 콘택홀을 따라서 Ru를 스퍼터 공정으로 증착하는 공정을 진행하고 in-situ로 Y를 Ru에 도핑해서 하부전극(8)을 형성한다.As shown in FIG. 1C, a process of depositing Ru by a sputtering process is performed along a storage node contact hole including the etched silicon oxide film 7 and the silicon nitride film 6, and doping Y to Ru in-situ. The lower electrode 8 is formed.
이때 하부전극(8)은 Ru를 증착하다가 1~10kW의 RF 파워를 이용해서 Ru-Y 합성물(composite) 타겟이나 Ru, Y의 듀얼 타겟을 이용한 스퍼터링으로 20~100nm의 두께를 갖는 Y가 도핑된 하부전극(8)을 형성하는 것이다.At this time, the lower electrode 8 is deposited with Ru and then doped with Y having a thickness of 20 to 100 nm by sputtering using a Ru-Y composite target or a dual target of Ru and Y using RF power of 1 to 10 kW. The lower electrode 8 is formed.
그리고 이때 Ru 내의 Y의 조성은 0.5~10%at로 유지한다.At this time, the composition of Y in Ru is maintained at 0.5-10% at.
이후에 실리콘산화막(7) 상부가 드러나도록 하부전극(8)을 화학적 기계적 연마하여 이웃하는 하부전극(8)과의 연결을 끊어준다.Subsequently, the lower electrode 8 is chemically mechanically polished to expose the upper portion of the silicon oxide film 7, thereby disconnecting the neighboring lower electrode 8.
다음에 도 1d에 도시한 바와 같이 하부전극(8)과 실리콘산화막(7)을 포함한 전면에 20~100nm의 두께를 갖도록 BST로 구성된 유전체막(9)을 증착하고, 유전체막(9)상에 상부전극(10)을 형성한다.Next, as shown in FIG. 1D, a dielectric film 9 composed of BST is deposited on the entire surface including the lower electrode 8 and the silicon oxide film 7 to have a thickness of 20 to 100 nm, and then on the dielectric film 9. The upper electrode 10 is formed.
이때 유전체막(9)은 피브이디(Physical Vapor Deposition)나 씨브이디(Chemical Vapor Deposition)법으로 증착한 후에 600~700℃의 온도의 산소분위기에서 열처리하여 결정화 시키고 PZT로도 형성할 수 있다.In this case, the dielectric film 9 may be deposited by physical vapor deposition or chemical vapor deposition, and then crystallized by heat treatment in an oxygen atmosphere at a temperature of 600 to 700 ° C., and may be formed of PZT.
그리고 상부전극(10)은 Ru, TiN, Ir 또는 Pt를 50~150nm의 두께를 갖도록 피브이디(Physical Vapor Deposition)나 씨브이디(Chemical Vapor Deposition)법으로 형성한다.The upper electrode 10 is formed of a physical vapor deposition or chemical vapor deposition method such that Ru, TiN, Ir, or Pt has a thickness of 50 to 150 nm.
상기에서 Y가 도핑된 Ru로 구성된 하부전극(8)에서 Ru와 Y의 산화물 형성 자유에너지는 공정이 진행될 정도의 고온 예를 들어 1000K(727℃)에서 각각 -130.9kj/mol과 -1618kj/mol로서 Y가 12배 이상 크다.In the lower electrode 8 composed of Y doped Ru, the free energy of forming oxides of Ru and Y is -130.9kj / mol and -1618kj / mol at a high temperature such that the process proceeds, for example, 1000K (727 ° C) Y is more than 12 times larger.
따라서 Ru내에 산소가 침투하면 Y만 선택적으로 산화되는 소위 내부산화 현상이 일어난다.Therefore, when oxygen penetrates into Ru, so-called internal oxidation occurs that only Y is selectively oxidized.
이러한 내부산화의 결과로 Ru 내에 미세한 Y2O3가 고르게 분산되어 분포한다.As a result of this internal oxidation, fine Y 2 O 3 is evenly distributed and distributed in Ru.
이와 같이 외부에서 하부전극으로 유입되는 산소를 Y가 모두 소모하므로 하부전극 Ru나 베리어 금속막인 티타늄 나이트라이드막이 산화되는 것이 방지된다.As described above, since Y consumes all oxygen introduced into the lower electrode from the outside, the lower electrode Ru or the titanium nitride film, which is the barrier metal film, is prevented from being oxidized.
상기와 같은 본 발명 커패시터의 제조방법은 다음과 같은 효과가 있다.The method of manufacturing the capacitor of the present invention as described above has the following effects.
첫째, 하부전극을 Y를 포함한 Ru로 구성하므로 외부에서 하부전극으로 유입되는 산소가 하부전극과 베리어 금속막을 산화시키는 현상을 효과적으로 방지할 수 있다.First, since the lower electrode is composed of Ru including Y, oxygen flowing into the lower electrode from the outside can be effectively prevented from oxidizing the lower electrode and the barrier metal film.
이에 따라서 고온에서도 내산화 특성이 우수한 커패시터를 형성할 수 있다.Accordingly, a capacitor having excellent oxidation resistance even at high temperatures can be formed.
둘째, 하부전극을 Ru를 스퍼터하는 공정중에 in-situ로 Y를 도핑하여 형성하므로 공정을 단순화 시킬 수 있다.Second, since the lower electrode is formed by doping Y in-situ during the process of sputtering Ru, the process can be simplified.
Claims (7)
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030047077A (en) * | 2001-12-07 | 2003-06-18 | 삼성전자주식회사 | Method for manufacturing metal - Insulator - Metal capacitor |
| KR100524935B1 (en) * | 2002-11-04 | 2005-10-31 | 삼성전자주식회사 | Method for manufacturing semiconductor memory device |
| US8436520B2 (en) | 2010-07-29 | 2013-05-07 | Federal-Mogul Ignition Company | Electrode material for use with a spark plug |
| US8471451B2 (en) | 2011-01-05 | 2013-06-25 | Federal-Mogul Ignition Company | Ruthenium-based electrode material for a spark plug |
| US8575830B2 (en) | 2011-01-27 | 2013-11-05 | Federal-Mogul Ignition Company | Electrode material for a spark plug |
| US8760044B2 (en) | 2011-02-22 | 2014-06-24 | Federal-Mogul Ignition Company | Electrode material for a spark plug |
| US8766519B2 (en) | 2011-06-28 | 2014-07-01 | Federal-Mogul Ignition Company | Electrode material for a spark plug |
| US8890399B2 (en) | 2012-05-22 | 2014-11-18 | Federal-Mogul Ignition Company | Method of making ruthenium-based material for spark plug electrode |
| US8979606B2 (en) | 2012-06-26 | 2015-03-17 | Federal-Mogul Ignition Company | Method of manufacturing a ruthenium-based spark plug electrode material into a desired form and a ruthenium-based material for use in a spark plug |
| US10044172B2 (en) | 2012-04-27 | 2018-08-07 | Federal-Mogul Ignition Company | Electrode for spark plug comprising ruthenium-based material |
-
2000
- 2000-12-21 KR KR10-2000-0079642A patent/KR100379527B1/en not_active IP Right Cessation
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030047077A (en) * | 2001-12-07 | 2003-06-18 | 삼성전자주식회사 | Method for manufacturing metal - Insulator - Metal capacitor |
| KR100524935B1 (en) * | 2002-11-04 | 2005-10-31 | 삼성전자주식회사 | Method for manufacturing semiconductor memory device |
| US8436520B2 (en) | 2010-07-29 | 2013-05-07 | Federal-Mogul Ignition Company | Electrode material for use with a spark plug |
| US8471451B2 (en) | 2011-01-05 | 2013-06-25 | Federal-Mogul Ignition Company | Ruthenium-based electrode material for a spark plug |
| US8575830B2 (en) | 2011-01-27 | 2013-11-05 | Federal-Mogul Ignition Company | Electrode material for a spark plug |
| US8760044B2 (en) | 2011-02-22 | 2014-06-24 | Federal-Mogul Ignition Company | Electrode material for a spark plug |
| US8766519B2 (en) | 2011-06-28 | 2014-07-01 | Federal-Mogul Ignition Company | Electrode material for a spark plug |
| US10044172B2 (en) | 2012-04-27 | 2018-08-07 | Federal-Mogul Ignition Company | Electrode for spark plug comprising ruthenium-based material |
| US8890399B2 (en) | 2012-05-22 | 2014-11-18 | Federal-Mogul Ignition Company | Method of making ruthenium-based material for spark plug electrode |
| US8979606B2 (en) | 2012-06-26 | 2015-03-17 | Federal-Mogul Ignition Company | Method of manufacturing a ruthenium-based spark plug electrode material into a desired form and a ruthenium-based material for use in a spark plug |
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| Publication number | Publication date |
|---|---|
| KR100379527B1 (en) | 2003-04-10 |
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