KR100223893B1 - The manufacturing method of semiconductor memory device - Google Patents

Abstract

The present invention relates to a semiconductor memory device, and more particularly, to a method of manufacturing a semiconductor memory device suitable for preventing diffusion between a capacitor lower electrode and polysilicon and reducing sheet resistance of the barrier metal layer.

A method of manufacturing a semiconductor memory device according to the present invention includes forming an insulating film on a semiconductor substrate; Selectively patterning the insulating layer to form a node contact hole; Forming a semiconductor layer plug in the node contact hole; Sequentially forming a TaSiN layer and a lower electrode on the upper layer of the semiconductor layer and the entire insulating layer; Patterning the lower electrode and the TaSiN layer so that only the capacitor region remains; Forming a high dielectric film on surfaces of the TaSiN layer and the lower electrode; And forming an upper electrode on the entire high dielectric layer.

Description

Manufacturing Method of Semiconductor Memory Device

The present invention relates to a semiconductor memory device, and more particularly, to a method of manufacturing a semiconductor memory device suitable for preventing diffusion between a capacitor lower electrode and polysilicon and reducing sheet resistance of the barrier metal layer.

In general, capacitors have been gradually reducing the thickness of the dielectric film to compensate for the reduction in capacitance as the area of the device increases as the device density increases. However, as the thickness of the dielectric film decreases, leakage current due to tunneling increases, and the reliability of the capacitor gradually decreases due to the leakage current and the thinning of the dielectric film thickness.

As a method of avoiding the thinning of the dielectric film, a method of increasing the effective area of a capacitor by forming a very complex surface bending at a storage node is widely used. In addition, the thin film is fabricated using a nitride / oxide layer or oxide / nitride / oxide layer having a high dielectric constant as the dielectric film of the capacitor. It is expected to be difficult to use in high-integration devices of 256MB DRAM or more due to problems such as difficult process and higher process cost. Accordingly, a method of using a material having a high dielectric constant as the dielectric film of a capacitor has been proposed as a method of dramatically improving the capacitance of the capacitor and reducing the surface curvature.

Ta ₂ O ₅ is the most studied material for high dielectric constant for capacitors. This material has many achievements in thinning, improving characteristics, and integration, but its practical dielectric constant is not so high. Recently, interest in perovskite-type oxides is increasing, and in particular, it is the subject of intensive research as a high dielectric film to be used in semiconductor devices.

Such high-k dielectric materials include PZT [(Pb (Zr, Ti) O ₃ ], PLZT [(Pb, La) (Zr, Ti) O ₃ ], BST [((Ba, Sr) TiO ₃ ], BaTiO ₃ , SrTiO ₃ etc. However, these materials melt at high temperatures of 600-700 ° C. and react easily with silicon or polysilicon, and the surface is exposed to a strong oxidizing atmosphere during the formation of capacitor high-k dielectric films. Many studies have been conducted to solve the problems caused by the actual integration process such as the electrode material and structure due to the oxidation of the node.

In addition, platinum (Pt), palladium (Pd), rhodium (Rh), RuO ₂ and IrO ₂ are known as materials that form a lower electrode such as a storage node, and are known as materials that do not oxidize well to suppress leakage current. Etc. are used.

Hereinafter, a method of manufacturing a conventional semiconductor memory device will be described with reference to the accompanying drawings.

1A to 1G are cross-sectional views of a manufacturing process of a conventional semiconductor memory device.

First, as shown in FIG. 1A, the field oxide film 2 and the gate electrode 3 are formed on the semiconductor substrate 1 using a conventional process, and then the source / side of the semiconductor substrate 1 on both sides of the gate electrode 3 is formed. A high concentration impurity region 4 to be used as the drain region is formed. At this time, reference numeral 5 denotes a gate insulating film for insulating the gate electrode 3.

As shown in Fig. 1B, the first oxide film 6 is deposited on the front surface of the substrate including the gate electrode 3 by using a material having good flatness. Thereafter, the first oxide layer 6 is selectively patterned (photolithography process + etching process) so as to expose the high concentration impurity region 4a on one side of the gate electrode 3 to form a bit line contact hole 7.

As shown in FIG. 1C, a polysilicon layer is formed on the entire surface of the bit line contact hole 7 and the first oxide film 6, and then selectively patterned to form a bit line 8. Next, a second oxide film 9 is formed on the entire surface of the first oxide film 6 including the bit line 8.

As shown in FIG. 1D, the first and second oxide films 6 and 9 are selectively patterned to form the node contact hole 10 so that the high concentration impurity region 4b on the other side of the gate electrode 3 is exposed. . Then, the polysilicon plug 11 is formed using polysilicon in the node contact hole 10.

As shown in FIG. 1E, the barrier metal layer 12, the lower layer electrode 13, and the photoresist film PR are sequentially formed on the entire surface of the second oxide film 9 including the polysilicon plug 11, and then exposed and developed. The photoresist film PR is patterned to remain only in the capacitor region. In this case, the lower electrode 13 is formed using platinum, and the barrier metal layer 12 is formed using any one material of TiN, TiW or TaN.

As shown in FIG. 1F, the lower electrode 13 and the barrier metal layer 12 are selectively removed by an etching process using the patterned photoresist film PR as a mask. Then, the photoresist film PR is removed.

As shown in FIG. 1G, a high-k dielectric film 14 and an upper electrode 15 are sequentially formed on the surfaces of the lower electrode 13 and the barrier metal layer 12 to complete a conventional semiconductor memory device. At this time, TiN, TaW and TiW used as the barrier metal layer 12 are destroyed at a high temperature of 600 ° C. or higher, so that the thermal stability (increase in sheet resistance after high temperature heat treatment and diffusion preventing ability) is deposited. Although not shown in the drawings, a high temperature heat treatment of 800 ° C. or higher is required for the flat layer in order to have excellent flatness in the process of forming the flat layer after the wiring process proceeded in a subsequent process.

In the conventional method of manufacturing a semiconductor memory device, platinum used as a storage node is a material having excellent properties of oxidation resistance, but vulnerable to preventing diffusion of oxygen, and a barrier metal such as TiN, TaN, or TiW between platinum and a polysilicon plug. It was formed to prevent contact between the oxygen atom of the high dielectric film and the polysilicon plug. However, the high temperature heat treatment process of about 800 ° C. or higher for planarization of ILD (Inter Layer Dielectrics) or IMD (Inter Metal Dielectrics) layers in the high temperature process of 600-700 ° C. required in the high dielectric film stacking process and the subsequent wiring process. As the barrier metal in contact with the polysilicon plug reacts, as shown in the graph of FIG. 3, there is a problem that the characteristics of the barrier metal are deteriorated due to the problem that the sheet resistance increases by about 100Ω or more at the interface. In order to solve the problem, there are technical difficulties such as maintaining the temperature of about 600 ° C. or less when the high dielectric film is deposited, and when deposited at 600 ° C. or less, there is a problem that high dielectric constant of the high dielectric film cannot be expected.

The present invention has been made to solve the problems of the conventional method of manufacturing a semiconductor memory device as described above by using the TaSiN layer as a barrier metal to prevent diffusion between the lower electrode of the capacitor and polysilicon and to reduce the sheet resistance of the barrier metal layer. It is an object of the present invention to provide a method for manufacturing a suitable semiconductor memory device.

1A to 1G are cross-sectional views of a manufacturing process of a conventional semiconductor memory device.

2A to 2G are cross-sectional views of a manufacturing process of the semiconductor memory device according to the present invention.

Figure 3 is a graph showing the temperature dependence of the sheet resistance with temperature in the junction diatom of the barrier metal and polysilicon according to the present invention

* Explanation of symbols for main parts of the drawings

20: semiconductor substrate 21: field oxide film

22: gate electrode 23: high concentration impurity region

24 gate insulating film 25 first insulating film

26: bit line contact hole 27: bit line

28: second insulating film 29: node contact hole

30 semiconductor layer plug 31 barrier metal layer

32: lower electrode 33: high dielectric film

34: upper electrode

A method of manufacturing a semiconductor memory device according to the present invention includes forming an insulating film on a semiconductor substrate; Selectively patterning the insulating layer to form a node contact hole; Forming a semiconductor layer plug in the node contact hole; Sequentially forming a TaSiN layer and a lower electrode on the upper layer of the semiconductor layer plug and on the entire surface of the insulating layer; Patterning the lower electrode and the TaSiN layer so that only the capacitor region remains; Forming a high dielectric film on surfaces of the TaSiN layer and the lower electrode; And forming an upper electrode on the entire high dielectric layer.

Such a method for manufacturing a semiconductor memory device of the present invention will be described with reference to the accompanying drawings.

2A through 2G are cross-sectional views illustrating a manufacturing process of a semiconductor memory device according to the present invention.

First, as shown in FIG. 2A, the field oxide film 21 and the gate electrode 22 are formed on the semiconductor substrate 20 using a conventional process, and then the source / film is formed on both semiconductor substrates 20 of the gate electrode 22. A high concentration impurity region 23 to be used as the drain region is formed. In this case, reference numeral 24 is a gate insulating film for insulating the gate electrode 22.

As shown in FIG. 2B, the first insulating layer 25 is deposited on the entire surface of the substrate including the gate electrode 22 by using a material having good flatness. Thereafter, the first insulating layer 25 is selectively patterned (photolithography process + etching process) so as to expose the high concentration impurity region 23a on one side of the gate electrode 22 to form a bit line contact hole 26.

As shown in FIG. 2C, a polysilicon layer is formed on the entire surface of the bit line contact hole 26 and the first insulating layer 25, and then selectively patterned to form a bit line 27. Next, a second insulating film 28 is formed on the entire surface of the first insulating film 25 including the bit line 27.

As shown in FIG. 2D, the first and second insulating layers 25 and 28 are selectively patterned so as to expose the high concentration impurity region 23b on the other side of the gate electrode 22 to form a node contact hole 29. . Next, a semiconductor layer plug 30 is formed in the node contact hole 29. In this case, the semiconductor layer plug 30 is formed using polysilicon or amorphous silicon using a chemical vapor deposition (CVD) method, and is formed lower than the upper surface of the second insulating layer 28. As the CVD method, a low pressure chemical vapor deposition method is used.

As shown in FIG. 2E, a barrier metal layer 31, a lower electrode 32, and a photoresist film PR are sequentially formed on the second insulating film 28 including the semiconductor layer plug 30, and then exposed and developed. The photoresist film PR is patterned so that only the capacitor region remains. In this case, the lower electrode 32 is formed using an oxidation resistant material such as platinum, and the barrier metal layer 31 is formed of TaSiN. At this time, the method of forming TaSiN is tantalum (Ta) and silicon (Si) at a different power (250w for Ta, 170w for Si) in a co- atmosphere of Ar / N ₂ mixed gas atmosphere- It is formed by using a reactive sputtering method using a sputtering (co-sputterring) method. In particular, when the composition of nitrogen (N) in the composition of TaxSiyNz is formed in the range of 30 to 43% of x + y + z, the sheet resistance of the barrier metal layer 31 does not increase and thermal stability can be ensured up to 800 ° C. have.

As shown in FIG. 2F, the lower electrode 32 and the barrier metal layer 31 are selectively removed by an etching process using the patterned photoresist film PR as a mask. Then, the photoresist film PR is removed.

As shown in FIG. 2G, the high dielectric film 33 and the upper electrode 34 are sequentially formed on the entire surface including the lower electrode 32 and the barrier metal layer 31 to complete the semiconductor memory device of the present invention. In this case, the high-k dielectric layer is formed to have a thickness of 400 to 600 kPa by using a material having a high dielectric constant such as BST or the like by a metal oxide chemical vapor deposition (MOCVD) method or a sputtering method. In this case, since the barrier metal layer 31 is formed of TaSiN having excellent thermal stability (surface resistance or diffusion preventing ability after high temperature heat treatment), the high dielectric film can be formed at a temperature of about 700 ° C. or higher, thereby ensuring the highest dielectric constant of the high dielectric film. .

3 is a graph showing the temperature dependence of the sheet resistance with temperature in the junction structure between the barrier metal layer and the polysilicon according to the present invention, as shown in the conventional case, the barrier metal worm was formed of any one of TiN, TiW or TaN. In the case of the temperature above 600 ℃ it can be seen that the surface resistance rapidly increases more than 100Ω. That is, since the temperature for excellent flatness during the wiring process is 800 ° C. or higher and the temperature for obtaining high dielectric effect during high dielectric film deposition is 700 ° C. or higher, it is difficult to obtain good characteristics as a memory device, as in the case of the present invention. When TaSiN is used as the metal layer, heat treatment may be performed at 700 ° C. or higher, thereby forming a dielectric film having high dielectric properties. In particular, when the TaSiN composition is set to Ta ₄₈ Si ₉ N ₄₃ , it can be seen that the sheet resistance hardly increases in the bonding structure between the barrier metal layer and polysilicon.

The manufacturing method of the semiconductor memory device according to the present invention has the following effects.

First, since a stable state can be maintained even at a high temperature of the diffusion barrier of the lower electrode without changing properties, the formation of a high-k dielectric material can proceed at a high temperature, thereby providing a semiconductor memory device having excellent electrical characteristics (leakage current, dielectric constant). .

Second, since the high temperature process is possible in the wiring process after the capacitor formation, it is possible to provide a semiconductor memory device which is advantageous for the planarization process after wiring.

Claims (8)

Forming an insulating film on the semiconductor substrate; Selectively patterning the insulating layer to form a node contact hole; Forming a semiconductor layer plug on an entire surface of the insulating layer including the node contact hole; Sequentially forming a TaSiN layer and a lower electrode on an entire surface of the insulating film including the semiconductor layer plug; Patterning the lower electrode and the TaSiN layer so that only the capacitor region remains; Forming a high dielectric film on surfaces of the TaSiN layer and the lower electrode; And forming an upper electrode on the entire surface of the high-k dielectric layer. The method of claim 1, wherein the semiconductor layer is formed using any one of polysilicon and amorphous silicon. The method of claim 1, wherein the TaSiN layer is a barrier metal layer for preventing diffusion of oxygen ions. The method of claim 3, wherein the TaSiN layer is formed by a reactive sputtering method. The method of manufacturing a semiconductor memory device according to claim 4, wherein the reactive sputtering method uses a co-sputtering method. The method of claim 3, wherein the TaSiN layer forms Ta and Si at different powers, in a mixed gas atmosphere of Ar / N ₂ . The method of manufacturing a semiconductor memory device according to claim 6, wherein the composition z of N is formed in the range of 30 to 43% of x + y + z when the composition of the TaSiN layer is called TaxSiyNz. The method of claim 1, wherein the semiconductor layer plug is formed lower than an upper surface of the insulating layer.