KR20020049804A - Method for forming a metal layer of a semiconductor device - Google Patents
Method for forming a metal layer of a semiconductor device Download PDFInfo
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- KR20020049804A KR20020049804A KR1020000079095A KR20000079095A KR20020049804A KR 20020049804 A KR20020049804 A KR 20020049804A KR 1020000079095 A KR1020000079095 A KR 1020000079095A KR 20000079095 A KR20000079095 A KR 20000079095A KR 20020049804 A KR20020049804 A KR 20020049804A
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- 238000000034 method Methods 0.000 title claims abstract description 24
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 239000002184 metal Substances 0.000 title claims description 6
- 229910052751 metal Inorganic materials 0.000 title claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 28
- 239000010949 copper Substances 0.000 claims abstract description 26
- 229910052802 copper Inorganic materials 0.000 claims abstract description 26
- 230000004888 barrier function Effects 0.000 claims abstract description 17
- 238000009792 diffusion process Methods 0.000 claims abstract description 17
- 230000009977 dual effect Effects 0.000 claims abstract description 10
- 239000000463 material Substances 0.000 claims abstract description 4
- 238000000151 deposition Methods 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 5
- 238000001312 dry etching Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000001771 vacuum deposition Methods 0.000 claims 1
- 235000017166 Bambusa arundinacea Nutrition 0.000 abstract description 5
- 235000017491 Bambusa tulda Nutrition 0.000 abstract description 5
- 241001330002 Bambuseae Species 0.000 abstract description 5
- 235000015334 Phyllostachys viridis Nutrition 0.000 abstract description 5
- 239000011425 bamboo Substances 0.000 abstract description 5
- 239000007769 metal material Substances 0.000 abstract description 4
- 238000001962 electrophoresis Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 238000007517 polishing process Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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Abstract
Description
본 발명은 반도체 디바이스의 배선 형성 방법에 관한 것으로서, 보다 상세하게는 이중 상감(Dual damascene) 구조의 메탈 배선을 형성하는 과정에 메탈 배선을 형성하기 위하여 증착되는 시드 막질의 측벽 또는 보텀을 제거하여 메탈의 성장이 일방향으로 진행되도록 하여 메탈 배선의 신뢰성을 개선시킨 반도체 디바이스의 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a wiring of a semiconductor device, and more particularly, by removing a sidewall or bottom of a seed film formed to form a metal wiring in the process of forming a metal wiring having a dual damascene structure. The present invention relates to a method for forming a wiring of a semiconductor device in which the growth of silicon oxide is performed in one direction, thereby improving the reliability of the metal wiring.
반도체 디바이스의 내부에는 전기적 동작을 위한 소자와 이들을 전기적으로결합시키기 위한 배선 등이 디자인되어 있으며, 배선은 금속 재질로 형성되고, 가장 일반적으로 구리가 이용된다.Inside the semiconductor device, elements for electrical operation and wiring for electrically coupling them are designed. The wiring is formed of a metal material, and copper is most commonly used.
또한, 배선의 효율성을 위하여 이중 상감 구조가 제시되어 널리 이용되고 있으며, 이중 상감 구조의 배선은 식각된 공간에 확산 방지막 증착, 시드 레이어 증착, 구리 채움 및 평탄화 과정이 수행되어 형성된다.In addition, a double inlay structure is proposed and widely used for wiring efficiency, and a double inlaid structure is formed by performing diffusion barrier film deposition, seed layer deposition, copper filling, and planarization processes in an etched space.
구체적으로, 도 1과 같이 기판(10)에 이중 상감 구조의 공간(12)이 형성되고, 여기에 도 2와 같이 확산 방지막(14)이 증착된다. 그리고, 도 3과 같이 확산 방지막(14)의 상부에는 일정한 두께의 구리 시드 레이어(16)가 증착되며, 그 후 나머지 공간에 구리가 배선(18) 형성을 위하여 채워지고, 일정한 두께를 제거하는 평탄화 공정이 수행되어 도 4의 구조를 갖는다.Specifically, as shown in FIG. 1, a space 12 having a double damascene structure is formed in the substrate 10, and the diffusion barrier film 14 is deposited as shown in FIG. 2. 3, a copper seed layer 16 having a predetermined thickness is deposited on the diffusion barrier 14, and then copper is filled in the remaining space to form the wiring 18, and planarization is performed to remove the constant thickness. The process is carried out to have the structure of FIG.
그러나, 도 1 내지 도 4의 수순으로 진행되는 배선 형성 방법에 의하면, 시드 레이어(16)가 형성된 후 구리 재질의 배선(18)이 형성되는 과정에서 측벽과 보텀(bottom) 지역 모두에서 증착이 발생되된다. 그 결과 그레인 사이즈(grain size)가 작아지고, 배선(18) 내에 전기영동 현상에 따른 수명 감소 요인으로 작용되는 그레인 바운더리(grain boundary)가 다수 형성된다.However, according to the wiring forming method proceeding according to the procedures of FIGS. 1 to 4, after the seed layer 16 is formed, deposition occurs in both the sidewall and the bottom region in the process of forming the copper wiring 18. do. As a result, the grain size is reduced, and a large number of grain boundaries are formed in the wiring 18, which act as a factor for reducing the lifetime of the electrophoresis phenomenon.
또한 측벽에서 구리의 성장이 일어나기 때문에 배선(18)은 구리의 뱀부(bamboo) 구조로 형성되기 어렵다.In addition, since the growth of copper occurs in the sidewalls, the wiring 18 is difficult to be formed of a copper (bamboo) structure.
따라서, 배선(18)의 전기영동 현상에 따른 수명의 신뢰성이 저하되는 문제점이 있다.Therefore, there is a problem that the reliability of the life due to the electrophoresis of the wiring 18 is lowered.
본 발명의 목적은 듀얼 상감 구조에서 시드 레이어를 측벽 또는 보텀에 제한하여 형성시켜서 금속을 증착시켜서 배선을 형성하여 증착이 일방향으로 이루어지도록 하여 전기영동 현상에 따른 배선의 신뢰성을 개선시킴에 있다.An object of the present invention is to improve the reliability of the wiring according to the electrophoresis phenomenon by forming a wiring by forming a wiring by depositing a metal by forming a limited seed layer on the sidewall or bottom in a dual damascene structure.
도 1 내지 도 4는 종래의 반도체 디바이스의 배선 형성 방법을 설명하는 공정도1 to 4 are process charts illustrating a wiring forming method of a conventional semiconductor device.
도 5 내지 도 9는 본 발명에 따른 반도체 디바이스의 배선 형성 방법의 제 1 실시예를 나타내는 공정도5 to 9 are process diagrams showing a first embodiment of a method for forming a wiring of a semiconductor device according to the present invention.
도 10 내지 도 14는 본 발명에 따른 반도체 디바이스의 배선 형성 방법의 제 2 실시예를 나타내는 공정도10 to 14 are process charts illustrating a second embodiment of the method for forming wirings of a semiconductor device according to the present invention.
본 발명에 따른 반도체 디바이스의 배선 형성 방법은, 기판 상의 듀얼 상감 구조로 식각된 영역에 금속 재질의 배선을 형성하며, 식각된 영역의 보텀과 측벽에 확산 방지막을 증착하는 단계; 확산 방지막 상에 구리 재질의 시드 레이어를 증착하는 단계; 시드 레이어의 측벽을 제거하는 단계; 식각된 영역 내에 잔류된 시드 레이어를 일방향으로 성장시켜서 상기 영역을 구리 재질로 채우는 단계; 및 상기 영역에 형성된 배선을 평탄화하는 단계로 이루어진다.In accordance with another aspect of the present invention, there is provided a method of forming a wiring of a semiconductor device, the method including: forming a wiring of a metal material on a region etched with a dual damascene structure on a substrate, and depositing a diffusion barrier on the bottom and sidewalls of the etched region; Depositing a copper seed layer on the diffusion barrier layer; Removing sidewalls of the seed layer; Growing the seed layer remaining in the etched region in one direction to fill the region with a copper material; And planarizing the wiring formed in the region.
이때 상기 시드 레이어는 습식식각으로 측벽이 제거되고 상기 영역에서 구리가 상부로 성장되거나, 또는 상기 시드 레이어는 건식식각으로 보텀이 제거되고 상기 영역에서 구리가 측방향으로 성장됨이 바람직하다.In this case, the seed layer may be wet-etched and sidewalls may be removed and copper may be grown upward in the region, or the seed layer may be bottom removed by dry etching and copper may be laterally grown in the region.
이하, 본 발명에 따른 실시예에 대하여 첨부 도면을 참조하여 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
본 발명은 듀얼 상감 구조를 갖는 금속 재질의 배선이 전기영동 현상에 대한 신뢰성을 가질수 있도록 공정을 개선시킨 것이다.The present invention is to improve the process so that the wiring of the metal material having a dual damascene structure can be reliable for the electrophoresis phenomenon.
본 발명은 시드 레이어를 보텀에만 형성하는 제 1 실시예와 시드 레이어를 측벽에만 형성하는 제 2 실시예로 갖는다.The present invention has a first embodiment in which the seed layer is formed only at the bottom and a second embodiment in which the seed layer is formed only at the sidewalls.
시드 레이어를 보텀에만 형성하는 제 1 실시예는 도 5 내지 도 9의 순으로이루어지며, 이를 참조하여 설명한다.A first embodiment in which the seed layer is formed only at the bottom is made in the order of FIGS. 5 to 9, and will be described with reference to this.
먼저, 도 5과 같이 듀얼 상감 구조로 기판(20)에 배선을 위한 공간(22)이 식각되어 형성된다.First, as shown in FIG. 5, a space 22 for wiring is etched and formed on the substrate 20 in a dual damascene structure.
그 후 도 6와 같이 배선을 위한 공간(22)에는 확산 방지막(24)이 증착되고, 그에 따라서 확산 방지막(24)은 측벽과 보텀에 각각 형성된다.Thereafter, as shown in FIG. 6, the diffusion barrier 24 is deposited in the space 22 for the wiring, and thus the diffusion barrier 24 is formed on the sidewall and the bottom, respectively.
그리고, 확산 방지막(24)의 상부에 도 7과 같이 구리 재질의 시드 레이어(26)가 플라즈마 증착 방법으로 증착되며, 그 후 도 8와 같이 시드 레이어(26)는 습식 식각에 의하여 식각이 진행되어서 측벽이 제거된다.Then, as shown in FIG. 7, the copper seed layer 26 is deposited on the diffusion barrier layer 24 by a plasma deposition method. Then, as shown in FIG. 8, the seed layer 26 is etched by wet etching. Sidewalls are removed.
시드 레이어(26)은 증착 공정과 배선을 위한 공간(22)의 구조적 특성상 측벽보다 보텀에 두꺼운 두께로 형성되며, 측벽의 시드 레이어(26)가 식각되어 확산방지막(24)의 측벽으로 드라나는 시점을 식각종료점으로 설정하여 습식 시각이 진행된다. 이 경우 등방성 식각이 해당된다.The seed layer 26 is formed to have a thickness thicker than the sidewall due to the structural characteristics of the space 22 for the deposition process and the wiring, and the seed layer 26 of the sidewall is etched to emerge to the sidewall of the diffusion barrier 24. Wet time is set by setting as the end point of etching. In this case, isotropic etching is applicable.
이와 같이 측벽의 시드 레이어(26)가 제거된 후 구리 재질의 시드 레이어(26) 상에만 선택적으로 구리를 성장시켜서 배선을 위한 공간(22)을 채운 후 화학적 물리적 폴리싱 공정을 수행하여 평탄화시키면 도 9와 같이 배선이 완성된다.After the side layer seed layer 26 is removed as described above, the copper layer is selectively grown on the copper seed layer 26 to fill the space 22 for wiring, and then the chemical physical polishing process is performed to planarize it. Wiring is completed as follows.
이때 구리 재질의 배선은 상부 방향으로 성장되므로 큰 그레인 사이즈와 작은 그레인 바운더리를 갖는다. 또한 뱀부 구조를 가짐으로써 전기 영동 현상에 대한 우수한 특성을 갖는다.At this time, since the copper wire is grown in the upper direction, it has a large grain size and a small grain boundary. In addition, having a bamboo structure has excellent properties for the electrophoresis phenomenon.
또한, 시드 레이어를 측벽에만 형성하는 제 2 실시예는 도 10 내지 도 14의순으로 이루어지며, 이를 참조하여 설명한다.In addition, the second embodiment in which the seed layer is formed only on the sidewall is made in the order of FIGS. 10 to 14, which will be described with reference to this.
먼저, 도 10과 같이 듀얼 상감 구조로 기판(30)에 배선을 위한 공간(32)이 식각되어 형성된다.First, as shown in FIG. 10, a space 32 for wiring is etched on the substrate 30 in a dual damascene structure.
그 후 도 11와 같이 배선을 위한 공간(32)에는 확산 방지막(34)이 증착되고, 그에 따라서 확산 방지막(34)은 측벽과 보텀에 각각 형성된다.Thereafter, as shown in FIG. 11, the diffusion barrier 34 is deposited in the space 32 for wiring, and thus the diffusion barrier 34 is formed on the sidewall and the bottom, respectively.
그리고, 확산 방지막(34)의 상부에 도 12와 같이 구리 재질의 시드 레이어(36)가 플라즈마 증착 방법으로 증착되며, 그 후 도 13와 같이 시드 레이어(36)는 건식 식각에 의하여 식각이 진행되어서 보텀이 제거된다.Then, as shown in FIG. 12, the copper seed layer 36 is deposited on the diffusion barrier layer 34 by a plasma deposition method, and as shown in FIG. 13, the seed layer 36 is etched by dry etching. The bottom is removed.
시드 레이어(26)는 배선을 위한 공간(22)의 구조적 특성상 건식식각에 의하여 보텀 부분이가 식각되며, 보텀의 확산방지막(24)이 드라나는 시점을 식각종료점으로 설정하여 건식 시각이 진행된다. 이 경우 방향성 식각이 해당된다.In the seed layer 26, the bottom portion is etched by dry etching due to the structural characteristics of the space 22 for the wiring, and the dry time is performed by setting a time point at which the bottom diffusion barrier 24 emerges as the etching end point. In this case, directional etching is applicable.
이와 같이 보텀의 시드 레이어(26)가 제거된 후 구리 재질의 시드 레이어(26) 상에만 선택적으로 구리를 성장시켜서 배선을 위한 공간(22)을 채운 후 화학적 물리적 폴리싱 공정을 수행하여 평탄화시키면 도 14와 같이 배선이 완성된다.After the bottom seed layer 26 is removed as described above, the copper is selectively grown on the copper seed layer 26 to fill the space 22 for wiring, and then the chemical physical polishing process is performed to planarize it. Wiring is completed as follows.
이때 구리 재질의 배선은 측 방향으로 성장되므로 제 1 실시예와 같이 큰 그레인 사이즈와 작은 그레인 바운더리를 갖는다. 또한 뱀부 구조를 가짐으로써 전기 영동 현상에 대한 우수한 특성을 갖는다.At this time, since the copper wire is grown in the lateral direction, it has a large grain size and a small grain boundary as in the first embodiment. In addition, having a bamboo structure has excellent properties for the electrophoresis phenomenon.
따라서, 본 발명에 의하면 듀얼 상감 구조의 배선을 형성할 때 배선 영역 내부에 채워지는 구리를 일방향으로 성장시켜서 배선이 큰 그레인 사이즈와 작은 그레인 바운더리를 갖고 뱀부 구조를 가짐으로써 전기영동 현상에 대한 특성이 극대화되는 효과가 있다.Therefore, according to the present invention, when the wiring having the dual damascene structure is formed, the copper filled inside the wiring region is grown in one direction so that the wiring has a large grain size and a small grain boundary and has a bamboo structure, so that the characteristics of the electrophoretic phenomenon are improved. There is an effect that is maximized.
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