KR20020049684A - Method for fabricating gate of flash semiconductor device - Google Patents
Method for fabricating gate of flash semiconductor device Download PDFInfo
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- KR20020049684A KR20020049684A KR1020000078907A KR20000078907A KR20020049684A KR 20020049684 A KR20020049684 A KR 20020049684A KR 1020000078907 A KR1020000078907 A KR 1020000078907A KR 20000078907 A KR20000078907 A KR 20000078907A KR 20020049684 A KR20020049684 A KR 20020049684A
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- gate
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- polysilicon
- floating gate
- control gate
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 31
- 229920005591 polysilicon Polymers 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 229910008486 TiSix Inorganic materials 0.000 claims abstract description 8
- 238000009413 insulation Methods 0.000 claims abstract description 4
- 238000000151 deposition Methods 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 4
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Inorganic Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 플래쉬 반도체소자의 게이트 형성방법에 관한 것으로, 특히 플래쉬 반도체소자의 제어게이트와 부유게이트 형성후 Ti를 이용한 살리사이드(salicide)를 형성하여 Rs(Sheet resistance)를 개선하여 플래쉬 소자의 특성을 개선할 수 있도록 한 플래쉬 소자의 게이트 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a gate of a flash semiconductor device. In particular, after forming a control gate and a floating gate of a flash semiconductor device, a salicide using Ti is formed to improve Rs (Sheet resistance) to improve characteristics of the flash device. It relates to a method of forming a gate of a flash device to be improved.
현재 플래쉬 소자인 0.20㎛ 이상에서의 제어게이트는 WSix를 이용한 폴리사이드를 사용하고 있는데 소자의 집적도가 증가할수록 하지층인 폴리실리콘과의 간격이 감소하거나 폴리실리콘의 두께가 증가하여 단차가 심해질수록 WSix는 폴리실리콘 사이에서 갈라진 틈(seam)(도1의 S참조)이 발생하여 Rs의 감소를 유발한다. 이는 WSix의 축성장(columna) 특성에 기인한 것으로, 셀내의 좁은 공간에서 갈라진 틈의 발생을 유발시켜 제어게이트의 Rs를 증가시킴으로써 플래쉬 소자의 특성을 저하시킨다.Currently, the control gate at the flash device of 0.20㎛ or more uses polysilicon using WSix, and as the integration degree of the device increases, the gap with the underlying polysilicon decreases or the thickness of the polysilicon increases. Is a crack (see S in Fig. 1) between the polysilicon causes a decrease in Rs. This is due to the columnar characteristics of WSix, which causes cracks in narrow spaces in the cell, thereby increasing the Rs of the control gate, thereby degrading the flash device characteristics.
본 발명은 상기 문제점을 해결하기 위한 것으로써, 고집적 플래쉬 소자에서 기존의 WSix를 사용한 폴리사이드의 Rs를 개선하기 위하여 TiSix를 형성하는 방법으로서 제어게이트를 스텝커버리지가 양호한 폴리실리콘을 사용하여 증착, 패터닝하고, Ti를 사용한 살리사이드(Salicide;Self Aligned Silicide)공정을 제어게이트와 함께 부유게이트인 폴리실리콘에 동시에 적용하여 Rs특성이 우수한 TiSix계열을 형성함으로써 WSix의 단차에 의한 제약을 극복하고 WSix보다 나은 TiSix의 Rs를 확보하여 소자특성을 향상시킬 수 있도록 하는 플래쉬 소자의 게이트 형성방법을 제공하는데 목적이 있다.The present invention is to solve the above problems, as a method of forming TiSix to improve the Rs of the polyside using the conventional WSix in a highly integrated flash device, the control gate is deposited and patterned using polysilicon having good step coverage In addition, the Salicide process using Ti is applied to polysilicon, which is a floating gate, together with the control gate to form a TiSix series with excellent Rs characteristics, thereby overcoming the limitations caused by the WSix step, It is an object of the present invention to provide a method for forming a gate of a flash device which can secure device characteristics by securing Rs of TiSix.
도1은 기존의 WSix를 사용한 플래쉬소자의 제어게이트의 문제점을 도시한 도면.1 is a view showing a problem of a control gate of a flash device using a conventional WSix.
도2는 본 발명에 의한 플래쉬 소자의 셀 내부의 레이아웃을 도시한 평면도로서, 부유게이트를 식각하여 형성한 후의 상태를 나타낸 도면.Fig. 2 is a plan view showing the layout of a cell interior of a flash device according to the present invention, showing a state after the floating gate is formed by etching.
도3은 활성영역상의 부유게이트용 폴리실리콘을 제거한 후의 상태를 나타낸 평면도.3 is a plan view showing the state after removing the floating gate polysilicon on the active region.
도4 내지 도7은 본 발명에 의한 플래쉬소자의 게이트 형성방법을 도시한 공정순서도로서 도4, 도6 및 도7은 도3의 X방향의 단면도, 도5는 도3의 Y방향의 단면도.4 to 7 are process flow charts illustrating a method for forming a gate of a flash device according to the present invention. FIGS. 4, 6 and 7 are sectional views in the X direction of FIG. 3, and FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 활성영역 2 : 필드산화막1: active area 2: field oxide film
5 : 부유게이트(제1폴리실리콘층) 6 : ONO막5: floating gate (first polysilicon layer) 6: ONO film
7 : 제2폴리실리콘층 8 : 하드마스크7: second polysilicon layer 8: hard mask
9 : Ti 10 :TiSix9: Ti 10: TiSix
상기 목적을 달성하기 위한 본 발명은, 플래쉬 반도체소자의 게이트 형성방법에 있어서, 기판상에 제1폴리실리콘을 증착하고 패터닝하여 부유게이트를 형성하는 단계와; 상기 부유게이트상에 이 부유게이트와 후에 형성될 제어게이트 사이의 절연을 위하여 절연막을 형성하는 단계; 기판 전면에 제2폴리실리콘을 증착하는 단계; 상기 제2폴리실리콘층상에 하드마스크층을 형성하는 단계; 상기 하드마스크층과 제2폴리실리콘을 소정의 제어게이트패턴으로 패터닝하는 단계; SAE를 통해 최종적인 부유게이트를 형성하는 단계; 및 Ti를 기판 전면에 증착하고 열처리하여 TiSix를 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a gate of a flash semiconductor device, the method comprising: forming a floating gate by depositing and patterning a first polysilicon on a substrate; Forming an insulating film on the floating gate for insulation between the floating gate and a control gate to be formed later; Depositing a second polysilicon over the substrate; Forming a hard mask layer on the second polysilicon layer; Patterning the hard mask layer and the second polysilicon into a predetermined control gate pattern; Forming a final floating gate through SAE; And depositing Ti on the entire surface of the substrate and performing heat treatment to form TiSix.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
도2는 플래쉬 소자의 셀 내부의 레이아웃을 도시한 평면도로서, 부유게이트(5)를 식각하여 형성한 후의 상태를 나타낸 것이고, 도3은 활성영역(1)상의 부유게이트용 폴리실리콘을 제거한 후의 상태를 나타낸 평면도이다. 그리고 도4 내지 도7은 본 발명에 의한 플래쉬소자의 게이트 형성방법을 도시한 공정순서도로서 도4, 도6 및 도7은 도3의 X방향의 단면도이고, 도5는 도3의 Y방향의 단면도이다. 이하, 도2 내지 도7을 참조하여 본 발명의 플래쉬소자의 게이트 형성방법을 설명한다.FIG. 2 is a plan view showing the layout of the interior of the cell of the flash device, showing the state after the floating gate 5 is etched and formed, and FIG. 3 after removing the floating gate polysilicon on the active region 1; It is a top view which shows. 4 to 7 are process flowcharts illustrating a method of forming a gate of a flash device according to the present invention. FIGS. 4, 6 and 7 are cross-sectional views in the X direction of FIG. 3, and FIG. It is a cross section. Hereinafter, the gate forming method of the flash device of the present invention will be described with reference to FIGS.
먼저, 기판 소정영역에 필드산화막(2)을 형성한 후, 터널산화막을 형성하기 위한 산화공정을 진행한 다음, 부유게이트로 사용할 제1폴리실리콘(5)을 300-1000Å 증착하고 패터닝하여 부유게이트(도5의 참조부호5 참조)를 형성한다.First, after the field oxide film 2 is formed in a predetermined region of the substrate, an oxidation process for forming the tunnel oxide film is performed. Then, the first polysilicon 5 to be used as the floating gate is deposited and patterned by 300-1000 kPa. (See 5 in Fig. 5) is formed.
이어서 부유게이트와 후에 형성될 제어게이트 사이의 절연을 위하여 ONO(oxide/nitride/oxide)(6)를 순차적으로 증착한다. 다음에 제어게이트 형성을 위해 스텝커버리지가 좋은 제2폴리실리콘(7)을 300-2000Å 증착한다.Subsequently, ONO (oxide / nitride / oxide) 6 is sequentially deposited for insulation between the floating gate and the control gate to be formed later. Next, a second step of polysilicon 7 having good step coverage is deposited to form a control gate at 300-2000 microseconds.
다음에 SAC(self aligned contact)등의 후속공정을 위한 하드마스크 물질(8)로서 예컨대 절연막, Si3N4, SiON, Low-k, SOG등을 기판전면에 400-3000Å 증착한다. 이어서 제어게이트를 형성하기 위하여 도4에 나타낸 바와 같이 상기 하드마스크(8)와 제2폴리실리콘(7)을 패터닝하다.Next, for example, an insulating film, Si 3 N 4, SiON, Low-k, SOG, or the like is deposited on the entire surface of the substrate as a hard mask material 8 for a subsequent process such as self aligned contact (SAC). Subsequently, the hard mask 8 and the second polysilicon 7 are patterned as shown in FIG. 4 to form a control gate.
이어서 SAE(self aligned etch)를 통해 활성영역(1)상의 제1폴리실리콘을 제거한다. 다음에 Ti(9)를 Si과의 반응비(Si:Ti≒2:1)를 고려하여 200Å 미만의 두께로 기판 전면에 증착한 후, 열공정을 통해 TiSix(10)를 형성한다.Subsequently, the first polysilicon on the active region 1 is removed through a self aligned etch (SAE). Next, Ti (9) is deposited on the entire surface of the substrate with a thickness of less than 200 GPa in consideration of the reaction ratio with Si (Si: Ti ≒ 2: 1), and then TiSix (10) is formed through a thermal process.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
본 발명은 플래쉬소자의 부유게이트와 제어게이트의 형성에 있어서 기존의 부유게이트는 폴리실리콘을 사용하고 제어게이트는 WSix를 사용하여 형성하는 방법 대신에 제어게이트도 폴리실리콘을 사용하여 형성한 후 Ti살리사이드를 형성함으로써 Rs를 확보하여 소자특성을 향상시킬 수 있다.In the present invention, in the formation of the floating gate and the control gate of the flash device, the conventional floating gate is made of polysilicon and the control gate is formed using polysilicon instead of the method of forming the control gate using WSix Ti salis By forming the side, Rs can be secured to improve the device characteristics.
Claims (6)
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| KR100390913B1 (en) * | 2001-06-28 | 2003-07-12 | 주식회사 하이닉스반도체 | Process for forming gate of flash mamory device |
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| JP3496723B2 (en) * | 1993-04-02 | 2004-02-16 | シャープ株式会社 | Method for manufacturing semiconductor device |
| JP3450539B2 (en) * | 1995-08-17 | 2003-09-29 | 株式会社東芝 | Manufacturing method of nonvolatile semiconductor memory device |
| JPH11163335A (en) * | 1997-11-28 | 1999-06-18 | Sharp Corp | Semiconductor device and its manufacture |
| JP3425887B2 (en) * | 1999-03-23 | 2003-07-14 | Ｎｅｃエレクトロニクス株式会社 | Semiconductor memory device and method of manufacturing the same |
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