KR20020048502A - Double Switch Board and A method of switch board redundancy - Google Patents

Abstract

PURPOSE: A duplex switch board and a duplexing method are provided to decrease a power consumption being generated in a non-activated switch board by minimizing a system clock being supplied in the non-activated switch board using a system clock control unit in each dual switch board. CONSTITUTION: I/O bus interface units, switch units, control units, and system clock control units are connected to an I/O bus. Processor interface units are connected to a processor bus. The system clock control unit includes the below elements. A control status sensing unit(310) senses a status of a control unit and creates a value corresponded to a switch mode. An external processor status sensing unit(320) checks a status of an external processor and creates a value corresponded to the switch mode. A system clock unit(340) creates a clock in accordance with the value created through the control status sensing unit(310) and the external processor status sensing unit(320). A system clock control device(330) controls the clock of a switch board independently using values received from the control status sensing unit(310) and the external processor status sensing unit(320) and the clock received from the system clock unit(340).

Description

Double Switch Board and A method of switch board redundancy}

The present invention relates to a dual switch board and a redundancy method that can reduce power consumption to a minimum, and more specifically, to a dual switch board and a redundancy method that can reduce a power consumption in an inactive switch board to a minimum. will be.

1 is a configuration diagram of a dual switch board according to the prior art. As illustrated, the dual switch boards 110 and 120 interconnected with the input / output 150 and the processor bus 160 may include the input / output bus interfaces 111 and 112, the controllers 112 and 122, and the switch unit 113. 123, the processor interfaces 114 and 124, and each switch board 110 and 120 are interconnected through a redundant data bus 130 and a redundant control bus 140.

Such a dual switch board is a redundant switch board, one of the active switch board to support the switching function and the other has the structure of the inactive switch board, when the active switch board failure, input into the inactive switch board Perform a path transformation of the data. This minimizes data loss even if one board fails, minimizing system stability and data loss.

However, since the system clock of such a redundant board is supplied to both dual switch boards, the same amount of power is consumed by the active and inactive switch boards. Double the power consumption.

An object of the present invention for solving the above problems of the prior art is to use the system clock control in each of the dual switch board, by minimizing the system clock supplied to the inactive switch board, the power generated in the inactive switch board The purpose of the present invention is to provide a dual switch board and a redundant method that can minimize the consumption.

1 is a configuration diagram of a dual switch board according to the prior art,

2 is a configuration diagram of a dual switch board according to an embodiment of the present invention;

3 is a configuration diagram of a system clock control unit used in the dual switch board shown in FIG.

4 is a flowchart illustrating an operation process of a system clock controller used in the dual switch board shown in FIG.

FIG. 5 is a waveform diagram of a clock generated by a system clock controller used in the dual switch board shown in FIG. 2.

※ Explanation of code about main part of drawing ※

210, 220: switch boards 211, 221: I / O bus interface

212, 222 control unit

213, 223: system clock control unit 214, 224: switch unit

215, 225: processor interface 250: I / O bus

260: processor bus

An object of the present invention for achieving the above object is to operate to reduce the power consumption to a minimum, includes the same two switch board, according to the provided control unit and the external processor status monitoring unit, one of the switch board Is in an active mode, the other switch board is a dual switch board configured to be in an inactive mode, each switch board including a system clock control, wherein the system clock control is configured to clock the system clock when the switch board is in the active mode. And does not generate a system clock when the switchboard is in inactive mode.

Preferably, it operates to reduce power consumption to a minimum, and includes two identical switch boards, and if one switch board is in active mode, the other switch board is in a dual switch board configured to be in inactive mode. In the system clock controller, if the switch board is in the active mode, a system clock is generated and provided to the switch board. If the switch board is in the inactive mode, the system clock is not generated.

More preferably, it operates to reduce power consumption to a minimum, includes two identical switch boards, and according to the provided external processor status monitor, if one switch board is in the active mode, the other switch board A redundancy method of a dual switch board configured to be in an inactive mode, comprising: a first step of generating a system clock for the one switch board if the one switch board is in the active mode; If the one switch board is in the inactive mode, controlling a system clock of the dual switch board; And a third step of controlling a system clock of the dual switch board by inspecting a state of the one switch board according to whether the other switch board has failed.

Hereinafter, a dual switch board and a duplication method according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. 2 is a configuration diagram of a dual switch board according to an embodiment of the present invention, and further includes a system clock control unit as compared with the related art.

The switch boards 210 and 220 may include an I / O bus interface 211 and 221 interconnected to the I / O bus 250, a switch unit 214 and 224, a control unit 212 and 222, and a system clock control unit ( 213 and 223 and processor interfaces 215 and 225 interconnected with processor bus 260. In addition, each switch board 210, 220 is interconnected via a redundant data bus 230 and a redundant control bus 240.

The operation process of the dual switch board configured as described above is as follows. First, when power is applied or initialized to each of the dual switch boards 210 and 220, the controllers 212 and 222 in each switch board 210 and 220 examine the state of the magnetic switch board and the state of the counterpart switch board, and then the redundant data bus ( 230 and interchange via redundant control bus 240. After the exchange, when the states of the two switch boards 210 and 220 are normal, they are defined as active switch boards and inactive switch boards in order of priority. Thereafter, the system clock controller 213 or 223 of the board defined as the inactive switch board receives the state of its own and the partner board from the controller 212 or 222 and controls the system clock. In control, if the other board is in active mode and the external processor is not setting or checking the magnetic board, the system clock can be turned off to reduce the power consumed by the chip in the inactive switch board.

Here, a detailed description of the system clock controller used in the dual switch board including such a feature is as follows. 3 is a block diagram of a system clock control unit used in the dual switch board according to the present invention.

As illustrated, the system clock controller 300 includes a controller state monitor 310, an external processor state monitor 320, a system clock controller 330, and a system clock unit 340.

The controller state monitoring unit 310 checks which switch mode (active / inactive) the magnetic switch board is currently in, which can be known as a register value inside the controller. For example, if the register value inside the controller is 1, the active mode may be set, and if the register value is 0, the non-active mode may be set. The controller state monitor 310 transmits 1 to the system clock controller 330 in the active mode and 0 in the inactive mode. As such, the inactive switch board must maintain the same state setting as the current active switch board for normal redundancy. To this end, an external processor sends and receives data through the switch unit and the processor bus.

The external processor monitoring unit 320 checks whether an external processor is exchanging data with the switch unit in order to set a state to the switch unit or check the set state. That is, when a read signal or a write signal is generated from an external processor, 1 is transmitted to the system clock controller 330.

The system clock generator 320 receives these signals and the system clock to control the system clock. A controlled system clock is supplied to each dual switch board

An operation process of the system clock controller including such a feature will be described below. FIG. 4 is a flowchart illustrating an operation process of a system clock controller used in the dual switch board illustrated in FIG. 2.

First, when the system switch is set to the active switch board and the inactive switch board by priority, the system clock controller first checks whether the magnetic switch board is the active switch board by checking the register value of the controller (S410). If the check result, the active switch board, the system clock is generated (S420), while if the check result, the inactive switch board, first checks whether the failure occurs in the active switch board (S430). As a result of the inspection, if the failure occurs in the activity switch board, the magnetic board must be switched to the activity switch mode, so the state of the magnetic board is first checked (S440). As a result of the test, if the state of the magnetic board is abnormal, this is regarded as a system failure because both the inactive switch board and the active switch board have failed (S450), while if the state of the magnetic board is normal, to perform the redundancy function Switch to the active switch mode and generates a system clock (S460). On the other hand, if a failure does not occur in the activity switch board which is a counterpart board, the value of the external processor state monitoring unit is checked to determine whether the external processor has made a read / write request (S470). If the check indicates that there is a read / write request from the external processor (if the external processor status monitor value is 1), it generates a system clock, while if there is no read / write request from the external processor (the external processor status monitor value is 0) In step S480, the system clock is not generated.

5 is a clock waveform diagram generated by the system clock controller including such a feature. As shown, the system clock controller controls the system clock according to values of the controller state monitor and the external processor state monitor.

In section 51 and section 52, the switch board is active switch mode, so the system clock is generated regardless of the external processor. On the other hand, in section 53, although the corresponding switch board is in the inactive switch mode, the external processor exchanges data with the switch unit, thereby generating a system clock. Finally, interval 52 does not generate a system clock because the switch board is in inactive switch mode and requires no external processor.

While the invention has been described above based on the preferred embodiments thereof, these embodiments are intended to illustrate rather than limit the invention. It will be apparent to those skilled in the art that various changes, modifications, or adjustments to the above embodiments can be made without departing from the spirit of the invention. Therefore, the scope of protection of the present invention should not be limited only by the appended claims, but should be construed as including all such changes, modifications or adjustments.

As described above, according to the present invention, by using the system clock control unit in each switch board, not only can the system clock supplied to the inactive switch board be minimized, but also minimize the power generated in the inactive switch board. Therefore, there is an effect of implementing a stable system as a whole.

Claims (6)

Operated to reduce power consumption to a minimum, it includes two identical switch boards, and according to the provided control and external processor status monitor, if one switch board is in active mode, the other switch board is inactive A dual switch board configured to be in mode, each switch board comprising a system clock control, the system clock control generating a system clock when the switch board is in an active mode, and when the switch board is in an inactive mode Dual switch board, which does not generate a system clock. The method of claim 1, The system clock control unit, A controller state monitoring unit for monitoring a state of the controller and generating a value corresponding to the switch mode; An external processor state monitoring unit configured to inspect a state of an external processor and generate a value corresponding to the switch mode; A system clock unit configured to generate a clock according to a value generated by the controller state monitor and an external processor state monitor; The dual switch board comprising a system clock controller for independently controlling the clock of the switch board by using the value received from the controller state monitoring unit and the external processor state monitoring unit and the clock received from the system clock unit. . Operated to reduce power consumption to a minimum, and include two identical switch boards, one of which is in active mode, the other switch board to the system clock control in a dual switch board configured to be in inactive mode. The system clock control unit of claim 1, wherein the system clock is generated and provided to the switch board when the switch board is in the active mode, and the system clock is not generated when the switch board is in the inactive mode. Operated to reduce power consumption to a minimum, it includes two identical switch boards and, depending on the external processor status monitors provided, if one of the switch boards is in active mode, the other switch board is in inactive mode. In the redundant method of the dual switch board configured to A first step of generating a system clock for the one switch board if the switch board is in the active mode; If the one switch board is in the inactive mode, controlling a system clock of the dual switch board; And a third step of controlling a system clock of the dual switch board by checking a state of the one switch board according to whether the other switch board has failed. The method of claim 4, wherein The second step, A first sub-step of generating a clock of the dual switch board when the value generated by the external processor state monitoring unit is 1 (active mode); And generating a clock of the dual switch board if the value generated by the external processor state monitor is 0 (inactive mode). The method of claim 4, wherein The third step, A first sub step of generating a clock of the dual switch board when the switch board is in a normal state; And if the switch board is in an abnormal state, treating the dual switch board as a failure state.