KR20020046436A - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
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- KR20020046436A KR20020046436A KR1020000076631A KR20000076631A KR20020046436A KR 20020046436 A KR20020046436 A KR 20020046436A KR 1020000076631 A KR1020000076631 A KR 1020000076631A KR 20000076631 A KR20000076631 A KR 20000076631A KR 20020046436 A KR20020046436 A KR 20020046436A
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- semiconductor device
- manufacturing
- diffusion barrier
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- tin diffusion
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- 238000000034 method Methods 0.000 title claims abstract description 29
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000009792 diffusion process Methods 0.000 claims abstract description 32
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 31
- 230000004888 barrier function Effects 0.000 claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 claims abstract description 30
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 21
- 229920005591 polysilicon Polymers 0.000 claims abstract description 21
- 238000000151 deposition Methods 0.000 claims abstract description 9
- 238000004140 cleaning Methods 0.000 claims abstract description 6
- 239000007789 gas Substances 0.000 claims abstract description 6
- 239000003990 capacitor Substances 0.000 claims description 24
- 229910052751 metal Inorganic materials 0.000 claims description 20
- 239000002184 metal Substances 0.000 claims description 20
- 229910008484 TiSi Inorganic materials 0.000 claims description 19
- 238000005229 chemical vapour deposition Methods 0.000 claims description 10
- 238000010438 heat treatment Methods 0.000 claims description 6
- 239000012495 reaction gas Substances 0.000 claims description 6
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 238000005406 washing Methods 0.000 claims description 3
- 229910052741 iridium Inorganic materials 0.000 claims description 2
- 229910052697 platinum Inorganic materials 0.000 claims description 2
- 229910052707 ruthenium Inorganic materials 0.000 claims description 2
- 238000007669 thermal treatment Methods 0.000 claims 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 abstract description 5
- 229910008479 TiSi2 Inorganic materials 0.000 abstract 1
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 abstract 1
- 230000008021 deposition Effects 0.000 description 4
- 239000012212 insulator Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
본 발명은 반도체소자 제조 방법에 관한 것으로, 더욱 상세하게는 MIM(Metal Insulator Metal) 구조의 캐패시터 제조 방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a capacitor having a metal insulator metal (MIM) structure.
통상적으로 Ta2O5캐패시터의 하부전극은 RTN(Rapid Thermal Nitrization) 표면처리된 폴리실리콘을 사용하였다.Typically, the lower electrode of the Ta 2 O 5 capacitor used a polysilicon surface treatment of rapid thermal nitrization (RTN).
한편, 소자가 점차 고 집적화됨에 따라 안정된 소자동작을 위한 셀당 캐패시턴스는 변화가 없는 반면 캐패시터 셀 사이즈는 점점 줄어들게 되어 유효산화막의 두께가 30Å 정도인 폴리실리콘을 하부전극으로 하는 Ta2O5캐패시터 구조는 한계에 도달하게 되었다.On the other hand, as the device is increasingly integrated, the capacitance per cell for stable device operation does not change, but the capacitor cell size is gradually reduced, and the Ta 2 O 5 capacitor structure having polysilicon as the lower electrode having an effective oxide thickness of about 30Å is used. The limit has been reached.
이러한 문제를 해결하기 위해 하부메탈전극을 도입해 유효산화막 두께를 낮추는 방법이 시도되었다. 이러한 하부메탈전극의 도입은 플러그 물질인 폴리실리콘과 하부메탈전극의 열반응 방지를 위한 확산방지막 형성공정을 필요로 하게 된다.In order to solve this problem, a method of lowering the effective oxide thickness by introducing a lower metal electrode has been attempted. The introduction of the lower metal electrode requires a diffusion barrier forming process for preventing thermal reaction between the polysilicon as the plug material and the lower metal electrode.
그러나, 종래기술의 MIM 캐패시터 제조 공정에서는 확산방지막과 오믹콘택층사이의 잔류 산화물에 의한 계면 저항에 의해 하부전극의 콘택 저항이 증가하여 캐패시터의 전기적 특성을 열화시키는 문제가 발생하게 된다.However, in the prior art MIM capacitor manufacturing process, the contact resistance of the lower electrode is increased due to the interfacial resistance caused by the residual oxide between the diffusion barrier and the ohmic contact layer, resulting in a problem of deteriorating the electrical characteristics of the capacitor.
도 1a 내지 도 1d는 종래기술에 따른 MIM 구조 캐패시터의 제조 방법을 보인다.1A-1D show a method of manufacturing a MIM structure capacitor according to the prior art.
먼저 도 1a에 보이는 바와 같이, 전도층(11) 상의 절연막(12)을 선택적으로 에칭하여 콘택홀(10)을 형성한다.First, as shown in FIG. 1A, the insulating layer 12 on the conductive layer 11 is selectively etched to form the contact hole 10.
다음으로 도 1b에 도시된 것처럼 폴리실리콘 플러그(13)와 TiSi2오믹콘택층(14)의 적층구조를 형성하도록 한다. 여기서, 폴리실리콘 플러그(13)는 폴리실리콘을 증착한 후 리세스 에치 백(Recess etch back)공정을 실시하여 형성하며, TiSi2오믹콘택층(14)은 물리기상증착법(Physical Vapor Deposition; PVD)에 의해 Ti를 층착하고 RTP(Rapid Thermal Process) 또는 로에서의 열처리에 의해 상기 폴리실리콘 플러그(13)과 Ti를 열반응시켜 TiSi2오믹콘택층(14)을 형성한 다음, SC(Standard Cleaning)-1 용액을 이용하여 절연막(12) 상에 잔류하는 미 반응 Ti 및 산화물을 제거한 것이다.Next, as shown in FIG. 1B, a laminated structure of the polysilicon plug 13 and the TiSi 2 ohmic contact layer 14 is formed. Here, the polysilicon plug 13 is formed by depositing polysilicon and performing a recess etch back process, and the TiSi 2 ohmic contact layer 14 is formed of a physical vapor deposition (PVD). By depositing Ti and thermally reacting the polysilicon plug 13 and Ti by heat treatment in a rapid thermal process (RTP) or a furnace to form a TiSi 2 ohmic contact layer 14, followed by SC (Standard Cleaning) The unreacted Ti and oxide remaining on the insulating film 12 are removed by using the −1 solution.
다음으로 도 1c에 도시된 것처럼 TiSi2오믹콘택층(14) 상에 TiN 확산방지막(15)을 증착한 후 CMP(Chemical Mechanical Polishing) 공정을 통하여 콘택홀(10) 내부에만 TiN 확산방지막(15)을 형성한다.Next, as illustrated in FIG. 1C, the TiN diffusion barrier layer 15 is deposited on the TiSi 2 ohmic contact layer 14, and then the TiN diffusion barrier layer 15 is formed only inside the contact hole 10 through a chemical mechanical polishing (CMP) process. To form.
다음으로 도 1d에 도시된 바와 같이 상기 폴리실리콘 플러그(13), TiSi2 오믹콘택층(14), TiN 확산방지막(15)이 적층구조를 이룬 웨이퍼 상에 하부메탈전극(16)과 유전막(17) 및 상부메탈전극(18)을 증착하여 캐패시터를 형성한다.Next, as shown in FIG. 1D, the lower metal electrode 16 and the dielectric layer 17 are stacked on the wafer on which the polysilicon plug 13, the TiSi 2 ohmic contact layer 14, and the TiN diffusion barrier layer 15 are stacked. And the upper metal electrode 18 is deposited to form a capacitor.
전술한 바와 같이 이루어지는 종래 MIM 구조 캐패시터의 제조 방법은 다음과 같은 문제점이 있다.The manufacturing method of the conventional MIM structure capacitor made as described above has the following problems.
Ti 금속 증착과 TiSi2오믹콘택층(14)의 형성을 위한 열반응 공정 이후, 미 반응 Ti 및 산화물의 제거를 위해 세정공정을 수행해야 하므로 TiSi2오믹콘택층(14) 표면의 산화물이 완전히 제거되지 않는다.After the thermal reaction process for the deposition of Ti metal and the formation of the TiSi 2 ohmic contact layer 14, a cleaning process must be performed to remove unreacted Ti and oxides, so that oxides on the surface of the TiSi 2 ohmic contact layer 14 are completely removed. It doesn't work.
특히, TiSi2오믹콘택층(14)과 TiN 확산방지막(15) 계면(14a)에 형성된 상기 산화물은 하부메탈전극(도 1의 16)의 콘택 저항을 감소시키며, 심지어 TiSi2오믹콘택층(14)과 TiN 확산방지막(15)을 양 전극으로 하는 기생 캐패시터를 형성하게 하여 소자의 전기적 특성을 열화시킨다.In particular, the oxide formed at the TiSi 2 ohmic contact layer 14 and the TiN diffusion barrier 15 interface 14a reduces the contact resistance of the lower metal electrode (16 in FIG. 1), and even the TiSi 2 ohmic contact layer 14 ) And the TiN diffusion barrier film 15 are formed to form a parasitic capacitor to deteriorate the electrical characteristics of the device.
본 발명은 상기와 같은 종래 기술의 문제점을 해결하기 위한 것으로서, TiN 확산방지막과 TiSi2오믹콘택층의 계면 저항에 의한 하부전극의 콘택 저항을 감소시켜 전기적 특성을 개선시키는 반도체소자 제조 방법을 제공하는데 그 목적이 있다.The present invention is to solve the problems of the prior art as described above, to provide a semiconductor device manufacturing method for improving the electrical properties by reducing the contact resistance of the lower electrode due to the interfacial resistance of the TiN diffusion barrier and TiSi 2 ohmic contact layer. The purpose is.
도 1a 내지 도 1d는 종래기술에 따른 캐패시터의 제조 공정을 나타내는 단면도,1A to 1D are cross-sectional views illustrating a manufacturing process of a capacitor according to the prior art;
도 2a 내지 2e는 본 발명의 실시예에 따른 캐패시터의 제조 공정을 나타내는 단면도.2A to 2E are cross-sectional views illustrating a manufacturing process of a capacitor according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
10 : 콘택홀10: contact hole
11, 21 : 전도층11, 21: conductive layer
12, 22 : 절연막12, 22: insulating film
13, 23 : 폴리실리콘 플러그13, 23: polysilicon plug
14, 24 : TiSi2오믹콘택층14, 24: TiSi 2 ohmic contact layer
14a : TiSi2오믹콘택층과 TiN 확산방지막의 계면14a: Interface between TiSi 2 ohmic contact layer and TiN diffusion barrier
24a : Ti층24a: Ti layer
24b : 미반응 Ti와 잔류산화물24b: unreacted Ti and residual oxide
15, 25 : TiN 확산방지막15, 25: TiN diffusion barrier
16, 26 : 하부메탈전극16, 26: lower metal electrode
17, 27 : 유전막17, 27: dielectric film
18, 28 : 상부메탈전극18, 28: upper metal electrode
상기 목적을 달성하기 위하여 본 발명은 캐패시터의 제조 방법에 있어서, 전도층 상의 절연막을 선택적으로 식각하여 콘택홀을 형성하는 단계; 상기 콘택홀 내부에 리세스된 폴리실리콘 플러그를 형성하는 단계; 결과물 전면에 Ti를 증착하고 상기 폴리실리콘과 상기 Ti를 열반응시켜 TiSi2오믹콘택층을 형성하는 단계; 미반응 Ti를 세정하여 제거하는 단계; NH3가스를 포함하는 플라즈마 화학기상증착에 의해 TiN 확산방지막을 형성하면서 상기 세정 시 형성되는 산화물을 제거하는 단계; 상기 TiN 확산방지막 상부을 식각하여 웨이퍼를 평탄화하는 단계; 및 상기 TiN 확산방지막 상에 캐패시터의 메탈전극를 형성하는 단계를 포함한다.In order to achieve the above object, the present invention provides a method of manufacturing a capacitor, comprising: forming a contact hole by selectively etching an insulating film on a conductive layer; Forming a recessed polysilicon plug in the contact hole; Depositing Ti on the entire surface of the resultant and thermally reacting the polysilicon and the Ti to form a TiSi 2 ohmic contact layer; Washing and removing unreacted Ti; Removing oxides formed during the cleaning while forming the TiN diffusion barrier by plasma chemical vapor deposition including NH 3 gas; Etching the upper portion of the TiN diffusion barrier layer to planarize the wafer; And forming a metal electrode of the capacitor on the TiN diffusion barrier layer.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부한 도 3a 내지 도 3e를 참조하여 설명한다.Hereinafter, in order to explain in detail enough that a person having ordinary skill in the art to which the present invention pertains can easily carry out the technical idea of the present invention, refer to FIGS. 3A to 3E attached with the most preferred embodiment of the present invention. Will be explained.
후술하는 본 발명의 MIM(Metal Insulator Metal) 구조의 캐패시터는 전극으로 Pt, Ru, Ir, 등의 금속 또는 IrO2, TiN 등의 전도성 산화막 중 어느 하나를 적용 가능하다.The capacitor of the metal insulator metal (MIM) structure of the present invention described below may be applied to any one of metals such as Pt, Ru, Ir, and conductive oxide films such as IrO 2 and TiN.
도 2a 내지 도 2e는 본 발명의 반도체소자 제조 공정을 나타내는 단면도이다.2A to 2E are cross-sectional views illustrating a semiconductor device manufacturing process of the present invention.
먼저 도 2a에 보이는 바와 같이, 절연막(22)이 에칭된 전도층(21) 상에 리세스된 폴리실리콘 플러그(23)를 형성한다. 폴리실리콘 증착 및 에치백에 의해 폴리실리콘 플러그(23)가 형성되는 바, 에치 백 시 상기 절연막(22)의 상부를 기준으로 500Å 내지 2000Å의 깊이로 상기 폴리실리콘 플러그(23)가 리세스되도록 한다.First, as shown in FIG. 2A, a polysilicon plug 23 is formed on the conductive layer 21 on which the insulating film 22 is etched. The polysilicon plug 23 is formed by polysilicon deposition and etch back, so that the polysilicon plug 23 is recessed to a depth of 500 mV to 2000 mV based on the upper portion of the insulating film 22 during the etch back. .
다음으로, 도 3b에 도시된 것처럼 결과물 전면에 Ti 증착 후 급속열처리(Rapid Thermal Process; RTP) 공정에 의해 Ti와 폴리실리콘의 열반응을 통하여 TiSi2 오믹콘택층(24)을 형성한다. 여기서, 상기 급속열처리(RTP) 공정은100sccm 내지 1000sccm의 N2가스를 반응가스로 하여 650℃ 내지 800℃의 온도 및 0.2Torr 내지 1Torr의 압력 하에서 10초 내지 60초 동안 실시한다. 도면부호 '24a'는 미반응 Ti를 나타낸다.Next, as illustrated in FIG. 3B, the TiSi 2 ohmic contact layer 24 is formed through thermal reaction between Ti and polysilicon by a rapid thermal process (RTP) after Ti deposition on the entire surface of the resultant. Here, the rapid heat treatment (RTP) process is carried out for 10 seconds to 60 seconds at a temperature of 650 ℃ to 800 ℃ and a pressure of 0.2 Torr to 1 Torr using N 2 gas of 100sccm to 1000sccm as the reaction gas. Reference numeral '24a' represents unreacted Ti.
다음으로 도 2c에 도시된 바와 같이, 미반응한 Ti층(24a)과 기타 잔류산화물의 제거를 위해 SC-1 용액을 이용하여 세정공정을 실시한다. 그러나, 상기의 세정공정을 실시하여도 미반응 Ti와 잔류산화물(24b)은 존재하게 된다.Next, as shown in FIG. 2C, a cleaning process is performed using SC-1 solution to remove unreacted Ti layer 24a and other residual oxides. However, unreacted Ti and residual oxide 24b also exist even if the above washing step is performed.
이어서, TiSi2오믹콘택층(24) 표면에 플라즈마 화학기상증착법(Plasma Enhanced Chemical Vapor Deposition; PECVD)에 의해 TiN 확산 방지막(25)을 형성한다. 여기서, 상기 플라즈마 화학기상증착법(PECVD)은 400℃ 내지 700℃의 온도 및 0.2Torr 내지 10Torr의 압력과 30W 내지 500W의 파워 하에서 30초 내지 120초 동안 10sccm 내지 5slm 유량의 NH3반응가스와 기화된 TiCl4를 이용하여 실시된다. 이 과정에서 Ticl4가스는 50℃ 내지 70℃의 온도에서 기화시켜 챔버에 투입한다. 따라서, TiN 증착과 동시에 상기 NH3반응가스에 의해 잔류산화물(24b)은 질화되고,상기 TiSi2오믹콘택층(24)과 TiN 확산방지막(25)의 접촉 저항을 감소시킬 수 있다.Subsequently, a TiN diffusion barrier layer 25 is formed on the surface of the TiSi 2 ohmic contact layer 24 by plasma enhanced chemical vapor deposition (PECVD). The plasma chemical vapor deposition (PECVD) is vaporized with NH 3 reaction gas at a flow rate of 10 sccm to 5 slm for 30 seconds to 120 seconds at a temperature of 400 ° C to 700 ° C, a pressure of 0.2 Torr to 10 Torr and a power of 30W to 500W. It is carried out using TiCl 4 . In this process, Ticl 4 gas is vaporized at a temperature of 50 ° C to 70 ° C and introduced into the chamber. Accordingly, the residual oxide 24b is nitrided by the NH 3 reaction gas at the same time as the TiN deposition, and the contact resistance between the TiSi 2 ohmic contact layer 24 and the TiN diffusion barrier layer 25 can be reduced.
다음으로 도 2d에 도시된 것 처럼 TiN 확산방지막(25) 상부를 식각하여 평탄화 한다.Next, as illustrated in FIG. 2D, the upper portion of the TiN diffusion barrier layer 25 is etched and planarized.
다음으로 도 2e에 도시된 바와 같이 상기 TiN 확산방지막 상에 하부메탈전극(26) 과 유전막(27) 및 상부메탈전극(28)을 적층하여 캐패시터를 형성한다.Next, as shown in FIG. 2E, a capacitor is formed by stacking a lower metal electrode 26, a dielectric layer 27, and an upper metal electrode 28 on the TiN diffusion barrier layer.
여기서, TiN 확산방지막(25) 상부의 캐패시터는 평판형, 원통형, 실린더 형 중 어느 하나를 적용한다..Here, the capacitor on the TiN diffusion barrier 25 is applied to any one of a plate type, a cylindrical type, a cylindrical type.
전술한 것처럼 본 발명의 반도체소자 제조 방법은 TiN 확산방지막을 NH3반응가스를 포함한 플라즈마 화학기상증착법에 의해 형성함으로써, 잔류 산화막을 질화시켜 TiSi2오믹콘택층과 TiN 확산방지막의 계면 저항이 감소되어 결과적으로 하부전극의 콘택저항이 감소되며 이것으로 인해 전체적인 캐패시터의 전기적 특성을 향상시킬 수 있음을 실시예를 통해 알아보았다.As described above, in the method of fabricating the semiconductor device of the present invention, the TiN diffusion barrier is formed by a plasma chemical vapor deposition method including NH 3 reaction gas, thereby nitriding the residual oxide layer to reduce the interfacial resistance between the TiSi 2 ohmic contact layer and the TiN diffusion barrier. As a result, the contact resistance of the lower electrode is reduced, and as a result, it was found through the examples that the electrical characteristics of the entire capacitor can be improved.
이상에서 본 발명의 기술 사상을 바람직한 실시예에 따라 구체적으로 기술하였으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention has been described in detail according to a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상기와 같이 본 발명은 반도체소자 제조 방법에 있어서, 오믹콘택층과 확산방지막의 계면저항을 줄이므로써 하부메탈전극의 콘택 저항을 줄여 캐패시터의 전기적 특성을 향상시킬 수 있다.As described above, in the method of manufacturing a semiconductor device, the electrical resistance of the capacitor can be improved by reducing the contact resistance of the lower metal electrode by reducing the interface resistance between the ohmic contact layer and the diffusion barrier.
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