KR20020045746A - Sram device and method for manufacturing the same - Google Patents

Abstract

PURPOSE: A static random access memory(SRAM) device is provided to simplify a fabricating process, by using the first polysilicon layer, the second polysilicon layer, the first metal layer, the second metal layer instead of 3 polysilicon layers and 2 metal layers. CONSTITUTION: An SRAM cell is composed of two access transistors, 2 drive transistors and 2 high impedance resistors. A power supply line supplies power to the high impedance resistor. A word line controls the gate of the access transistor. A ground line is connected to the source of the drive transistor. A bit line and a bit line bar are connected to the drain of the access transistor, and data is inputted/outputted through the bit line and the bit line bar. The high impedance resistor is of a plug type using an undoped polysilicon layer.

Description

SRAM DEVICE AND METHOD FOR MANUFACTURING THE SAME

The present invention relates to an SRAM device and a method of manufacturing the same, and more particularly, to a cell layout of the SRAM device and a method of manufacturing the same.

Semiconductor memory devices are classified into DRAM and SRAM according to a storage method. SRAM is a very popular memory device that is driven by high speed, low power consumption and simple operation. In addition, unlike DRAM, it is not necessary to refresh periodically stored information, and it is easy to design.

In general, an SRAM cell is composed of two pull-down devices, two access devices, and two pull-up devices, which are completely dependent on the configuration of the pull-up device. It is classified into three types: a CMOS type, a high load resistor (HLR) type, and a thin film transistor (TFT) type. P-channel bulk MOSFET (P-channel bulk MOSFET) is used as a pull-up device in the full CMOS type, and a polysilicon layer with a high resistance value is used as a pull-up device in the HLR type, and a P-channel polysilicon TFT is used in the TFT type. Used as

Here, the SRAM device of the high load resistance type is symmetrically arranged and transmits a bit line or a bit bar line signal when the word lines W / L1 and W / L2 are turned on. A pair of access transistors Q1 and Q2, the drain and the drain of each of the access transistors Q1 and Q2 are connected, the source is connected to the ground line Vss, and the gate is connected to the drain of the symmetrically arranged access transistor. And a pair of symmetrically arranged driving transistors Q3 and Q4 and a pair of symmetrically arranged high load resistors R1 and R2 connected between the drain of the driving transistor and the power line Vcc.

However, the SRAM device according to the prior art has the following problems.

In SRAM devices, SRAM is manufactured using three polysilicon films and two metal films in an SRAM device of 1M or more.

At this time, since the bit line has a high topology, the bit contact resistance is high when the access transistors Q1 and Q2 are in contact with the active region, which is a problem in implementing a high speed SRAM device.

In addition, since the ground line contact formed at the same time as the bit line and in contact with the active region of the driving transistor is contacted using a polysilicon layer, the ground line contact resistance is high.

Accordingly, an object of the present invention for solving the above problems is to reduce the bit contact resistance and ground line contact resistance, and to provide a method for manufacturing an SRAM device that can achieve a process simplification.

1A to 1G illustrate a cell layout of an SRAM device according to the present invention.

Explanation of symbols on the main parts of the drawings

1 semiconductor substrate 2 device isolation film

5 gate 6 active region

8: first contact hole 9: plug high load resistance film

10: power supply voltage line 11: second contact hole

12: contact hole for bit line 13: contact hole for ground line

14 first tungsten plug film 15 word line

16: interlayer film for bit line 17: interlayer film for ground line

18: third contact hole 19: second tungsten plug film

20: bit line 21: ground line

Q1, Q2: access transistor Q3, Q4: drive transistor

1Nd: first node 2Nd: second node

The present invention for achieving the above object is composed of two access transistors, two driving transistors and two high load resistance, and controls a power supply voltage line for supplying power to the high load resistance and the gate of the access transistor An SRAM cell layout including a word line, a ground line connected to a source of a driving transistor, and a bit line and a bit bar line connected to a drain of the access transistor to input and output data. In this case, the non-doped polysilicon film is characterized in that it comprises a plug-type high load resistance.

Further, according to the present invention, there is provided a semiconductor substrate including an access transistor and a drive transistor having a first polysilicon film as a gate electrode; Depositing a first interlayer insulating film on the entire surface of the semiconductor substrate; Etching a portion of the first interlayer insulating layer to form a first contact hole exposing a portion of an active region of the access transistor and the driving transistor; Embedding an undoped polysilicon film on the first contact hole to form a plug high load resistance film; Forming a power supply voltage line by depositing a second polysilicon film on an upper surface of the entire structure on which the plug high load resistance film is formed; Depositing a second interlayer insulating film on an upper surface of the entire structure in which the power voltage line is formed; Forming a second contact hole simultaneously exposing a predetermined portion of an active region of the access transistor and a driving transistor for forming a bit line and a ground line while exposing a predetermined portion of a gate electrode of the access transistor on the second interlayer insulating film; step; Forming a plug polysilicon layer on the second contact hole; Depositing a first metal film on the entire surface of the resultant after the plug polysilicon film is formed, and patterning a predetermined portion to form word lines. Forming an intermediate layer in contact with the plug polysilicon layer in contact with the active regions of the access transistor and the driving transistor; Depositing a third interlayer dielectric layer on an upper surface of the entire structure where the word line and the intermediate layer are formed; Etching the third interlayer dielectric layer to expose a predetermined portion of the intermediate layer to form a third contact hole; And forming a bit line and a ground line by depositing a second metal layer on the third contact hole.

(Example)

Hereinafter, a method of manufacturing an SRAM device of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1G illustrate one cell layout of an SRAM device according to the present invention.

First, as shown in FIG. 1A, an element isolation film 2 for separating an element is formed on the semiconductor substrate 1. In this case, the device isolation film 2 is formed using a known process, for example, a shallow trench isolation (STI) process.

Next, on the semiconductor substrate 1 on which the device isolation film 2 is formed, a pair of pairs of access transistors Q1 and Q2 and drains of the access transistors Q1 and Q2 are arranged symmetrically with each other. Drive transistors Q3 and Q4 are formed.

At this time, in the cell layout in which the access transistors Q1 and Q2 and the driving transistors Q3 and Q4 are formed, the access transistors Q1 and Q2 and the driving transistors Q3 and Q4 are formed with a gate insulating film (not shown) and a gate. It is formed of a gate 5 composed of electrodes.

In addition, the gate electrode is preferably formed of a first polysilicon film.

Then, on the resulting product on which the gate 5 is formed, low concentration impurity ion implantation, spacers (not shown) are formed on both side walls of the gate 5, to form LDD (LightlyDoped Drain) which is a known process. By performing concentration impurity ion implantation, a source / drain region (not shown) is formed in the active region 6.

Subsequently, as shown in FIG. 1B, an interlayer insulating film (not shown) is formed on the upper surface of the entire structure in which the access transistors Q1 and Q2 and the driving transistors Q3 and Q4 are formed, although not shown in the drawing.

Then, on the interlayer insulating film (not shown), the active region 6 of the access transistor Q1, the active region 6 of the driving transistor Q3, and the gate of the driving transistor Q4 on the semiconductor substrate 1 The first contact hole 8 exposing a predetermined portion of 5) is formed to form the first node 1Nd.

In addition, at the same time, the active portion 6 of the access transistor Q2 on the semiconductor substrate 1, the active region 6 of the driving transistor Q4, and a predetermined portion of the gate 5 of the driving transistor Q3 are exposed. The first contact hole 8 is formed to form the second node 2Nd.

Then, the first contact hole 8 is filled with an undoped polysilicon film to contact the first node 1Nd and the second node 2Nd.

Subsequently, the undoped polysilicon film is blanket etched to form a plug high load resistance film 9 filling only the first contact hole 8.

At this time, the resistance of the plug high load resistance film 9 is adjusted to adjust the resistance value by controlling the ion implantation to the blanket.

Next, as shown in FIG. 1C, a second polysilicon film is deposited on the upper surface of the entire structure on which the plug high load resistance film 9 is formed to be in contact with the plug high load resistance film 9.

Subsequently, a predetermined portion of the second polysilicon film is patterned to form a power supply voltage line 10 having a cross shape.

Next, as illustrated in FIG. 1D, a second interlayer insulating film (not shown) is deposited on the upper surface of the entire structure in which the power supply voltage line 10 is formed.

Next, a second contact hole 11 exposing a predetermined portion of the gate 5 of the access transistors Q1 and Q2 is formed on the second interlayer insulating film (not shown).

At this time, the second contact hole 11 is formed, and at the same time, a portion for exposing a predetermined portion of the active region 6 of the access transistors Q1 and Q2 for contact between the bit line and the ground line to be formed later. Three contact holes, for example, bit line contact holes 12 are formed.

At the same time, a third contact hole for exposing a predetermined portion of the active region 6 of the driving transistors Q3 and Q4, for example, a contact hole 13 for a ground line, is formed.

Next, a metal film, preferably a first tungsten plug film 14, is formed to fill the second contact hole 11, the bit line contact hole 12, and the ground line contact hole 13.

Subsequently, as shown in FIG. 1E, the first tungsten plug layer 14 filling the second contact hole 11, the bit line contact hole 12, and the ground line contact hole 13 is formed. The first metal film is deposited on the upper surface of the structure.

Then, the bit line intermediate layer 16 which contacts the tungsten plug layer 14 buried in the bit line contact hole 12 is formed while the word line 15 is formed by patterning a predetermined portion of the first metal layer. And an interlayer film 17 for ground line contacting the tungsten plug film 14 buried in the contact hole 13 for ground line at the same time.

Subsequently, as illustrated in FIG. 1F, a third interlayer insulating film (not shown) is deposited on the entire structure of the word line 15, the bit line interlayer 16, and the ground line interlayer 17.

Next, a fourth contact hole 18 is formed on the third interlayer insulating layer (not shown) to expose a predetermined portion of the bit line intermediate layer 16 and the ground line intermediate layer 17.

Next, a metal film filling the fourth contact hole 18, preferably, a second tungsten plug film 19, is formed to form the bit line intermediate film 16 and the ground line intermediate film 17. Contact.

Subsequently, as illustrated in FIG. 1G, a second metal film is formed on the upper surface of the entire structure in which the second tungsten plug film 19 is formed.

Subsequently, the second metal film is partially patterned to form a bit line 20 in contact with the second tungsten plug film 19 on the bit line intermediate film 16, and at the same time, the ground line intermediate film 17 An SRAM device is manufactured by forming a ground line 21 in contact with the tungsten plug film 19 on the top.

As described in detail above, the present invention manufactures an SRAM device using a first and a second polysilicon film and a first and a second metal film, that is, 2 poly / 2 metal. Thus, it is possible to simplify the process of the SRAM device using a conventional 3 poly / 2 metal.

In addition, since the present invention is formed of a structure of 2 poly / 2 metal, the step difference of the bit line 20 is lowered, so that the conventional bit contact resistance can be reduced, so that a speed margin can be secured more than before.

In addition, the ground line 21 is formed between the active region 6 of the driving transistors Q3 and Q4, the first tungsten plug layer 14, the ground line intermediate layer 17, and the second tungsten plug layer 190. Is put in and contacted.

Thus, conventionally, the resistance can be reduced compared to the ground line formed with the polysilicon film interposed therebetween.

In addition, it can change and implement variously in the range which does not deviate from the summary of this invention.

Claims (5)

Two access transistors, two driving transistors, and two high load resistors, a power supply voltage line for supplying power to the high load resistor, a word line for controlling the gate of the access transistor, and a ground connected to the source of the driving transistor In the SRAM cell layout comprising a line, a bit line and a bit bar line connected to the drain of the access transistor to the input and output of data, An SRAM device comprising a plug-type high load resistance using an undoped polysilicon film. Providing a semiconductor substrate having an access transistor of an SRAM cell and a gate of a driving transistor formed of a first polysilicon film; Depositing a first interlayer insulating film having a first contact hole exposing a predetermined portion of an active region of the access transistor and a driving transistor on an entire surface of the semiconductor substrate; Filling a non-doped polysilicon film in the first contact hole to form a plug high load resistance film; Forming a power supply voltage line by depositing a second polysilicon film on an upper surface of the entire structure on which the plug high load resistance film is formed; A third contact hole for exposing a predetermined portion of a gate of the access transistor is formed on an upper surface of the entire structure in which the power supply voltage line is formed, and a third contact hole for exposing a predetermined portion of an active region of the access transistor and a driving transistor is provided; Depositing a second interlayer dielectric film; Forming a first metal plug layer on the second contact hole and the third contact hole; Depositing a first metal film on the entire surface of the resultant after forming the first metal plug film; Patterning the first metal film at a predetermined portion to form a word line in contact with the first metal plug film on the second contact hole. Simultaneously forming an intermediate layer in contact with the first metal plug layer on the third contact hole; Depositing a third interlayer dielectric layer having a fourth contact hole exposing a predetermined portion of the intermediate layer on an upper surface of the entire structure where the word line and the intermediate layer are formed; Forming a second metal plug layer on the fourth contact hole; Depositing a second metal film on an upper surface of the entire structure on which the second metal plug film is formed; And And forming a bit line and a ground line by patterning the second metal film at a predetermined portion. The method of claim 2, And said first metal plug film and said second metal plug film are formed of a tungsten plug film. The method of claim 2, And said third contact hole comprises a bit line contact hole and a ground line contact hole. The method of claim 2, The interlayer film is a method of manufacturing an SRAM device, characterized in that consisting of the interlayer film for the bit line and the ground line.