KR100345073B1 - Method of fabricating sram device using impurity diffusion by thermal process - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an SRAM device by diffusing a step of an oxide film formed on a thin film transistor and diffusion of impurity ions using a BSG film.

The SRAM device manufacturing method of the present invention comprises the steps of: forming a thin film transistor gate electrode on a semiconductor substrate provided with a base layer, and forming a gate oxide film, a thin film transistor channel and a polysilicon thin film for forming a power supply voltage line thereon; Etching and removing a predetermined portion after forming a barrier layer on the polysilicon thin film; Sequentially forming an impurity diffusion layer, a load oxide film, and an interlayer insulating film on the resultant product; And forming a metal wiring after planarizing the interlayer insulating film by a heat treatment process.

Description

Manufacturing method of SRM element which diffuses impurities through heat treatment process {METHOD OF FABRICATING SRAM DEVICE USING IMPURITY DIFFUSION BY THERMAL PROCESS}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a static random access memory (SRAM) device, wherein an oxide film on a thin film transistor is formed to have a step, and impurities are diffused by a heat treatment process to form a power supply voltage line. A method for manufacturing an SRAM device.

There are two basic MOS (Metal-Oxide Semiconductor) RAM structures for semiconductor memory devices: DRAM (Dynamic RAM) and SRAM. In the case of DRAM, bit data is stored in a capacitor, whereas SRAM uses a flip-flop structure.

The SRAM cell is composed of two pull-down devices, a drive transistor, two access transistors, and two pull-up devices.

1 shows a circuit diagram of a typical SRAM cell. Referring to FIG. 1, the SRAM 10 may include a first CMOS including a first P-MOS transistor P1 and a first NMOS transistor N1 having drains connected to each other. Complementary MOS Transistor 14, and the second CMOS transistor (15) composed of a second PMOS transistor (P2) and a second NMOS transistor (N2) connected to the drain, the output of the first CMOS transistor 14 The node n1 is connected to the second PMOS transistor P2 of the second CMOS transistor 15 and the gate Gate of the second NMOS transistor N2, and the output node n4 of the second CMOS transistor 15 is connected. Is connected to the gate of the first PMOS transistor P1 and the first NMOS transistor N1 of the first CMOS transistor 14.

In addition, a first access transistor N3 connecting the output node n1 of the first CMOS transistor 14 and a bit line 11 and an output node of the second CMOS transistor 15. and a second access transistor N4 connecting the n4 and the bit bar line 12.

The source of the first PMOS transistor P1 and the second PMOS transistor P2, which are pull-up devices, is connected to the power supply Vcc, and the first NMOS transistor N1 and the pull-down device are connected to the power source Vcc. The source of the 2 NMOS transistor N2 is connected to ground.

In the SRAM cell having the above structure, when the high state signal is applied to the word line 13, the first access transistor N3 and the second access transistor N4 are turned on, and thus the bit line ( 11 is connected to the drain node n1 of the first inverter 14 and the gate node n3 of the second CMOS transistor 15, and the bit bar line 12 is a gate node of the first CMOS transistor 14. n2 and the drain node n4 of the second CMOS transistor 15.

According to the configuration of the pull-up device, the SRAM cell has three types of structures: a fully complementary metal oxide semiconductor (CMOS) type, a high load resistor (HLR) type, and a thin film transistor (TFT) type. Classified as Full-CMOS type uses P-channel bulk metal oxide semiconductor field effect transistor (P-MOS) as pull-up device, and high-load resistance type uses polysilicon layer with high resistance value as pull-up device. In the transistor type, a P-channel polysilicon thin film transistor is used as a pull-up device.

Here, the thin film transistor type SRAM element can be significantly reduced in cell size, and thus it is easy to apply to a semiconductor memory device used exclusively for the memory element. That is, since the thin film transistor is formed on the substrate on which the driving transistor and the access transistor are formed, it is easy for high integration.

2 is a cross-sectional view of a conventional thin film transistor type SRAM device, and schematically illustrates a method of manufacturing a conventional thin film transistor type SRAM device through the drawings.

A gate insulating film is formed on the semiconductor substrate 21 provided with the field oxide film 22 separating the devices from the devices, and the first polysilicon film is deposited by a known deposition method. Subsequently, the first polysilicon film is partially patterned to form the gate electrode 23A of the access transistor and the gate electrode 23B of the driving transistor.

Impurities are injected into both semiconductor substrates 21 of the gate electrodes 23A and 23B of the access transistor and the driving transistor to form source and drain regions S and D of the transistor, respectively. At this time, in the drawing, the source region S is a portion to be contacted later with the bit line, and the drain region D is a common connection node between the access transistor, the driving transistor, and the thin film transistor to be formed later.

Thereafter, the first oxide layer 24 is deposited on the entire structure, and then the first oxide layer 24 is etched to expose the source region S of the access transistor. Then, a second polysilicon film is deposited to contact the exposed source region S, and then a predetermined portion is etched to form a bit line 25.

Thereafter, the second oxide film 26, the planarization insulating film 27, and the third oxide film 28 are sequentially formed on the bit line 25 and the first oxide film 24, and the common connection serving as the drain region of the driving transistor is sequentially formed. The third oxide layer 28, the planarization insulating layer 27, the second oxide layer 26, and the first oxide layer 24 are partially etched so that the node D and the gate electrode 23B of the drive transistor are simultaneously exposed. The contact hole C is formed.

Subsequently, after depositing a third polysilicon layer on the inner wall of the node contact hole C and the third oxide layer 28, the third polysilicon layer is formed in the region where the gate electrode of the thin film transistor is to be formed and inside the node contact hole C. Patterning is performed so as to exist in the adjacent region of the node contact hole (C) to form the gate electrode (29A) and the first node contact line (29B) of the thin film transistor. Then, impurities are implanted into the gate electrode 29A and the first node contact line 29B. Thereafter, the gate insulating film 30 of the thin film transistor is formed on the resultant, and the gate insulating film 30 is patterned to exist only in the region where the thin film transistor is to be formed.

Next, the resulting surface is cleaned using a fluorine-based wet solution, for example HF solution, in order to remove contamination and damage due to natural oxide film, etching. Thereafter, a fourth polysilicon film, which will serve as a second node contact line, a channel of the thin film transistor, and a power supply voltage (Vcc) line, is formed over the entire structure. Subsequently, impurities are ion-implanted only in portions of the fourth polysilicon film except for the channel forming portion of the thin film transistor, and are patterned to a predetermined size to supply a power supply voltage (Vcc) line 31A, the channel region 31B of the thin film transistor, and the second node. Line 31C is formed.

However, in the case of using the thin film transistor as a pull-up device as described above, in order to form a power supply voltage (Vcc) line, a fourth polysilicon thin film is formed with a very thin thickness of 200 to 300 kHz. If the ion implantation energy is not accurately controlled in the process of implanting the impurity ions to form the power supply voltage Vcc region, the resistance value of the power supply voltage Vcc line is severely changed.

FIG. 3 shows a photograph when a power supply voltage line (Vcc Line) is formed with a thin thickness as described above.

Therefore, when the SRAM device operates with a low power supply, there is a problem in that the power supply voltage line does not perform a normal operation.

The present invention is to solve the above problems, by using an oxide film and a BSG (Boro Silicate Glass) film having a step on the polysilicon thin film for forming a power voltage line on the polysilicon thin film through a subsequent heat treatment process It is an object of the present invention to provide a method for manufacturing an SRAM device by diffusing impurity ions.

1 is a circuit diagram of a typical SRAM cell,

2 is a cross-sectional view of a conventional thin film transistor type SRAM device,

3 is a photograph of the SRAM device of FIG.

4A to 4D are cross-sectional views of respective processes for illustrating a method of manufacturing an SRAM device according to an embodiment of the present invention.

(Name of the code for the main part of the drawing)

40: semiconductor substrate 41: base layer

42: gate electrode 43: gate oxide film

44: polysilicon thin film 45: barrier film

46: impurity diffusion layer 47: rod oxide film

48: interlayer insulating film

A1, A2: source / drain regions of the thin film transistor

B: Channel region of the thin film transistor C: LDO region of the thin film transistor

In order to achieve the above object, the SRAM device manufacturing method of the present invention forms a thin film transistor gate electrode on a semiconductor substrate provided with an underlayer, and a polysilicon thin film for forming a gate oxide film, a thin film transistor channel, and a power supply voltage line thereon. Forming a barrier layer on the polysilicon thin film, etching and removing a predetermined portion, forming an impurity diffusion layer, a load oxide layer, and an interlayer insulating layer on the resultant, And forming a metal wiring after the interlayer insulating film is planarized by a heat treatment process.

The barrier film is characterized in that a thin oxide film having excellent film quality is formed so as to prevent diffusion of impurities from the outside.

The barrier film is formed to a thickness of 500 to 1,000 Å.

The etching of the barrier layer may include a high concentration impurity region etching step of removing only the source / drain region of the thin film transistor, leaving a channel region and a light drain offset (LDO) region of the thin film transistor through a lithography process, and a thin film through a lithography process. And a low concentration impurity region etching step of removing the barrier layer in the LDO region of the transistor, leaving only a predetermined thickness.

The high concentration impurity region etching may be performed using a mask for forming a power supply voltage line.

The low concentration impurity region etching may be performed by removing about 10% of the initial thickness.

The impurity diffusion layer is characterized by using a BSG film.

The interlayer insulating film is characterized by using a BPSG (Boro Phospho Silicate Glass) film.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4A to 4D are cross-sectional views of respective processes for explaining a method of manufacturing an SRAM device according to the present invention. Here, in the present embodiment, the process of forming the driving transistor and the access transistor is the same as in the conventional art, and the description thereof is omitted, and the method of forming the thin film transistor will be described. In addition, in this figure, only the thin film transistor portion of the SRAM element is shown.

First, as shown in FIG. 4A, a gate conductive film is deposited on a semiconductor substrate 40 having a base layer 41, and then a predetermined portion is etched to form a gate electrode 42 of a thin film transistor. Then, the gate oxide film 43, the channel of the thin film transistor and the polysilicon thin film 44 for the power supply voltage line are sequentially formed on the gate electrode 42 and the base layer 41.

Thereafter, as shown in FIG. 4B, after depositing a barrier oxide film on the polysilicon thin film 44 to a predetermined thickness, a source / drain region A1 of the thin film transistor on which a power supply voltage line Vcc Line is to be formed. , A2 is removed, and the barrier layer 45 is formed by performing an etching process so that the channel region B and the LDO region C of the thin film transistor remain.

The barrier oxide film uses an oxide film having excellent film quality to prevent diffusion of impurities from an impurity diffusion layer to be formed thereon, and is preferably formed as thin as possible with a thickness of 500 to 1,000 mW. For example, the barrier oxide film is a thermal oxide film formed by a thermal oxidation method.

In this case, the etching of the barrier layer 45 removes only the source / drain regions A1 and A2 of the thin film transistor corresponding to the power supply voltage line, and thus may be performed using a power supply voltage line forming mask.

Then, as shown in FIG. 4C, the barrier film existing in the LDO region C of the thin film transistor is removed 45a again, leaving only a predetermined thickness. In this case, the barrier layer of the LDO region C of the thin film transistor may be removed from the impurity diffusion layer to be formed on the upper side, leaving only about 1/10 of the impurity to be injected at a low concentration into the lower polysilicon thin film 44.

Thereafter, as shown in FIG. 4D, the impurity diffusion layer 46, the load oxide film 47, and the interlayer insulating film 48 are sequentially formed so as to cover the barrier film 45a.

The impurity diffusion layer 46 is for injecting impurities into the polysilicon thin film 44 formed at a lower portion by a subsequent heat treatment process, and a BSG film is used. Therefore, the boron ions in the impurity diffusion layer 46 diffuse into the polysilicon thin film 44 under the heat treatment process to form a power supply voltage line. In other words, the power supply voltage line made of the thin polysilicon thin film 44 is formed by the impurity diffusion method by the heat treatment process, not by the ion implantation method.

In this case, while the impurities are diffused into the polysilicon thin film 44 by the heat treatment process, impurities may be injected from the interlayer insulating layer 48 formed thereon to the lower side. In order to prevent this, the rod oxide layer 47 may be impurity diffused. It forms on 46.

In addition, the interlayer insulating film 48 preferably uses a BPSG film to improve planarization characteristics.

After the SRAM element is formed as described above, the interlayer insulating film 48 is planarized through a heat treatment step, and subsequent steps such as a metal wiring step are performed.

As a result, in the heat treatment process of planarizing the interlayer insulating film 48, impurities (borons) in the impurity diffusion layer 46 are directly diffused into the polysilicon thin film in the thin film transistor source / drain regions, or by a barrier film on the thin film transistor LDO region. The channel and power supply voltage lines of the thin film transistor are formed by diffusion into the polysilicon thin film at low concentration or by not being diffused into the channel region of the thin film transistor by the barrier film.

In the above description, only the SRAM device has been described as an example. However, the present invention is not limited to the SRAM device, and the present invention may be equally applied to a thin film transistor such as a thin film transistor liquid crystal display (TFT-LCD). Can be.

As described in detail above, according to the manufacturing method of the present invention, the thin film transistor channel and the power supply voltage line are more easily formed by allowing impurities to diffuse from the impurity diffusion layer during the heat treatment process without directly implanting ions into the thin polysilicon thin film. There is an advantage that can be formed.

Therefore, the resistance of the power supply voltage line can be kept constant, thereby ensuring safety in the operation of the SRAM element.

Hereinafter, this invention can be implemented in various changes in the range which does not deviate from the summary.

Claims (8)

Forming a thin film transistor gate electrode on a semiconductor substrate provided with an underlayer, and forming a polysilicon thin film for forming a gate oxide film, a thin film transistor channel, and a power supply voltage line thereon; Etching and removing a predetermined portion after forming a barrier layer on the polysilicon thin film; Sequentially forming an impurity diffusion layer, a load oxide film, and an interlayer insulating film on the resultant product; And forming a metal wiring after planarizing the interlayer insulating film by a heat treatment process. The method of claim 1, wherein the barrier film It is a thermal oxidation film formed by the thermal oxidation method. The manufacturing method of the SRAM element characterized by the above-mentioned. The method of claim 2, wherein the barrier film A method of manufacturing an SRAM element, characterized in that it is formed in a thickness of 500 to 1,000 GPa. The method of claim 1, wherein the etching of the barrier layer comprises: A high concentration impurity region etching step of removing only the barrier layer formed on the source / drain region of the thin film transistor without removing the channel region of the thin film transistor and the barrier film formed on the LDO region; And a low concentration impurity region etching step of removing the barrier layer formed on the LDO region of the thin film transistor, leaving only a predetermined thickness. The method of claim 4, wherein the high concentration impurity region etching step is performed. A method of manufacturing an SRAM element, comprising using a mask for forming a power supply voltage line. The method of claim 4, wherein the low concentration impurity region etching step is performed. A method of manufacturing an SRAM device, characterized in that the removal of leaving about 10% of the initial thickness. The method of claim 1, wherein the impurity diffusion layer A method for producing an SRAM device, comprising using a BSG film. The method of claim 1, wherein the interlayer insulating film A method of manufacturing an SRAM element, comprising using a BPSG film.