KR20020045748A - Sram device and method for manufacturing the same - Google Patents

Abstract

PURPOSE: A static random access memory(SRAM) device is provided to make the widthwise length of an SRAM cell longer than its lengthwise length, by disposing access transistors and drive transistors in the same direction. CONSTITUTION: An SRAM cell(100) is composed of two access transistors, 2 drive transistors and 2 high impedance resistors. A power supply line supplies power to the high impedance resistor. A word line controls the gate of the access transistor. A ground line is connected to the source of the drive transistor. A bit line and a bit line bar are connected to the drain of the access transistor, and data is inputted/outputted through the bit line and the bit line bar. The access transistors and the drive transistors are disposed in the same direction. The ground line and the bit line are formed of the same conductive layer.

Description

SRAM DEVICE AND METHOD FOR MANUFACTURING THE SAME

The present invention relates to an SRAM device and a method of manufacturing the same, and more particularly, to a cell layout of the SRAM device and a method of manufacturing the same.

Semiconductor memory devices are classified into DRAM and SRAM according to a storage method. SRAM is a very popular memory device that is driven by high speed, low power consumption and simple operation. In addition, unlike DRAM, it is not necessary to refresh periodically stored information, and it is easy to design.

In general, an SRAM cell is composed of two pull-down devices, two access devices, and two pull-up devices, which are completely dependent on the configuration of the pull-up device. It is classified into three types: a CMOS type, a high load resistor (HLR) type, and a thin film transistor (TFT) type. P-channel bulk MOSFET (P-channel bulk MOSFET) is used as a pull-up device in the full CMOS type, and a polysilicon layer with a high resistance value is used as a pull-up device in the HLR type, and a P-channel polysilicon TFT is used in the TFT type. Used as

Here, the SRAM device of the high load resistance type is symmetrically arranged and transmits a bit line or a bit bar line signal when the word lines W / L1 and W / L2 are turned on. A pair of access transistors Q1 and Q2, the drain and the drain of each of the access transistors Q1 and Q2 are connected, the source is connected to the ground line Vss, and the gate is connected to the drain of the symmetrically arranged access transistor. And a pair of symmetrically arranged driving transistors Q3 and Q4 and a pair of symmetrically arranged high load resistors R1 and R2 connected between the drain and power line Vcc of the driving transistor.

However, the conventional SRAM device has the following problems.

In recent years, as the cell size decreases, the interval between the bit lines or bit varines through which data is input and output is reduced, thereby increasing the load on the lines.

This acts as a major factor to reduce the SRAM characteristics that require high-speed operation, and the difficulty in processing is increasing.

In addition, the bit line uses a low-resistance metal wire. In addition to the bit line, the ground line should also have a low resistance.

If the resistance of the ground line is high, cell operation becomes unstable and data is difficult to maintain.

In addition, when one word line is turned on when the SRAM cells are arranged, current flows in several cells. When such a current flows through one ground line, the voltage of the ground line increases, which may cause a problem of deterioration of cell stability.

In addition, the access transistors Q1 and Q2 and the drive transistors Q3 and Q4 are integrated on the substrate surface, while the load resistors R1 and R2, the power line Vcc, the ground line Vss and the bit line Bit are / Bit) is integrated on both the substrate surface and the top of the layer.

Accordingly, since the load resistance, the power line, the ground line and the bit line are integrated at the top of the substrate, a plurality of line patterns are densely packed on the top of the substrate, and it is very difficult to secure the process margin between the patterns.

Accordingly, an object of the present invention is to solve the conventional problems described above, and to provide an SRAM device and a method of manufacturing the SRAM device capable of improving the characteristics of the SRAM device by securing stability and process margin of the cell.

1 is a circuit diagram of an SRAM device according to the prior art.

2A, 3A, 4A, 5A and 6A are plan views showing the cell layout of an SRAM device according to the present invention.

2B, 3B, 4B, 5B, and 6B are cross-sectional views illustrating a method of manufacturing an SRAM device according to the present invention.

1 semiconductor substrate 2 gate insulating film

3: device isolation layer 4: gate electrode

5 spacer 6 active area

6a, 6b: source / drain regions 7: first interlayer insulating film

8: first contact hole 9: first polysilicon layer

10 second insulating interlayer 11 second contact hole

12 second polysilicon layer 13 third interlayer insulating film

14 third contact hole 15 third polysilicon layer

16: fourth interlayer insulating film 17: fourth contact hole

18: bit line 19: bit bar line

20: ground line 100: cell

The present invention for achieving the above object, two access transistors, two drive transistors, two high load resistors, a power supply voltage line for supplying power to the high load resistor, and a word for controlling the gate of the access transistor An SRAM device comprising: a line, a ground line connected to a source of a driving transistor, a bit line connected to a drain of the access transistor, to input and output data, and a bit bar line. The driving transistors are arranged in the same direction.

Further, according to the present invention, two access transistors, two drive transistors, two high load resistors, a power supply voltage line for supplying power to the high load resistor, a word line for controlling the gate of the access transistor, An SRAM device comprising a ground line connected to a source of a driving transistor, a bit line connected to a drain of the access transistor to input and output data, and a bit bar line, wherein the access transistor and the driving transistor are connected to each other. Formed by forming in the same direction with each other, characterized in that the ground line and the bit line is formed of the same conductive layer.

According to the present invention, there is provided a semiconductor substrate including a driving transistor and an access transistor having a first polysilicon film as a gate electrode and having the same direction as each other; Depositing a first interlayer insulating film on the entire surface of the driving transistor and the access transistor; Forming a first contact hole exposing a predetermined portion of an active region of the access transistor and a predetermined portion of a gate electrode of the driving transistor on the interlayer insulating layer; Depositing a second polysilicon film on the first contact hole; Implanting ions into the second polysilicon layer to form a high load resistance and patterning a predetermined portion; Forming a second interlayer insulating film on an upper surface of the entire structure on which the high load resistance is formed; Forming a second contact hole exposing a predetermined portion of a gate electrode of the access transistor on the second interlayer insulating film; Depositing a third polysilicon layer on the second contact hole and patterning the third polysilicon layer to form a word line; Depositing a third interlayer dielectric layer on the entire structure of the word line; Forming a third contact hole exposing a predetermined portion of the high load resistance on the third interlayer insulating film; Depositing a fourth polysilicon layer in contact with the high load resistance on the third contact hole to form a power supply voltage line; Depositing a fourth interlayer insulating film on an upper surface of the entire structure in which the power voltage line is formed; Forming a fourth contact hole on the fourth interlayer insulating film to partially expose an active region of the access transistor and the driving transistor; And embedding a conductive layer on the fourth contact hole so as to be in contact with the active regions of the access transistor and the driving transistor to simultaneously form a bit line and a ground line.

(Example)

Hereinafter, an embodiment of an SRAM device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2A illustrates a pair of driving transistors Q3 connected to an isolation layer, a pair of access transistors Q1 and Q2 and drains of the access transistors Q1 and Q2 on the semiconductor substrate 1, and symmetrically arranged. The cell layout of the SRAM device in which the gate electrode 4 of Q4 is formed is shown.

Four cells 100 are shown in the figure.

Here, the gate electrode 4 is formed of a first polysilicon layer.

As shown, the access transistor Q1 and the driving transistor Q3 and the access transistor Q2 and the driving transistor Q4 are formed in parallel in the same direction.

In addition, active regions 6 are formed on both sides of the access transistors Q1 and Q2 and the gate electrodes 4 of the driving transistors Q3 and Q4.

As described above, the access transistors Q1 and Q2 and the driving transistors Q3 and Q4 are formed so that the horizontal direction of the cell can be made larger than the longitudinal direction of the cell. This configuration makes it possible to increase the width and spacing of the bit lines to be formed later, thereby facilitating the manufacturing process.

Next, referring to FIG. 2B, FIG. 2B illustrates a cross-sectional view of the AA ′ line of FIG. 2A.

As shown, the gate insulating film 2 is formed on the semiconductor substrate 1.

Next, a gate electrode material, for example, a first polysilicon layer is deposited on the gate insulating layer 2.

Subsequently, the first polysilicon layer is patterned to form a gate electrode 4.

Then, in order to form a lightly doped drain (LDD) which is a known process, low concentration impurity ion implantation is performed on the upper surface of the entire structure in which the gate electrode is formed, and spacers 5 are formed on both sidewalls of the gate electrode 4. Form.

High concentration impurity ion implantation is then performed to form source / drain regions 6a and 6b to form an access transistor Q1 and a driving transistor Q3.

3A shows a cell layout of an SRAM device in which high load resistors R1 and R2 are formed on a resultant product in which the access transistors Q1 and Q2, the driving transistors Q3 and Q4, and the contact holes 8 are formed. .

As shown, the high load resistance R1 is formed such that the active region 6 of the access transistor Q1 and the active region 6 of the driving transistor Q3 are contacted, and at the same time the access transistor 8 is formed on the contact hole 8. And to contact the active region of Q1 and the gate electrode 4 of the driving transistor Q4.

In addition, the high load resistance R2 is formed such that the active region 6 of the access transistor Q2 and the active region 6 of the driving transistor Q4 are in contact with each other, and at the same time, the contact transistor 8 of the access transistor Q2 is formed. It is formed to contact the active region and the gate electrode 4 of the driving transistor Q3.

At this time, a first interlayer insulating film (not shown) is disposed between the high load resistors R1 and R2, the active region 6 of the access transistors Q1 and Q2, and the driving transistors Q2 and Q4.

Next, referring to FIG. 3B, FIG. 3B illustrates a cross-sectional view taken along line BB ′ of FIG. 3A.

An access transistor Q1 and a driving transistor Q4 are shown on the semiconductor substrate 1 on which the device isolation film 3 is formed.

The first interlayer insulating layer 7 is formed on the upper surface of the entire structure in which the access transistor Q1 and the driving transistor Q4 are formed.

Next, a predetermined portion of the first interlayer insulating layer 7 is exposed to the first interlayer insulating layer 7 to expose an active region 6 of the access transistor Q1 and a predetermined portion of the gate electrode of the driving transistor Q4. The portion is etched to form the first contact hole 8.

Subsequently, a second polysilicon layer is deposited on the first contact hole, and impurity ion implantation is performed on the second polysilicon layer.

Next, the impurity ion implanted second polysilicon layer is patterned to form a high load resistance 9.

At this time, the resistance value of the high load resistance 9 can be adjusted through the ion implantation.

4A shows a cell layout of an SRAM device in which word lines 11 are formed on the gate electrodes 4 and the second contact holes 11 of the access transistors Q1 and Q2.

At this time, a second interlayer insulating film (not shown) and a first interlayer insulating film (not shown) are disposed between the word line 11 and the access transistors Q1 and Q2.

4B, there is shown a cross-sectional view of the BB 'line in FIG. 4A.

A second interlayer insulating film 10 is formed on the upper surface of the entire structure in which the high load resistances R1 and R2 are formed. Subsequently, the second interlayer insulating film 10 and a predetermined portion of the first interlayer insulating film 7 are sequentially rotated to expose a predetermined portion of the gate electrode 4 of the access transistor Q1 to the second interlayer insulating film 10. The second contact hole 11 is formed by etching.

Subsequently, a third polysilicon layer is embedded in the second contact hole 11 so as to be in contact with the gate electrode 4 of the access transistor Q1, and the buried third polysilicon layer is partially patterned. The word line 12 is formed.

In this case, the word line 12 may be formed of a polyside layer in addition to the third polysilicon layer.

5A shows a cell layout of the SRAM device in which the high load resistors R1 and R2 and the power supply voltage line 15 are contacted on the fourth contact hole 14.

In this case, the power supply voltage line 15 is formed of a fourth polysilicon layer, and between the power supply voltage line 15 and the high load resistors R1 and R2, a second interlayer insulating film (not shown) and a third interlayer are formed. An insulating film (not shown) is provided.

5B shows a cross-sectional view of the CC ′ line of FIG. 5A.

A third interlayer insulating layer 13 is deposited on the upper surface of the entire structure in which the word line 12 is formed. Subsequently, the fourth contact hole 14 is formed by sequentially etching the predetermined portions of the third interlayer insulating film 13 and the second interlayer insulating film 10 so that a predetermined portion of the high load resistance R1 is exposed.

Next, a fourth polysilicon layer is buried in the fourth contact hole 14 to contact the high load resistance R1. Subsequently, the fourth polysilicon layer is partially patterned to form a power supply voltage line 15.

6A shows that the active region 6 and the conductive layer of the access transistors Q1 and Q2 are contacted on the fifth contact hole 17 so that the bit line 18, the bit bar line 19, and the ground are connected. A cell layout of an SRAM device forming a line 20 is shown.

In this case, a first interlayer insulating film, a second interlayer insulating film, a third interlayer insulating film, and a fourth interlayer insulating film (not shown) are disposed between the conductive layer and the active region 6 of the access transistors Q1 and Q2. .

Here, the ground line 20 is disposed at right angles to the word line 12 in FIG. 4A, and the bit line 18, the ground line 20, and the bit bar line 19 are disposed in parallel to each other. .

In addition, in the related art, only one bit line may be formed by one conductive layer, whereas in the present invention, the ground line 20 may be formed in addition to the bit line 18 by one conductive layer.

6B shows a cross-sectional view of the DD 'line in FIG. 6A.

A fourth interlayer insulating film 16 is deposited on the upper surface of the entire structure in which the power supply voltage line 15 is formed.

Subsequently, the fourth interlayer insulating film 16, the third interlayer insulating film 13, the second interlayer insulating film 10, and the first interlayer insulating film may be exposed to expose a predetermined portion of the active region 6 of the access transistor Q1. A predetermined portion of 7) is etched to form a fourth contact hole 17.

Next, the conductive layer is buried in the fourth contact hole 17 to contact the active region 6 of the access transistor Q1.

Next, the conductive layer is patterned to form a bit line 18 in contact with the active region 6 of the access transistor Q1.

In addition, although not shown in the drawing, a ground line 20 is formed in contact with the active region 6 of the driving transistors Q3 and Q4, and the bit bar line 19 is in contact with the active region of the access transistor Q2. To form an SRAM device.

Referring to the above-described embodiment, since the length of the bit line passing through one cell is shortened, the resistance and capacitance of the bit line can be lowered, thereby lowering the load on the bit line.

In addition, the current from one cell flows only to one ground line passing over the cell, since the ground line and the word line are disposed at right angles.

As a result, as in the prior art, as much current is concentrated in one ground line, a problem of raising the ground line voltage does not occur.

As described in detail above, the SRAM device of the present invention arranges the access transistors Q1 and Q2 and the driving transistors Q3 and Q4 in the same direction so that the horizontal direction of the SRAM cell is longer than the length of the longitudinal direction. I can make it big.

This makes it possible to increase the width and spacing of the bit lines to be formed later, thereby facilitating the manufacturing process.

In addition, since the length of the bit line passing through one cell is shortened, the resistance and capacitance of the bit line can be lowered, thereby reducing the load on the bit line.

Thus, the operating speed of the SRAM device may be increased.

In addition, since only one cell current flows through one ground line, the voltage of the ground line is stable.

As a result, as in the prior art, as much current is concentrated in one ground line, a problem of raising the ground line voltage does not occur.

Claims (15)

Two access transistors, two driving transistors, two high load resistors, a power supply voltage line for supplying power to the high load resistor, a word line for controlling the gate of the access transistor, and a ground connected to the source of the driving transistor An SRAM device comprising a line, a bit line connected to a drain of the access transistor, through which data is inputted and outputted, and a bit bar line, And the access transistor and the driving transistor arranged in the same direction to each other. The method of claim 1, And the ground line and the word line are at right angles to each other. The method of claim 1, And the ground line and the bit line are formed of the same conductive layer. The method of claim 1, The high load resistance is an SRAM device, characterized in that formed after the polysilicon layer, by adjusting the resistance value through ion implantation. The method of claim 3, wherein And the conductive layer is a low resistance metal layer. The method of claim 1, And said wordline is formed by one of a polysilicon layer and a polyside layer. The method of claim 1, And said power supply line is formed of a polysilicon layer. Two access transistors, two driving transistors, two high load resistors, a power supply voltage line for supplying power to the high load resistor, a word line for controlling the gate of the access transistor, and a ground connected to the source of the driving transistor An SRAM device comprising a line, a bit line connected to a drain of the access transistor, through which data is inputted and outputted, and a bit bar line, Forming the access transistor and the driving transistor in the same direction, And the ground line and the bit line are formed of the same conductive layer. The method of claim 8, The high load resistance is an SRAM device, characterized in that formed after the polysilicon layer, by adjusting the resistance value through ion implantation. The method of claim 8, And the conductive layer is a low resistance metal layer. The method of claim 8, And said wordline is formed by one of a polysilicon layer and a polyside layer. The method of claim 8, And said power supply line is formed of a polysilicon layer. Providing a semiconductor substrate having a first polysilicon layer as a gate electrode and having driving transistors and access transistors having the same direction; Depositing a first interlayer insulating film on the entire surface of the driving transistor and the access transistor; Forming a first contact hole exposing a predetermined portion of an active region of the access transistor and a predetermined portion of a gate electrode of the driving transistor on the interlayer insulating layer; Depositing a second polysilicon layer on the first contact hole; Performing ion implantation on the second polysilicon layer and patterning a predetermined portion of the ion implanted second polysilicon layer to form a high load resistance; Forming a second interlayer insulating film on an upper surface of the entire structure on which the high load resistance is formed; Forming a second contact hole exposing a predetermined portion of a gate electrode of the access transistor on the second interlayer insulating film; Depositing a third polysilicon layer on the second contact hole and patterning the third polysilicon layer to form a word line; Depositing a third interlayer dielectric layer on the entire structure of the word line; Forming a third contact hole exposing a predetermined portion of the high load resistance on the third interlayer insulating film; Depositing a fourth polysilicon layer in contact with the high load resistance on the third contact hole to form a power supply voltage line; Depositing a fourth interlayer insulating film on an upper surface of the entire structure in which the power voltage line is formed; Forming a fourth contact hole on the fourth interlayer insulating layer to expose a predetermined portion of active regions of the access transistor and the driving transistor; And And embedding a conductive layer on the fourth contact hole so as to be in contact with the active regions of the access transistor and the driving transistor, thereby simultaneously forming a bit line and a ground line. The method of claim 13, And the word line and the ground line are arranged at right angles. The method of claim 13, And the conductive layer is formed of a metal layer having low resistance.