KR20020045507A - Method and device for adjustment of IC tester - Google Patents

Abstract

PURPOSE: To precisely adjust the timing, using an input signal for test with a frequency the same as that when an actual testing object IC is measured. CONSTITUTION: This method is a method for adjusting the timing of the input signal for test supplied to each signal pad in an IC tester for conducting the input of the testing input signal to the testing object IC via the signal pads formed plurally in a measuring board and an acquirement of an output signal of the object IC with respect to the testing input signal, so as to test the testing object IC. In the method, the each testing input signal is inputted in order in an alternative way into a comparator connected to one end of a flexible signal transmission line by making the other end of the signal transmission line contact, in order, with the signal pads to measure each inversion timing when an output of the comparator is inverted, and the testing input signal is adjusted so that each inversion timing is to be a specified timing.

Description

METHOD AND DEVICE FOR ADJUSTMENT OF IC TESTER

The present invention relates to an IC tester adjusting method and apparatus for timing adjustment of a test input signal to an IC tester which performs various operation tests by inputting a test input signal to an IC (integrated circuit).

As is well known, an IC tester is an apparatus for testing the operation characteristics of various ICs, and it is to test whether the operation of the IC is normal by evaluating the output signal to the test input signal. Such an IC tester regularly or arbitrarily adjusts the timing relationship between test input signals, and an adjusting device dedicated to this adjustment, that is, an IC tester adjusting device, is used. Timing adjustment (timing adjustment) between test input signals using the IC tester adjusting device has become very important with the recent increase in the speed of the IC, and the number of adjustments has also increased due to the need to more accurately test the operating characteristics of the IC.

2 is a schematic diagram showing an example of a conventional IC tester adjusting device. In this figure, reference numeral 1 denotes a measuring board, 2a, 2b,... … 2n is a test driver, 3a, 3b,... … 3n is an open / close switch, 4 is a waveform probe, 5 is an X-Y robot, and 6 is an oscilloscope.

On the surface of the measuring board 1, a plurality of signal pads are formed on the surface of the signal pads in contact with the IC under test, and each of the signal pads has a test input signal Sa to Sn for input to the IC under test. , 2b, ..., 2n, and open / close switches 3a, 3b, ..., 3n are supplied from the IC tester main body (not shown), respectively. By operating the XY robot 5, the waveform observation probe 4 is brought into contact with each of the signal pads, and the waveforms of the test input signals Sa to Sn of the respective signal pads acquired by the waveform observation probe 4 are changed. By measuring with the oscilloscope 6, the timing adjustment of the test input signals Sa to Sn supplied to each signal pad is performed on the IC tester main body side.

In this timing adjustment, when the actual test target IC is measured by using the oscilloscope 6 having a wide frequency characteristic that can sufficiently measure the test input signals Sa to Sn of the highest frequency of operation of the IC tester. It is possible to perform timing adjustment by using the test input signals Sa to Sn having the same frequency as. However, the general purpose interface bus (GPIB) is used as the interface standard of the instrument for the operation control of the oscilloscope 6, and the test input signal (Sa) of each signal pad is controlled while controlling the oscilloscope 6 through the GP-IB. Since sn) is observed, there is a problem that the timing adjustment time is lengthened in proportion to the number of signal pads.

3 is a schematic diagram showing another example of the conventional IC tester adjusting device. This timing adjustment is performed by using the open / close switches 7a, 7b,... 7n, the relay matrix circuit 8 and the reference comparator 9 instead of the corrugated observation probe 4, the XY robot 5, and the oscilloscope 6. will be. That is, by opening / closing the switches 3a, 3b,... 3n to the open state and closing the switches 7a, 7b,... 7n to the closed state, they are output from the respective test drivers 2a, 2b,... The test input signals Sa to Sn are input to the relay matrix circuit 8, and are alternatively selected by the relay matrix circuit 8 to be supplied to the reference comparator 9. As the inversion timing of the output of the reference comparator 9, the timing of each test input signal Sa to Sn is detected, and the inversion timing is adjusted to a prescribed value.

In this timing adjustment, since the oscilloscope 6 operating and controlled through the GP-IB is not used, the problem of longer timing adjustment is solved. However, the relay matrix circuit 8 uses the test input signals Sa to Sn. Waveform deterioration occurs, and the timing of the test input signals Sa to Sn at the output terminals of the test drivers 2a, 2b, ..., 2n is adjusted, not on the original signal pads. Adjustment cannot be realized. In this timing adjustment, since the waveform of the test input signals Sa to Sn in the relay matrix 8 is degraded, the test input signals Sa to Sn of the same frequency are used as in the case of measuring the actual test target IC. There is also a problem that timing adjustment cannot be performed.

4 is a schematic diagram which shows another example of the conventional IC tester adjustment apparatus. In such an IC tester adjusting device, the reference comparator 9 'is prepared on an XY robot 5', and the output of the reference comparator 9 'is transmitted through a flexible coaxial cable 10 to the IC tester main body. In this case, timing adjustment of each test input signal Sa to Sn is performed. That is, by operating the XY robot 5 ', the reference comparator 9' is sequentially transferred onto each signal pad on the measurement board 1, and the input terminal of the reference comparator 9 'is connected to each signal pad by contacting. The inversion timing of the test input signals Sa to Sn on each signal pad is detected, and the respective test input signals Sa to Sn are adjusted so that the inversion timing is a specified value.

In this timing adjustment, since the above-described matrix circuit 8 is not used, the waveform deterioration of the test input signals Sa to Sn does not occur, and therefore the test input signal of the same frequency as that of the actual test target IC ( The timing adjustment can be performed using Sa to Sn). However, as in the case of FIG. 2 described above, since the structure of the X-Y robot 5 'becomes complicated, its cost and weight increase.

The present invention has been made in view of the above-described problems, and an object thereof is to precisely adjust timing by using a test input signal having the same frequency as in the case of measuring an actual test target IC.

1 is a schematic diagram showing the configuration of an IC tester adjusting device according to an embodiment of the present invention.

2 is a schematic diagram showing an example of a conventional IC tester adjusting device in an IC tester;

3 is a schematic diagram showing another example of a conventional IC tester adjusting device in an IC tester;

Fig. 4 is a schematic diagram showing still another example of the conventional IC tester adjusting device in the IC tester.

<Description of the symbols for the main parts of the drawings>

One ; Measuring board

2a, 2b,... … 2n; Test Driver

3a, 3b,... … 3n, 7a, 7b,... … 7n; On / off switch

4 ; Waveform Probe

5, 5A; X-Y Robot

6; oscilloscope

8 ; Relay matrix circuit

9, 9 ', 9A; Standard comparator (comparator)

10, 10A; Coaxial Cable (Signal Transmission Line)

In order to achieve the above object, in the present invention, as a first means according to the IC tester adjustment method, the input of the test input signal for the test target IC and the test target for the test input signal through a plurality of signal pads formed on the measurement board An IC tester for acquiring an output signal of an IC and testing the IC under test, wherein the timing of the test input signal supplied to each of the signal pads is regulated by a prescribed timing. By sequentially contacting one end with each of the signal pads, each test input signal is alternatively sequentially inputted to a comparator connected to the other end of the signal transmission line, and the inverted timings in which the comparator output is inverted are respectively measured. Means for adjusting each test input signal shall be adopted to achieve the specified timing.

As a second means according to the IC tester adjusting method, in the first means, a test input signal supplied to each signal pad is set to the same frequency as when the actual test target IC is tested.

As a third means according to the IC tester adjusting method, the first or second means employs a means of using a coaxial cable as a signal transmission line.

On the other hand, in the present invention, as a first means according to the IC tester adjusting device, the input of the test input signal to the test target IC and the output signal of the test target IC to the test input signal through a plurality of signal pads formed on the measuring board An apparatus for adjusting the timing of the test input signal supplied to each signal pad with a prescribed timing, with respect to an IC tester for acquiring an IC tester for acquiring the test target IC, wherein the device has flexibility and A signal transmission line for transmitting a test input signal, an XY robot for holding the one end of the signal transmission line and moving the measurement board on the measurement board to contact the one end with each signal pad, and the other end of the signal transmission line And a comparator for comparing the test input signal input from the signal transmission line with a predetermined threshold value. A means for adjusting each test input signal is adopted so that the inversion timing of the output of the comparator is the specified timing.

As the second means according to the IC tester adjusting device, in the first means, the test input signal supplied to each signal pad has means set to the same frequency as when the actual test target IC is tested. .

As the third means according to the IC tester adjusting device, the first or second means employs a means of using a coaxial cable as a signal transmission line.

Hereinafter, an embodiment of an IC tester adjusting method and apparatus according to the present invention will be described with reference to the drawings. In addition, in the following description, the same code | symbol is attached | subjected to the component already demonstrated, and the description is abbreviate | omitted.

1 is a schematic diagram showing the configuration of the IC tester adjusting device according to the present embodiment. The feature of this configuration is that by holding one end of the core of the flexible coaxial cable 10A in the XY robot 5A, the one end is alternately sequentially contacted with each signal pad on the measurement board 1, and The input end of the reference comparator 9A is connected to the other end of the core wire of the coaxial cable 10A so that the respective test input signals Sa to Sn are sequentially and alternatively inputted to the reference comparator 9A.

In other words, the IC tester adjusting device maintains one end of the coaxial cable 10A having a signal transmission function on the XY robot 5A moving on the measurement board 1 so as to test input signals Sa to Sn on each signal pad. Is selected alternatively, so that the conventional relay matrix circuit 8 is not used.

Here, the coaxial cable 10A has a characteristic impedance equal to that of each signal pad, for example, one having a characteristic impedance of 50 Ω. With this consideration, waveform distortions of each test input signal Sa to Sn are suppressed to the minimum and are input to the reference comparator 9A.

In addition, in this embodiment, since waveform distortion is suppressed by using 10 A of coaxial cables, the frequency of each test input signal Sa-Sn is set to the same frequency as the case where an actual test object IC is measured.

In the IC tester adjusting device configured as described above, one end of the coaxial cable 10A comes into contact with a signal pad to which, for example, a test input signal Sa is supplied, for example, by the operation of the XY robot 5A. Sa) is input to the reference comparator 9A via the coaxial cable 10A. Then, the inversion timing Ta of the test input signal Sa is detected by the reference comparator 9A, and the timing of the test input signal Sa is adjusted so that the inversion timing Ta is equal to the prescribed timing TR. Adjusted.

In the same manner below, one end of the coaxial cable 10A is sequentially brought into contact with a signal pad to which a test input signal Sb is supplied, and a signal pad to which a test input signal Sn is supplied. Each timing of the test input signals Sb to Sn is adjusted so that the inverted timings Tb to Tn of the signals Sb to Sn are detected and the inverted timings Tb to Tn are equal to the prescribed timing TR. do.

According to this embodiment, since one end of the core wire of the coaxial cable 10A is held by the XY robot 5A, the test input signals Sa to Sn on the respective signal pads are alternatively selected in a state where the waveform distortion is suppressed. Since the reference comparator 9A can be input, the timing inputs of each test input signal Sa to Sn can be precisely adjusted.

In addition, since the coaxial cable 10A adopts the same characteristic impedance as that of the signal pad, it is possible to minimize waveform distortion. In this way, waveform distortion can be suppressed to a minimum. It is possible to set the frequency of Sa-Sn) in the same way as in the case of measuring the actual IC under test, thus increasing the accuracy of timing adjustment.

As described above, according to the IC tester adjusting method and apparatus according to the present invention, each test input signal is selected to a comparator connected to the other end of the signal transmission line by sequentially contacting one end of the flexible signal transmission line to each signal pad. By sequentially inputting the signals, the inverting timing in which the comparator output is inverted is measured separately, and each test input signal is adjusted so that each inverting timing becomes a specified timing. Therefore, each test input signal is compared with a conventional relay matrix circuit. It is possible to suppress the occurrence of waveform distortion of the signal, and thus it is possible to precisely adjust the timing of each test input signal.

Claims (6)

Through input of a plurality of signal pads on the measuring board 1, the input of the test input signals Sa to Sn to the test target IC and the output signals of the test target IC to the test input signals Sa to Sn are acquired. In the method for adjusting the timing of the test input signals Sa to Sn supplied to respective signal pads with a prescribed timing (TR) for an IC tester for testing the test target IC, By sequentially contacting one end of the flexible signal transmission line 10A with the respective signal pads, each test input signal Sa to Sn is alternatively connected to the comparator 9A connected to the other end of the signal transmission line 10A. Inverting timings Ta to Tn in which the comparator 9A output is inverted by sequentially inputting each of them are measured, and each test input signal Sa to Sn is set such that each inversion timing Ta to Tn becomes the specified timing TR. IC tester adjusting method, characterized in that for adjusting (). The IC tester adjusting method according to claim 1, wherein the test input signals Sa to Sn supplied to the respective signal pads are set to the same frequency as when the actual test target IC is tested. An IC tester adjusting method according to claim 1 or 2, wherein a coaxial cable is used as the signal transmission line (10A). Through a plurality of signal pads formed on the measuring board 1, the input of the test input signals Sa to Sn to the test target IC and the output signals of the test target IC to the test input signals Sa to Sn are acquired and tested. An apparatus for adjusting the timing of the test input signals Sa to Sn supplied to respective signal pads to a prescribed timing TR with respect to an IC tester for testing a target IC, A signal transmission line 10A having flexibility and transmitting test input signals Sa to Sn of each signal pad contacted at one end thereof; An X-Y robot 5A which maintains the one end of the signal transmission line 10A and selectively contacts the one end to each signal pad by moving on the measurement board 1; A comparator 9A connected to the other end of the signal transmission line 10A and comparing the test input signals Sa to Sn inputted from the signal transmission line 10A with a predetermined threshold value, And the respective test input signals Sa to Sn so that the inversion timings Ta to Tn of the output of the comparator 9A become the specified timing TR. The IC tester adjusting device according to claim 4, wherein the test input signals Sa to Sn supplied to the respective signal pads are set to the same frequency as when the actual test target IC is tested. The IC tester adjusting device according to claim 4 or 5, wherein a coaxial cable is used as the signal transmission line (10A).