JP2000199781A - Semiconductor device tester and its calibration method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To calibrate the output timing of test signal in a semiconductor test device, having a socket which has a first terminal capable of giving test signals to a semiconductor device and a driver outputting the test signal to the first terminal. SOLUTION: For this tester provided are a step installing a testing board having a terminal array similar to the terminal array of a semiconductor device 20 to a socket 50, a production step for producing test signals with a driver 76, a detection step for detecting the test signal having reached the testing board and a setting step for setting the output timing of the test signals, based on the test signals detected in the detection step. It is desirable that the contact terminal contacting the first terminal 12 in the testing board have the same input impedance as the contact terminal which makes contact with the first terminal 12 in the semiconductor device 20.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device test apparatus for testing a semiconductor device (also referred to as a "DUT"; for example, a semiconductor integrated circuit). And its calibration method.

[0002]

FIG. 1 is a sectional view of a conventional semiconductor test apparatus. The test head 70 outputs a test signal for testing the semiconductor device 20 and receives an output signal output from the semiconductor device 20. A performance board 66 for transmitting a signal between the test head 70 and the coaxial cables 62 and 64 is mounted on the test head 70. A coaxial cable 62 transmits the test signal from the performance board 66 to the socket board 60, and transmits the output signal from the socket board 60 to the performance board 66. A socket 50 is provided on the socket board 60, and a test signal is supplied to the semiconductor device 20 via the pins 52 and the first terminals 12 of the socket 50,
The output signal is received from the semiconductor device 20 via the second terminal 14 and the pin 54.

The test head 70 includes a driver 76 (76A, 76B) for generating a test signal, and a driver delay circuit 78 for delaying the test signal generated by the driver 76.
(78A, 78B), a comparator 80 (80A, 80B) that receives an output signal, and a comparator delay circuit 82 (82) that delays the time from when the comparator 80 receives the output signal to when the output signal is output.
A, 82B). A test signal output from each driver 76 is measured by a probe of a measuring device such as an oscilloscope, and the delay time given by the driver delay circuit 78 is adjusted so that the timing of the test signal output from each driver becomes the same. Thereby, the plurality of drivers 76
The skew between them can be offset. Further, the skew between the plurality of comparators 80 can be canceled by adjusting the delay time given by the comparator delay circuit 82.

FIGS. 2A and 2B are a top view and a front view, respectively, of semiconductor device 20. Here is TSOP
Although a semiconductor device of a type is shown, the semiconductor device may be of a type such as QFP or BGA. By preparing sockets 50 corresponding to semiconductor devices of various shapes, any of the semiconductor devices can be tested in the same manner. The semiconductor device 20 has a semiconductor device input pin 22 for inputting a signal and a semiconductor device output pin 24 for outputting a signal, and these pins contact the first terminal 12 and the second terminal 14 of the socket 50. .

FIG. 3 is a sectional view showing the socket 50 and the socket board 60 on which the socket 50 is mounted. When the socket 50 is mounted along the socket guide 58 of the socket board 60, the pins 52 and 54 of the socket 50 are inserted into the through holes 56 of the socket board 60.
Is inserted. The core wires of the coaxial cables 62 and 64 are inserted and soldered from below the through hole 59 of the socket board 60. In recent years, since the number of pins of the semiconductor device 20 has increased, the first terminal 12 of the socket 50 has:
It is difficult to accurately apply a probe such as an oscilloscope. Therefore, a method has been proposed in which the semiconductor device 20 is removed from the socket 50 and the probe is directly brought into contact with the socket board.

FIG. 4 is a top view of the socket board 60. Pin 5 of socket 50 is provided on socket board 60.
2, 54 and a through hole 5 for inserting and soldering a coaxial cable.
9 are provided. In addition, a ground pattern (GND) and a power supply pattern (VD
D) is provided. By applying an oscilloscope probe to the socket board 60, the semiconductor test apparatus can be calibrated.

FIG. 5 shows a probe 4 on a socket board 60.
4 is shown. The probe 44 has a signal terminal 40 and a ground terminal 42. The socket 50 is removed from the socket board 60 provided in the test apparatus, the signal terminal 40 of the probe 44 is brought into contact with the through hole 56 for the socket, and the ground terminal 42 is connected to the socket board 60.
By contacting the upper ground pattern, a signal applied to the through hole 56 can be measured. However, when the ground pattern is not near the through hole to be measured, the ground wire of the probe 44 connected to the ground terminal 42 must be lengthened, and the line impedance at the time of measurement increases. recent years,
With the speeding up of the semiconductor device 20, the semiconductor device 2
There is a need to test 0 with high accuracy. Therefore, it is necessary to calibrate the semiconductor test device with high accuracy. However, if the line impedance of the signal when measuring the test signal is large, the semiconductor test device cannot be calibrated accurately.

Since the signal wiring pattern and the ground pattern are provided adjacent to each other on the performance board 66, the socket 50, the socket board 60, and the coaxial cables 62 and 64 are removed, and the probe is directly brought into contact with the performance board. Then, the line impedance of the signal can be reduced. However, in this case,
Since the effects of the inductance and stray capacitance of the coaxial cables 62 and 64, the socket board 60, and the socket 50 do not appear in the test signal, accurate calibration cannot be performed in an actual test state.

FIG. 6 shows another conventional method for calibrating a semiconductor test apparatus. In this embodiment, a comparator 80 and a programmable load 180 are provided in parallel with the driver 76. By appropriately setting the programmable load 180, a desired load can be applied to the driver 76. Socket 50
When the test signal is output from the driver 76, the test signal is reflected at the upper end of the socket 50 and input to the comparator 80. By dividing the time (time during which the test signal reciprocates) t1 by 2, the signal transmission time from the driver 76 to the socket 50 can be measured.

FIG. 7 shows still another embodiment of the conventional semiconductor test apparatus. A form has been proposed in which two coaxial cables are connected to each pin of the socket 50 as shown in the figure. In this case, even if the semiconductor device 20 is removed to generate a test signal, the test signal is transmitted to the comparator 90 without being reflected by the socket 50. For this reason,
The test signal transmission time from the driver 76 to the socket 50 cannot be measured.

FIG. 8 shows a flowchart of a conventional calibration method. First, the probe 44 is brought into contact with the through hole 56 of the socket board 60 and the ground pattern GND, which are measurement points (S302). Next, timing measurement and calibration are performed (S310). That is, the rising or falling timing of the waveform of the test signal output from the one-channel driver is measured, and calibration data is obtained. The setting value of the driver delay circuit 78 is set to an initial state, and a test signal is generated under a predetermined amplitude condition (S312). Next, the timing of the rising waveform of the test signal is measured, and the driver 76 is calibrated with the rising waveform (S314). Next, the timing of the falling waveform of the test signal is measured, and the driver 76
Is calibrated (S316).

FIG. 9A shows a waveform of the test signal measured in the timing measuring step (S310). The waveform S ₀ has a _value of 50 at the reference timing position t ₀ .
% Level. Waveform _{S 1} and _{S 2} is made at each time _{t 1} and _{t 2} 50% level. The slew rate represents the rising or falling slope of the waveform. The plurality of drivers 76 included in the test head 70 are adjusted to output signals at a slew rate of less than 500 picoseconds / V ± 10%. In the rising waveform measurement step (S314), FIG.
As shown in, calibrate a plurality of drivers 76 by moving the timing t ₁ and t ₂ to the reference timing position t ₀ delay adjustment to the corresponding driver delay circuit 78 to each of the plurality of drivers 76 . As a result of this movement, setting data obtained by increasing or decreasing the delay amount of the driver delay circuit 78 is obtained as calibration data. When the signal terminal 40 of the probe 44 and the through hole 56 of the socket board 60 are in a high resistance state due to dust or the like,
Since the level of the test signal decreases and 50% of the level is not detected, it can be easily recognized that a contact failure has occurred.

FIG. 9C shows a waveform of a test signal when the ground terminal 42 of the probe 44 and the ground pattern GND of the socket board 60 are in poor contact. Waveform S ₄
FIG. 9 is a waveform example when the ground terminal 42 and the ground pattern GND are open. Waveform S ₆ is a waveform example when there is a high contact resistance between the ground terminal 42 and the earth pattern GND. Waveform _{S 4} and _{S 6} are distorted and the waveform is caused to accent. However, even in the waveform S ₄ and S _6, since normal waveform S ₀ Like 50% level is measured, contact failure unnoticed timing calibration from being performed. Therefore, since calibration cannot be performed at an appropriate timing position, erroneous calibration may be performed. For example, in the waveform _{S 6,} the deviation _{e 2} of the timing with respect to the original normal waveform _{S 0} has occurred. Further, the deviation _{e 1} timing occurs even in the waveform _{S 4.} Therefore, the driver 76 is calibrated at an incorrect timing. If the calibration is performed in a state where the timing shift has occurred, it may be a factor of deteriorating the accuracy of the calibration or a factor of deteriorating the reliability in the calibration work.

As a method of checking for a contact failure, there is a method of measuring a DC resistance at a contact point between the probe 44 and the socket board 60. This method uses probe 4
4 is applicable to poor contact between the signal terminal 40 of No. 4 and the through hole 56 of the socket board 60. However, the poor contact between the ground terminal 42 of the probe 44 and the ground pattern GND of the socket board 60, which is the ground line, can be detected because the ground pattern GND is a circuit ground and is commonly connected. Have difficulty.

Accordingly, the present invention provides at least one of the above objects.
It is an object of the present invention to provide a semiconductor test apparatus that can solve the above problems. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous embodiments of the present invention.

[0016]

According to a first aspect of the present invention, a socket having a first terminal capable of supplying a test signal to a semiconductor device by mounting the semiconductor device, and a socket for transmitting the test signal to the first terminal. Mounting a test board having a terminal arrangement similar to the terminal arrangement of the semiconductor device to a socket in order to calibrate an output timing of a test signal in a semiconductor test apparatus having a driver for outputting to a terminal; , A detection step of detecting a test signal that has reached the test board, and a setting step of setting the output timing of the test signal based on the test signal detected by the detection step. Here, it is preferable that the contact terminal of the test board that contacts the first terminal has the same input impedance as the contact terminal of the semiconductor device that contacts the first terminal.

According to a second aspect of the present invention, a test board has an earth short pattern that is in contact with a first terminal and is connected to the ground, and the detecting step is performed by a test board output from a driver. Measure the reflected test signal.

According to a third aspect of the present invention, the semiconductor test apparatus further includes a delay circuit for delaying the test signal, and the generating step includes outputting the test signal by the driver and generating the predetermined reference signal. The setting step includes a delay setting step of setting a magnitude of a delay added by the delay circuit based on a phase difference of the test signal detected in the detection step with respect to the reference signal.

According to a fourth aspect of the present invention, a test board has a signal wiring pattern contacting a first terminal, and an earth pattern arranged adjacent to the signal wiring pattern. A test signal is detected by an electrical characteristic test probe attached to the signal wiring pattern and the ground pattern.

According to a fifth aspect of the present invention, a semiconductor test apparatus has a plurality of drivers, a socket has a plurality of first terminals associated with each of the plurality of drivers, and the test board has A plurality of signal wiring patterns are associated with each of the plurality of first terminals, a detecting step is performed on each of the plurality of signal wiring patterns, and a delay setting step is measured on each of the plurality of signal wiring patterns. The magnitude of each delay in the plurality of delay circuits is set so that the magnitude of the phase difference becomes the same.

According to a sixth aspect of the present invention, the socket further has a second terminal for contacting the semiconductor device and receiving an electric signal from the semiconductor device, and the semiconductor test apparatus receives an input from the second terminal. The test board is a short board having a short pattern for electrically connecting the first terminal and the second terminal.

According to the seventh aspect of the present invention, the test signal output from the driver and passed through the short board is detected by the comparator. Next, a value obtained based on a time difference between a reference timing having a predetermined time difference with respect to the output step and a time when the test signal is detected in the comparator detection step is set as a reference time for testing the semiconductor device. I do. A plurality of drivers and a plurality of comparators are provided in the semiconductor test apparatus, and a plurality of first terminals associated with each of the plurality of drivers and a plurality of second terminals associated with each of the plurality of comparators are provided in the socket. Providing a plurality of short patterns for connecting the plurality of first terminals and the plurality of second terminals to the short board, performing the detecting step on each of the plurality of signal wiring patterns, and setting the reference time to each of the plurality of comparators. On the other hand, the reference times may be set independently.

According to the eighth aspect of the present invention, a plurality of sockets, a plurality of test boards such as a short board corresponding to each of the plurality of sockets, and a frame for integrally holding the plurality of test boards are provided. , And the frame has, for each test board, a call-in mechanism for moving the test board to a desired position when the frame is mounted at a predetermined position in the semiconductor test apparatus.

According to a ninth aspect of the present invention, a driver for outputting a test signal used for testing a semiconductor device, a comparator for receiving an electrical signal from the semiconductor device, and a test signal for mounting the semiconductor device and for outputting the test signal In a calibration method for calibrating a processing timing of a semiconductor test apparatus having a socket that can be provided to a semiconductor device, a test signal or an electrical signal required to be provided to a measuring instrument for measuring a waveform of a test signal is provided. A connection step of making a connection, a waveform measurement step of measuring the test signal output by the driver with a measuring instrument,
A waveform determining step of determining whether the waveform of the test signal measured by the measuring instrument is within a desired range; and a connection made to the measuring instrument when the waveform measured by the measuring instrument is out of the desired range. It is preferable to include a notifying step of notifying that there is. In the waveform measuring step, it is preferable to measure at least one of rising and falling waveforms of the test signal. Further, the notification step includes, when the waveform is out of the desired range, a reconnection step of repeating the connection step, the waveform measurement step, and the waveform determination step, and the connection step, the waveform measurement step, and the waveform determination step a predetermined number of times It is preferable to include a failure notifying step of notifying that the connection made to the measuring instrument is defective when the waveform is out of the desired range even after repetition.

According to a tenth aspect of the present invention, in the above-described calibration method, the measuring device is a measuring device external to the semiconductor test apparatus, and the measuring device has an electrical characteristic test probe for inputting a test signal. Preferably, the connecting step includes a step of making a necessary connection for providing a test signal to the electrical characteristic test probe.

According to an eleventh aspect of the present invention, in the above-mentioned calibration method, the measuring device is a measuring device inside the semiconductor test device, and the waveform measuring step is performed by outputting the test signal reflected from the socket output from the driver. Preferably, the method includes a step of inputting from the comparator and measuring at the measuring device.

According to a twelfth aspect of the present invention, in the above-mentioned calibration method, the measuring device is a measuring device inside the semiconductor test apparatus, and the waveform measuring step is a step of measuring the predetermined reference signal input from the comparator by the measuring device. It is preferable to have the step of measuring at.

According to a thirteenth aspect of the present invention, in the above-mentioned calibration method, the connecting step includes a step of connecting a test board for inputting a test signal for calibration and supplying the test signal to the measuring instrument. It is preferred to have.

According to a fourteenth aspect of the present invention, in the above-mentioned calibration method, the measuring device is a measuring device inside the semiconductor test apparatus, and the waveform measuring step is output from the driver and reflected by the test board. Preferably, the method further comprises a step of inputting the test signal from the comparator and measuring the test signal in the measuring instrument.

According to a fifteenth aspect of the present invention, in the above-mentioned calibration method, the waveform judging step judges whether the level of the test signal in a rising or falling period of the test signal is within a desired range. Is preferred.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described through embodiments of the present invention. However, the following embodiments do not limit the claimed invention and have the features described in the embodiments. Not all combinations are essential to the solution of the invention.

FIG. 10 shows a cross section of the entire semiconductor test apparatus in this embodiment. The same components as those in FIG. 1 are denoted by the same reference numerals as those in FIG. On the socket board 60, a plurality of sockets 50 connected to the performance board by coaxial cables 62 and 64 are provided. Further, a plurality of holding units 110 are held (mounted) on the frame 100, and an opening 120 is provided at an upper portion of each holding unit. Each holding unit 110 holds one semiconductor device 20.
In the test head 70, two coaxial cables 62, 6
Although only a circuit for the semiconductor device 20 is shown, a coaxial cable is provided for each pin of the semiconductor device 20 and a driver 7 is provided for each coaxial cable.
6, a delay circuit 78, a comparator 80, and a comparator delay circuit 82 are provided. Although only a circuit corresponding to one semiconductor device 20 is shown in the figure, a similar circuit is actually provided for each semiconductor device.

The present semiconductor test apparatus can test a plurality of semiconductor devices at the same time, so that more semiconductor devices can be tested in a given time. When calibrating the semiconductor test apparatus, the test board 10 is used instead of the semiconductor device 20 in advance.
Is attached to each holding unit 110. When the frame 100 is mounted on the semiconductor test apparatus, the test board 10 is mounted on the socket 50. Next, a probe is applied to the test board 10 from above the opening 120, and a test signal is generated by the driver 76. The test signal reaching the test board 10 is detected by an oscilloscope, and the output timing of the test signal is set by changing the setting of the delay circuit 78A based on the detected test signal.

The driver 76 is provided for each of a plurality of signals applied to the semiconductor device 20. The test head 70 further includes one driver 176 for generating a reference signal and one driver 176 for giving a predetermined delay to the reference signal.
And two delay circuits 178. The time difference between when the reference signal is generated and when the driver 76 generates the test signal is always constant. Therefore, this reference signal is input to the oscilloscope as a trigger. By making the phase difference between the phase of the test signal output from each driver 76 and the phase of the reference signal the same, it is possible to indirectly align the phases among the plurality of drivers 76 and reduce the skew between the drivers. it can. However, as another form, one test signal that reaches the test board 10 may be selected as a reference signal and input as a trigger of an oscilloscope, and the phase of another test signal may be matched to the phase of the selected test signal. .

FIGS. 11A and 11B show the holding unit 11.
FIG. 2 is a top view and a bottom view of a probe board 10A as an example of a test board 10 to be mounted on the probe board 10; On the lower surface of the test board 10, contact terminals 30 are provided in the same arrangement as the terminals of the semiconductor device 20. When the frame 100 is attached to the semiconductor test device, the contact terminals 30 come into contact with the first terminal 12 and the second terminal 14 of the socket 50. The ground pattern 36 and the plurality of signal wiring patterns 32 provided on the upper surface are connected to the contact terminals 30 provided on the lower surface. The ground pattern 36 extends to the center of the upper surface. The ground pattern 36 is adjacent to each signal wiring pattern 32, and the shortest distance is about 2 mm or less. Therefore, each signal wiring pattern 32 and ground pattern 36
Then, the signal terminal 40 and the ground terminal 42 of the probe 44 can be easily brought into contact. Further, since the shortest distance between each signal wiring pattern 32 and the ground pattern 36 is substantially equal, variation in line impedance of each signal is small, and each signal can be measured accurately.

Driver 7 at the time of calibration
6 and the actual semiconductor device 20
When the driver 76 is mounted on the semiconductor test apparatus,
In order to prevent an error from occurring between the output timing of the semiconductor device 20 and the output timing of the semiconductor device 20, it is preferable that the input impedance of each signal at the contact terminal 30 be substantially the same as the input impedance of the signal at the actual semiconductor device 20. In order to make the input impedance the same as that of the semiconductor device 20, an appropriate capacitor (capacitance), a resistor, and the like may be provided between the signal wiring pattern 32 and the ground pattern 36, as is well known.

FIG. 12 shows another embodiment of the probe board 10A. The probe board 10 </ b> A has a plurality of contact terminals 30 provided on the outer peripheral side surface of an insulating block 270 having substantially the same external dimensions as the semiconductor device 20, in substantially the same arrangement as the terminals of the semiconductor device 20. Contact terminal 30
Can contact the first terminal 12 and the second terminal 14 of the socket 50 on the side surface or the lower surface of the insulating block 270.

A plurality of signal wiring patterns 32 are formed at locations extending from the plurality of contact terminals 30 to the periphery of the upper surface of the insulating block 270, respectively. Signal wiring pattern 3
2 is used to make the signal terminal 40 of the probe 44 contact. Therefore, the signal wiring pattern 32 has a bulged shape so that the signal terminals 40 can easily contact with each other.
A ground pattern 36 is formed inside the plurality of signal wiring patterns 32 so as to extend from the ground terminal 37. The ground pattern 36 is used to contact the ground terminal 42 of the probe 44. The probe 4
4 is held by the holding fitting 262.

Since the ground pattern 36 is adjacent to each signal wiring pattern 32, the signal wiring pattern 32 and the ground pattern 36 can be easily brought into contact with the signal terminal 40 and the ground terminal 42 of the probe 44. Since the ground terminal 42 and the ground pattern 36 can be brought into contact with each other in a short distance, the ground terminal 42 can be grounded with low impedance. For this reason, the external noise superimposed on the test signal via the conventional ground impedance is reduced, and the distortion of the test signal due to the influence of the noise is suppressed.
The accuracy of the calibration is improved. Further, since the signal wiring pattern 32 and the signal terminal 40 can maintain stable contact, noise generated from a contact portion between the signal wiring pattern 32 and the signal terminal 40 and distortion of a test signal due to the noise are suppressed, and calibration is performed. Accuracy is improved.

FIGS. 13A and 13B show the test board 10.
9 shows a short board 10B as another example. A contact terminal 30 that contacts the first terminal 12 and the second terminal 14 of the socket 50 is provided on the lower surface of the short board 10B. A plurality of short patterns 46 for short-circuiting the contact terminals 30 contacting the first terminals and the contact terminals 30 contacting the second terminals 14 are provided on the upper surface of the short board 10B.
Is provided. Probe board 10A shown in FIG.
Is mounted on a semiconductor test apparatus, and after calibrating the skew between the plurality of drivers 76, the probe board 10A is removed from the semiconductor test apparatus.
3 is attached to the semiconductor test device.

In this state, the skew between the plurality of comparators 80 is calibrated. First, test signals are simultaneously generated from the plurality of drivers 76A. Driver 7
The test signal generated by the short board 10A
The signal reaches the comparator 80B via B. Driver 7
The approximate delay time from when the test signal 6 generates the test signal to when the comparator 80 detects the test signal is known in advance. Thus, for example, when the reference signal is taken into the oscilloscope 150 as a trigger, a time obtained by adding a known delay time by the oscilloscope 150 is selected as the reference timing. However, in another embodiment of the present invention, a time when a reference signal is detected may be selected as the reference timing. This is zero as the delay time above
This corresponds to the selection of "0".

Next, a time difference from the reference timing to when each of the comparators 80 detects the test signal is measured for each comparator 80, and a value based on the time difference is set as a reference time for testing the semiconductor device 20. This is set for each comparator 80. For example, if the time difference is + a, the delay time of the comparator delay circuit 82 corresponding to the comparator 80 is reduced by a, and the time difference becomes -a
If so, the delay time by the comparator delay circuit 82 is increased by a. Thereby, the skew between the plurality of comparators 80 can be calibrated.

However, as another embodiment, a memory for storing the delay time may be provided for each comparator 80 instead of the comparator delay circuit 82, and the time difference may be simply stored in the memory. In this case, by subtracting the time difference stored in the memory from the time when the comparator 80 detects when the semiconductor device 20 is actually tested, a value in which the influence of the skew between the comparators 80 can be obtained. As such a memory,
In addition to the semiconductor digital memory, an analog memory, a delay circuit whose delay time can be set, or the like can be used. Means for reducing the time difference include subtraction by numerical operation,
Subtraction by analog operation, subtraction by a delay circuit, and the like can be used.

FIG. 14 shows another embodiment of the semiconductor test apparatus. The same components as those shown in FIG. 10 are denoted by the same reference numerals, and their description will be omitted. In this embodiment, the coaxial cable 64 corresponding to the output terminal of the semiconductor device 20 is provided with only the comparator 80B and the comparator delay circuit 82B, and the driver 76B and the driver delay circuit 78B shown in FIG. 10 are omitted. ing. The driver 76A and the comparator 8
A programmable load 180 that applies a desired load to the driver 76A is provided in parallel with 0A.

First, the semiconductor device 20 and the test board 10 are removed from the socket 50, and the delay time by the driver delay circuit 78A and the comparator delay circuit 82A is set to zero "0". Next, the time from when the output voltage of the driver 76A is changed to when the comparator 80A detects the reflected current, that is, the driver 76A and the socket 5
A time t1 at which the test signal reciprocates between 0 and 0 is measured. By dividing the time t1 by 2, the time from when the driver 76A generates the test signal to when the test signal is transmitted to the socket 50, that is, the one-way time (t1) / 2 can be obtained. By measuring the transmission time (t1) / 2 of the test signal for each driver 76A, the time difference Δdr of each test signal in the path from the plurality of drivers 76 to the socket 50 can be obtained.

FIG. 15 shows a method for easily obtaining the signal transmission time from the socket 50 to the comparator 80B. Attach the short board 10B to the socket 50,
A test signal is generated by the driver 76A. The test signal is received by the comparator 80B via the coaxial cable 62, the short board 10B, and the coaxial cable 64. The time from when the driver 76 generates the test signal to when the comparator 80B receives the test signal, that is, the signal transmission time t2 between the driver 76 and the comparator 80B.
Is measured, and the transmission time (t1) / 2 between the driver 76 and the socket 50 is subtracted from t2, whereby the signal transmission time t3 from the socket 50 to the comparator 80B can be obtained. By measuring the transmission time t3 from the socket 50 to each comparator 80B, the time difference Δcp of the test signal in the path from the socket 50 to each comparator 80B can be obtained. By changing the delay time set in the driver delay circuit 78 based on the time difference Δdr in the path on the driver 76A side, the skew between the drivers 76A can be offset. Also, by changing the delay time set in the delay circuit 82B for the comparator 80B based on the time difference Δcp,
Skew among the plurality of comparators 80B can be canceled.

FIG. 16 shows still another embodiment of the semiconductor test apparatus. In the present embodiment, two coaxial cables are connected to one terminal of the socket 50. In this case, since the impedance mismatch does not occur in the socket 50 even when the semiconductor device 20 and the test board 10 are removed, the signal transmission time from the driver 76 to the socket 50 and the signal transmission time from the socket 50 to the comparator 90 are obtained. Can not do. Therefore, first, an earth short board 10C as an example of the test board 10 is attached to the socket 50. Earth short board 1
At 0C, each test signal is shorted to ground. This causes an impedance mismatch in the ground short board 10C, so that the signal generated by the driver 76 is reflected to the comparator 80.

Next, the earth short board 10C shown in FIG.
The delay time in the delay circuit 92 is set to zero “0”. Further, when a test signal is generated by the driver 76,
As in the case of FIG. 15, the test signal is supplied to the coaxial cable 62,
It is received by comparator 90 via 64. The time from when the driver 76 generates the test signal to when the comparator 90 receives the test signal, that is, the signal transmission time t2 between the driver 76 and the comparator 90 is measured, and the transmission time between the driver 76 and the socket 50 is measured. (T1) /
By subtracting 2 from t2, the signal transmission time t3 from the socket 50 to the comparator 90 can be obtained. By measuring the transmission time t3 from the socket 50 to each comparator 90, the time difference Δcp of the test signal in the path from the socket 50 to each comparator 90B is obtained. The skew between the drivers 76 can be canceled by changing the delay time set in the driver delay circuit 78 based on the time difference Δdr in the path on the driver 76 side. Further, by changing the delay time set in the delay circuit 92 for the comparator 90 based on the time difference Δcp, the skew between the plurality of comparators 90 can be canceled.

FIGS. 17A and 17B show the structure of the ground short board 10C. Earth short board 10C
A contact terminal 30 that contacts the first terminal 12 and the second terminal 14 of the socket 50 is provided on the lower surface of the socket 50. On the upper surface of the ground short board 10C, each signal wiring pattern 32 that contacts the first terminal of the socket 50 is short-circuited to the ground pattern 36. For this reason, the line impedance of the test signal is
After being short-circuited to the ground, it rapidly decreases. Due to the impedance mismatch, the signal generated by the driver 76A is reflected by the ground short board 10C and detected by the comparator 80A.

FIG. 18 shows still another configuration of the semiconductor test apparatus. In this embodiment, two coaxial cables 62 and 64 are connected to one terminal of the socket 50, and a driver, a driver delay circuit, a comparator, a programmable load, and a comparator delay circuit are connected to each coaxial cable. Have been. In this case, the ground short board 10C is attached to the socket 50, test signals are sequentially generated from the drivers 76 and 77, and the test signals reflected by the socket 50 are detected by the comparators 80 and 90, respectively. Thereby, the line from the driver 76 to the socket 50 and the driver 7
The time difference Δdr of the transmission delay time in the line from 7 to the socket 50 can be obtained. This time difference Δdr
The skew between the drivers 76, the skew between the drivers 77, the skew between the comparators 80, and the skew between the comparators 90 are calibrated by the delay circuits 78, 79, 82, and 83, respectively, based on Can be

FIG. 19 shows a modification of the method for calibrating the semiconductor test apparatus shown in FIG. For the sake of easy understanding, in this figure, the delay circuit 7 shown in FIG.
8, 79, 82, and 83 are omitted. Also, the same components as those shown in FIG. 18 are denoted by the same reference numerals as those in FIG. 18, and the description thereof will be omitted. In the present embodiment, two drivers 76 from one waveform shaper 160,
77 can be provided with a test signal. A gate 162 is provided between the waveform shaper 160 and the driver 77 to control whether or not to pass a test signal.
According to the present embodiment, since it is not necessary to provide a pattern generator, a waveform formatter, and the like for generating a test signal for each of the drivers 76 and 77, the test apparatus can be configured at low cost.

FIG. 20 shows the opening 12 of the frame 100.
FIG. 2 is an enlarged view of a reference numeral 0, a holding unit 110, and a test board 10. The column member 104 of the frame 100 is passed through the holding unit 110, and the holding unit 106 prevents the holding unit 110 from coming off. Holding unit 11
0 can hold the test board 10 or the semiconductor device 20. Holding unit 110 and cylindrical member 10
4, a large clearance is provided, so that each time keeping unit 110 can be freely displaced with respect to the frame 100 within the range of the clearance. The spring 102 presses the holding unit 110 against the socket 50. The socket 50 has a positioning rod 1 having a conical tip.
08 is provided. The positioning rod 108 functions as a loading mechanism for loading each holding unit 110 and the test board 10 to an appropriate position. That is, when the positioning rod 108 is inserted into the positioning hole provided in the holding unit 110, the holding unit is displaced to an appropriate position. For this reason, the first terminal 12 and the second terminal 14 of the socket 50 can accurately contact the contact terminal 30 of the test board 10 or the semiconductor device 20.

FIG. 21 is a top view of the frame 100. At both ends of the frame 100, handles 140 for gripping the frame 100 with human hands or a robot are provided. Each holding unit 110 has a frame 1
Within 00, it can be freely displaced independently of the other holding units 110. Conventionally, the holding unit 11
In order to make each of the 0s surely contact the socket 50, each holding unit was first mounted on the socket, and then the holding unit was fixed from above. According to the present embodiment, when the frame 100 is mounted on the semiconductor test apparatus, each of the holding units 110 is displaced to an appropriate position.
Can be easily attached or detached.

In particular, by preparing a plurality of frames 100 on which necessary types of test boards 10 are mounted in advance and a frame 100 on which the semiconductor device 20 is mounted, a plurality of tests can be performed simply by exchanging the frames 100. The type of the use board 10 can be changed or the semiconductor device 20 can be changed.

In the above embodiment, the semiconductor test apparatus is calibrated by mounting the test board 10 in the socket 50 instead of the semiconductor device 20. According to the above embodiment, since the signal line when actually testing the semiconductor device and the signal line when calibrating the semiconductor test apparatus are substantially the same, the line impedance in each case is substantially equal. Therefore, the semiconductor test apparatus can be calibrated in a state close to actual use. However, other embodiments include, for example, semiconductor device 20 and socket 50.
May be removed from the semiconductor test apparatus, and the test board 10 may be directly attached to the socket board 60. In this case, the line impedance in the actual use state is slightly different from the line impedance at the time of calibration. However, since the socket board 60 has a larger area than the upper side of the socket 50, the probe 44 can be easily brought into contact with the signal line.

FIG. 22 is a top view of the socket board 60 to which the probe board 10D is attached. On the upper surface of the probe board 10D, signal wiring patterns 132 are arranged at a predetermined interval from each other. For this reason, when the signal terminal 40 of the probe 44 is brought into contact, it is possible to prevent the signal terminal 40 from being short-circuited to another signal wiring pattern. An earth pattern 136 is provided on the upper surface of the probe board 10D. The ground pattern 136 is adjacent to each signal wiring pattern 132,
The shortest distance is about 2 mm or less. Therefore, the signal terminal 40 and the ground terminal 42 of the probe 44 can be easily brought into contact with each of the signal wiring patterns 132 and the ground pattern 136. Further, since the shortest distance between each signal wiring pattern 132 and the ground pattern 136 is substantially equal, variation in line impedance of each signal is small, and each signal can be accurately measured.

A large number of test boards 10 to be mounted in place of the semiconductor device 20 and the socket 50 are prepared, and each of them is a holding unit 110 shown in FIG.
May be held. In an actual semiconductor test, in addition to the semiconductor device 20, a socket 50 for the semiconductor device 20 is mounted on the holding unit 110 and further mounted on the frame 100. By preparing each frame 100 to which the required type of test board is attached,
By simply exchanging the frame 100, the types of many test boards 10 can be easily exchanged, or the test boards 10 can be exchanged for the semiconductor devices 20. In the above-described calibration, various terminals need to be brought into contact with each other, but this may be performed not by hand but by a robot. Thereby, not only can a uniform pressure be applied, but also productivity can be improved. Further, in the present embodiment, the test signal is detected by the oscilloscope. However, the test signal may be detected by using, for example, a standard driver and a standard comparator.

As described above, according to the present embodiment, the accuracy of the calibration of the semiconductor test apparatus can be improved. Further, since a plurality of semiconductor devices can be easily mounted on the test apparatus, the productivity of the semiconductor test can be improved.

FIG. 23 shows another embodiment of the test board 10. In FIG. 23, the components denoted by the same reference numerals as those in FIG. 10 have the same configurations as those in FIG. The test board 10 is connected to the pogo pins 204 provided on the test head 70 so that the test head 7
0. The contact terminals 30 formed on the lower surface of the test board 10 are connected to the pogo pins 204 of the test head 70.
Is formed in accordance with the arrangement of. The signal wiring pattern 32 and the ground pattern 36 formed on the upper surface of the test board 10 are formed in accordance with the arrangement of the signal terminal 40 and the ground terminal 42 of the probe 44. The signal wiring pattern 32 and the ground pattern 36 of the test board 10 are electrically connected to the contact terminals 30. In this manner, by arranging the contact terminals 30 of the test board 10 in accordance with the arrangement of the terminals of the socket board 60, the performance board 66, or the test head 70, not only can the test board 10 be mounted on the socket 50, but also the socket It can be mounted on the board 60, the performance board 66, or the test head 70.

The test head 70 includes a test apparatus main body 208.
, A test signal of a predetermined level is generated, and the test signal is supplied to the test board 10 via the pogo pin 204. The test head 70 includes the pin electronics 206 therein. Pin electronics 206
Has a plurality of drivers 76, a driver delay circuit 78, a comparator 80, and a comparator delay circuit 82 (not shown). The oscilloscope 200 is a measuring instrument calibrated in advance. The oscilloscope 200 and the test apparatus main body 208 are connected by communication means such as GPIB that can be controlled bidirectionally. Therefore, measurement can be performed under desired conditions, and the timing data of the measurement result is used in the test apparatus main body 208 for calibration data or determination processing. The test apparatus main body 208 has a main body delay circuit 210 and can adjust set values of delay times of the driver delay circuit 78 and the comparator delay circuit 82 included in the pin electronics 206.

The reference pulse signal 220 is input to the trigger input terminal of the oscilloscope 200 from the reference signal terminal 221 provided in the test head 70. Reference pulse signal 2
20 adjusts the timing at which the driver 76 outputs the test signal. The signal terminal 40 and the ground terminal 42 of the probe 44 connected to the oscilloscope 200 are in contact with and electrically connected to the signal wiring pattern 32 and the ground pattern 36 of the test board 10.

FIG. 24 is a connection diagram of the semiconductor test apparatus shown in FIG. The test board 10 includes a pogo pin 204 provided at the output end P1 of the pin electronics 206.
At the contact terminal 30 and are electrically connected. Calibration is performed so that the timing at which the plurality of drivers 76 output the test signals in the signal wiring pattern 32 of the test board 10 is the same for all drivers.

FIG. 25 is a flowchart showing a method for calibrating the semiconductor test apparatus shown in FIG. 23 or FIG. However, the calibration method shown in this flowchart is not limited to the semiconductor test device shown in FIG. 23 or FIG. 24, and a signal obtained from the measurement target by contacting the probe 44 with the measurement target is measured outside the test device. Applicable to a test device that measures with an instrument. In the conventional calibration method, there was a possibility that a contact failure between the probe 44 and the measurement target could not be detected.
Therefore, in the present embodiment, before the calibration of the driver 76, the contact between the probe 44 and the measurement target is checked.

First, the signal terminal 40 and the ground terminal 42 of the probe 44 are brought into contact with the signal wiring pattern 32 and the ground pattern 36 of the test board 10 (S302).
Next, while the probe 44 is in contact with the test board 10, the slew rate value, which is the time required for the rise or fall of the waveform of the test signal output from the driver 76, is calculated using the oscilloscope 200 connected to the probe 44. (S304). The quality of the contact check between the probe 44 and the test board 10 may be determined by either rising or falling of the waveform. Next, it is determined whether or not the measured slew rate value is within a range of a desired slew rate value, and the process branches (S306).

If it is determined in the slew rate determination step (S306) that the slew rate value is out of the desired range, the probing step (S302)
The slew rate measuring step (S304) and the slew rate determining step (S306) are repeated a predetermined number of times.
Further, it is determined whether the probing step (S302), the slew rate measuring step (S304), and the slew rate determining step (S306) have been repeated a predetermined number of times (S322). If it is determined that the slew rate value is out of the desired range even after repeating the probing step (S302), the slew rate measuring step (S304), and the slew rate determining step (S306) a predetermined number of times, the probe 44 A faulty contact between the test board 10 and the test board 10 is notified to the outside of the semiconductor test apparatus (S326).
The test operator inspects the connection failure portion of the transmission line between the driver 76 and the test board 10 to remove dust.

FIG. 26 shows a slew rate measurement step (S
3 shows three types of probing contact waveforms in the case of the rising edge of the waveform measured in 304). The first waveform S ₀ is a case where the contact state is good, and the second waveform S ₄ is an example where the ground terminal 42 of the probe 44 and the ground pattern 36 of the test board 10 are open. third waveform S ₆ is an example of a case where there is a high contact resistance of a few hundred Ω between the ground terminal 42 and the earth pattern 36. The slew rate value is obtained by calculating the difference between the times when the waveform levels reach the respective thresholds, using the 20% and 80% levels as thresholds for the 100% level.

[0067] slew rate value T in the first waveform _{S 0}
r1 is a case where it substantially matches the normal slew rate value, and it can be easily determined that the contact state is good. Then slew rate value Tr3 in the second waveform _{S 4}
Indicates a slew rate value several times the normal slew rate value Tr1. Therefore, it can be determined that the ground terminal 42 and the ground pattern 36 are in poor contact. Also,
Shows the slew rate of several times the slew rate Tr1 also normal in the slew rate value Tr2 in the third waveform S _6. Therefore, also in this case, it can be determined that the ground terminal 42 and the ground pattern 36 are in poor contact.

As still another embodiment, instead of measuring a slew rate value, a desired threshold range is set based on the level of a normal signal at a specific time within a rising or falling period of a test signal. Thus, the contact failure may be determined based on whether or not the measured signal level falls within a desired threshold range. For example, when the timing of measuring the waveform level is Ts and the range of the threshold is a level within 20% from the level of 100% of the normal signal, that is, a level of 80% or more of the normal signal,
Although the level of the waveform S ₀ is within the range of the threshold, the waveform S ₆ and the waveform S ₄ is deviated from the range of the threshold value. Therefore, in the waveform S ₀ has a good contact state, in the waveform S ₆ and S _4, can determine the contact state is defective.

FIG. 27 shows a schematic diagram and a connection diagram of a semiconductor test apparatus for showing still another embodiment of the calibration method. 27A and 27B, FIG.
Configurations denoted by the same reference numerals as in FIGS. 3 and 24 have the same configurations as in FIGS. The performance board 66 is installed so as to be in contact with the pogo pins 204, and is electrically connected to the pogo pins 204. The socket 50 on which the semiconductor device 20 or the test board 10 is mounted is connected to a performance board 66 by a coaxial cable 64. The socket 50 transmits the test signal generated by the driver 76 in the pin electronics 206 to the pogo pin 204 and the performance board 6.
6, and input through the coaxial cable 64 to the semiconductor device 20 or the test board 10. In the semiconductor test apparatus shown in FIG. 27, there is a possibility that a contact failure occurs at a contact point 272 between the pogo pin 204 and the performance board 66.

FIG. 28 is a flowchart showing an embodiment of the calibration of the semiconductor test apparatus shown in FIG. First, the reflected waveform output from the driver 76 and reflected from the socket 50 is input using the comparator 80 connected to the driver 76, and the reflected waveform input from the comparator 80 is measured in the test apparatus main body 208. (S404). Next, the test apparatus main body 208 determines whether the measured reflected waveform is within a desired range, and if it is determined to be defective, the process branches to a loop count determination step (S322) (S406).

When it is determined that the reflection waveform is out of the desired range, the performance board 66 and the pogo pin 204 are re-contacted (S424), and the reflection waveform measurement step (S404) and the reflection waveform determination step (S40)
Repeat 6). Next, a re-contact step (S424),
It is determined whether the reflection waveform measurement step (S404) and the reflection waveform determination step (S406) have been repeated a predetermined number of times (S322). If the measured waveform is determined to be out of the desired range even after repeating the re-contact step (S424), the reflected waveform measuring step (S404), and the reflected waveform determining step (S406) a predetermined number of times, the performance is determined. The contact failure between the board 66 and the pogo pins 204 is notified to the outside of the semiconductor test apparatus (S326).

FIG. 29 shows a reflection waveform measuring step (S40).
An example of the reflection waveform measured in 4) is shown. It is transition waveform _{S 10} that shown in FIG. 29 (B) is measured in reflection waveform measuring step (S404). Transition waveform S ₁₀ is a transition waveform of the normal case. The transition of the reflected waveform is determined by the output of the driver 76 and the length of the transmission line. That is, as shown in FIG.
₁₀ changes at a level V2 which is half of the level V4 at first, and reaches the level V4 after a lapse of a round-trip time T1 during which a pulse reciprocates in the transmission line. Is used as a basis for transition waveform S ₁₀ is compared with the measured transition waveform S _12. In reflected waveform determination step (S406), it changes the data of the waveform S _12, the difference between the transition waveform S ₁₀ serving as a reference is calculated, acceptability of the waveform from the distribution D ₁₀ is the difference amount is determined.

The calibration method shown in FIGS. 28 and 29 is also applicable to the calibration method of generating a reflection signal using the ground short board 10C shown in FIGS. 17, 18, and 19. FIG.
Even when the test board 10 shown in FIG. 3 is mounted at a place other than the socket 50, the reflection signal can be generated by using the ground short board 10C as the test board 10, so that the present invention is applicable.

FIG. 30 shows another embodiment of the calibration method for the comparator 80. Probe 4
23 is connected to the reference signal terminal 221, and the reference pulse signal 220 input from the reference signal terminal 221 is applied to the test board 10 via the probe 44. It is. As a method of calibrating the comparator 80, there is a method in which a reference pulse signal 220 is supplied to the test board 10 as a reference timing to input the reference timing to a plurality of comparators 80 and perform calibration. In the calibration method of the comparator 80,
The method for detecting a contact failure described with reference to FIGS. 25 and 26 can be applied. For example, the probe 44 and the test board 10
If there is poor contact between, the comparator 80, the reference pulse signal 220 of similar waveform to the waveform S ₄ or S ₆ shown in FIG. 26 are input. In this case, as in the description of FIG. 26, for example 1 of the waveform S ₀
The time required for each waveform to reach the threshold level may be measured using the 20% and 80% levels as thresholds for the 00% level. By calculating the difference between the measured times, the slew rate value can be calculated, and the difference from the slew rate value Tr1 in a normal state can be obtained. Therefore, similarly to the calibration of the output timing of the driver 76, the contact failure between the probe 44 and the test board 10 can be detected by the comparator 80.

As still another embodiment, in the same manner as described with reference to FIG. 26, instead of measuring the slew rate value, the level of the normal signal within the rising or falling period of the test signal is used to determine the desired threshold value. Set the range,
The contact failure may be determined based on whether or not the measured signal level falls within a desired threshold range.

As described above, the present invention has been described using the embodiments. However, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is apparent to those skilled in the art that various changes or improvements can be made to the above embodiment. It is apparent from the description of the appended claims that embodiments with such modifications or improvements are also included in the technical scope of the present invention.

[Brief description of the drawings]

FIG. 1 is a sectional view of a conventional semiconductor test apparatus.

FIG. 2 is a top view and a front view of the semiconductor device 20.

FIG. 3 is a sectional view showing a socket 50 and a socket board 60 on which the socket 50 is mounted.

4 is a top view of the socket board 60. FIG.

FIG. 5 shows a state in which a probe 44 is applied to the socket board 60.

FIG. 6 shows another conventional method for calibrating a semiconductor test apparatus.

FIG. 7 shows still another embodiment of the conventional semiconductor test apparatus.

FIG. 8 shows a flowchart of a conventional calibration method.

FIG. 9 shows a waveform of a test signal measured in a timing measurement step (S310).

FIG. 10 shows a cross section of the entire semiconductor test apparatus according to the present embodiment.

11A and 11B are a top view and a bottom view of a probe board 10A as an example of the test board 10 mounted on the holding unit 110.

FIG. 12 is a short board as another example of the test board 10.

FIG. 13 shows another embodiment of the semiconductor test apparatus.

FIG. 14 shows a method for easily obtaining a signal transmission time from the socket 50 to the comparator 80B.

FIG. 15 shows still another embodiment of the semiconductor test apparatus.

FIG. 16 shows a configuration of an earth short board 10C.

FIG. 17 shows still another configuration of the semiconductor test apparatus.

FIG. 18 shows a modified example of a method of calibrating the semiconductor test apparatus shown in FIG.

FIG. 19 is an enlarged view of the opening 120 of the frame 100, the holding unit 110, and the test board 10.

20 is a top view of the frame 100. FIG.

FIG. 21 is a top view of the socket board 60 to which the probe board 10D is attached.

FIG. 22 shows still another embodiment of the semiconductor test apparatus.

FIG. 23 shows another embodiment of the test board 10.

24 shows a connection diagram of the semiconductor test apparatus shown in FIG.

FIG. 25 is a flowchart showing a method of calibrating the semiconductor test device shown in FIG. 23 or 24.

FIG. 26 shows a waveform measured in a slew rate measuring step (S304).

FIG. 27 shows a schematic diagram and a connection diagram of a semiconductor test apparatus for showing still another embodiment of the calibration method.

FIG. 28 is a flowchart illustrating an embodiment of a calibration method of the semiconductor test apparatus illustrated in FIG. 27;

FIG. 29 shows an example of a reflected waveform measured in a reflected wave measuring step (S404).

FIG. 30 shows another embodiment of a calibration method for the comparator 80.

[Explanation of symbols]

10 Test Board 10A Probe Board 10B Short Board 10C Ground Short Board 10D Probe Board 12 First Terminal 14 Second Terminal 20 Semiconductor Device 30 Contact Terminal 32 Signal Wiring Pattern 36 Ground Pattern 40 Signal Terminal 42 Ground Terminal 44 Probe 46 Short Pattern 50 Socket 52 pin 54 pin 56 through hole 58 socket guide 59 through hole 60 socket board 62 coaxial cable 64 coaxial cable 66 performance board 70 test head 76 driver 77 driver 78 delay circuit 79 delay circuit 80 comparator 90 comparator 82 delay circuit 83 delay circuit 100 Frame 102 Spring 104 Column member 106 Fastener 108 Positioning rod 110 Holding unit 12 Opening 132 Signal wiring pattern 136 Ground pattern 140 Handle 150 Oscilloscope 160 Waveform shaper 162 Gate 180 Programmable load 200 Oscilloscope 204 Pogo pin 206 Pin electronics 208 Test apparatus main body 210 Main body delay circuit 220 Reference pulse signal 221 Reference signal end 222 Reference driver S302 Probing Step S304 Slew rate measurement step S306 Slew rate determination step S310 Timing measurement step S312 Test signal generation step S314 Rising waveform measurement step S316 Falling waveform measurement step S322 Loop number determination step S424 Recontact step S326 Failure notification step S404 Reflection waveform measurement step S406 Reflection waveform judgment step Flops _{S 0, S 1, S 2} , S 4, S 6 waveform S _{10, S 12} transition waveform t ₀ reference timing position t _{1, t 2} timing e _{1, e 2} timing deviation D ₁₀ distribution V2 half level V4 Level T1 Round trip time

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G01R 31/28 PR (72) Inventor Hiroyuki Nagai 1-32-1 Asahimachi, Nerima-ku, Tokyo Stock Association Inside Advantest (72) Inventor Hiroyuki Shiozuka 1-32-1 Asahicho, Nerima-ku, Tokyo Co., Ltd. Inside Advantest (72) Inventor Hiroyuki Hama 1-32-1 Asahimachi, Nerima-ku, Tokyo Co., Ltd. Advantest (72) Inventor Eiichi Sekine 1-32-1 Asahicho, Nerima-ku, Tokyo Within Advantest Co., Ltd. (72) Inventor Toshikazu Suzuki 1-32-1 Asahicho, Nerima-ku, Tokyo Advantest Co., Ltd. (72) Inventor Ko ▲ zuka ▼ Kiyoshi 1-32-1 Asahicho, Nerima-ku, Tokyo Advantest Co., Ltd. (72) Inventor Yukio Ishigaki Nerima-ku, Tokyo Town 1-chome No. 32 No. 1 stock company within the Advantest

Claims (36)

[Claims] 1. A socket having a first terminal to which a semiconductor device is mounted and a test signal used for testing the semiconductor device can be given to the semiconductor device, and the test signal is output to the first terminal. A calibration method for calibrating the output timing of the test signal in a semiconductor test apparatus having a driver, wherein a mounting step of mounting a test board having a pin arrangement similar to the pin arrangement of the semiconductor device to the socket. A generating step of generating the test signal by the driver, a detecting step of detecting the test signal reaching the test board, and an output timing of the test signal based on the test signal detected by the detecting step. Setting step of setting Calibration method. 2. The test board according to claim 1, wherein a pin that contacts the first terminal has the same input impedance as a pin of the semiconductor device that contacts the first terminal. Calibration method. 3. In the test board, a contact terminal that contacts the first terminal is connected to a ground pattern, and the detecting step includes the step of outputting the test signal output from the driver and reflected by the test board. The calibration method according to claim 1, further comprising the step of: 4. The calibration method according to claim 1, wherein the mounting step includes a step of measuring a DC resistance between the socket and the test board to check for a contact failure. 5. The semiconductor test apparatus further comprises a comparator for receiving the test signal from the test board, wherein the mounting step includes the step of comparing the test signal output from the driver and reflected by the test board with the comparator. A reflected wave measuring step of measuring by the comparator; a reflected waveform determining step of determining whether a waveform of the test signal measured by the comparator is within a desired range; and the waveform measured by the comparator being the desired range. A notification step of notifying a connection failure of a transmission line from an output end of the driver to the test board when the connection is disconnected.
Calibration method described in 1. 6. The semiconductor test apparatus further includes a delay circuit that delays the test signal, and the generation step includes:
Outputting the test signal by the driver and generating a predetermined reference signal, wherein the setting step is based on a phase difference of the test signal detected by the detection step with respect to the reference signal. 2. The calibration method according to claim 1, further comprising a delay setting step of setting a magnitude of the delay added by the delay circuit. 7. The test board has a signal wiring pattern that contacts the first terminal, and an earth pattern disposed adjacent to the signal wiring pattern, and the detecting step includes: 7. The calibration method according to claim 6, further comprising a step of detecting the test signal using an electrical characteristic test probe attached to the ground pattern. 8. The calibration according to claim 7, wherein the mounting step includes a step of measuring a DC resistance between the electrical characteristic test probe and the test board to check a contact failure. Method. 9. The mounting step includes an inspection step of checking a contact failure between the electrical characteristic test probe and the test board, and the inspection step includes: testing the electrical characteristic test probe by the test. A probing step of bringing the test signal into contact with a test board, a waveform measuring step of measuring the test signal detected by the electrical characteristic test probe in an external measuring instrument, and the test signal measured by the external measuring instrument. A waveform determining step of determining whether the waveform is within a desired range, and when the waveform measured by the external measuring device is out of the desired range, the electrical characteristic test probe and the A notification step of notifying a contact failure with the test board. 10. The socket further has a second terminal that contacts the semiconductor device and receives an electrical signal from the semiconductor device, and the semiconductor test apparatus receives a signal input from the second terminal. The calibration method according to claim 1, further comprising a comparator, wherein the test board is a short board having a short pattern for electrically connecting the first terminal and the second terminal. 11. The detecting step includes detecting the test signal output from the driver and passing through the short board by the comparator, a reference timing having a predetermined time difference from the generation step, and the comparator detecting step And a reference time setting step of setting a value obtained based on a time difference from a time when the test signal is detected in the comparator as a reference time for testing the semiconductor device. The calibration method according to claim 10, wherein the calibration is performed. 12. A socket having a first terminal capable of supplying a test signal to the semiconductor device by mounting the semiconductor device, and a second terminal receiving an electrical signal from the semiconductor device; A calibration method for calibrating the processing timing of a semiconductor test device having a driver that outputs to a terminal and a comparator that receives a signal input from the second terminal, wherein the first terminal and the second terminal are connected to each other. Mounting a short board having a short pattern to be electrically connected to the socket; outputting the test signal from the driver; and outputting the test signal output from the driver via the short board to the comparator. Measuring step, and the output step. A reference timing having a predetermined time difference with respect to the pump, and a value obtained based on a time difference between the time when the test signal is measured in the measurement step and the reference time for testing the semiconductor device. A calibration method. 13. The semiconductor test apparatus has a plurality of the drivers and a plurality of the comparators, and the socket has a plurality of the first terminals respectively associated with the plurality of the drivers, and a plurality of the comparators. A plurality of the second terminals associated with each of the plurality of the second terminals, the short board includes a plurality of the short patterns respectively connecting the plurality of the first terminals and the plurality of the second terminals, and the reference time 13. The calibration method according to claim 12, wherein the setting step sets the reference time independently for each of the plurality of comparators. 14. A driver for outputting a test signal used for testing a semiconductor device, a comparator for receiving an electric signal from the semiconductor device, and attaching the semiconductor device to apply the test signal to the semiconductor device. A calibration method for calibrating the processing timing of a semiconductor test apparatus having a socket capable of performing a test, wherein the test signal or the electrical signal is required to be provided to a measuring instrument for measuring a waveform of the test signal. A connection step of making a connection; a waveform measurement step of measuring the test signal output by the driver with the measurement device; and a waveform determination for determining whether the waveform of the test signal measured by the measurement device is within a desired range. And the step wherein the waveform measured by the measuring device is out of the desired range. Calibration method which is characterized in that the connection went to the instrument when is a notification step of notifying that the defect are. 15. The calibration method according to claim 14, wherein the waveform measuring step measures at least one of a rising edge and a falling edge of the test signal. 16. The re-connecting step of repeating the connecting step, the waveform measuring step, and the waveform determining step when the waveform is out of the desired range, the connecting step, A waveform measuring step, and a failure notifying step of notifying that the connection made to the measuring instrument is defective when the waveform is out of the desired range even if the waveform determining step is repeated a predetermined number of times. 15. The calibration method according to claim 14, wherein: 17. The method according to claim 17, wherein the measuring device is a measuring device external to the semiconductor test apparatus, the measuring device includes an electrical characteristic test probe for inputting the test signal, and the connecting step includes: The method of claim 14, further comprising the step of making the necessary connections to provide a test probe with the test signal. 18. The measuring device, wherein the measuring device is a measuring device inside the semiconductor test apparatus, and the waveform measuring step is performed by inputting the test signal output from the driver and reflected by the socket from the comparator from the comparator. 15. The calibration method according to claim 14, further comprising the step of: 19. The measuring device is a measuring device inside the semiconductor test apparatus, and the waveform measuring step includes a step of measuring a predetermined reference signal input from the comparator by the measuring device. The calibration method according to claim 14, wherein the calibration is performed. 20. The method according to claim 14, wherein the connecting step includes a step of connecting a test board to which the test signal is input and supplied to the measuring device for the calibration, to the measuring device. 20. The calibration method according to any one of 19. 21. The measuring device, wherein the measuring device is a measuring device inside the semiconductor test apparatus, wherein the waveform measuring step comprises: receiving the test signal output from the driver and reflected by the test board from the comparator. 21. The calibration method according to claim 20, further comprising a step of measuring with the measuring device. 22. The method according to claim 14, wherein the waveform determining step determines whether a level of the test signal is within a desired range during a rising or falling period of the test signal. Calibration method described in 1. 23. A semiconductor testing apparatus for testing electrical characteristics of a semiconductor device, comprising: a socket having a first terminal for contacting an electrical terminal of the semiconductor device and providing a signal to the semiconductor device;
A test board that has a pin arrangement similar to that of the semiconductor device and can be mounted on the socket, a driver that outputs a test signal to the first terminal, and the test board that is output from the driver And a setting unit for setting an output timing at which the driver outputs the test signal using the test signal that has arrived at the semiconductor test apparatus. 24. The semiconductor according to claim 23, wherein the test board has a signal wiring pattern contacting the first terminal, and an earth pattern arranged adjacent to the signal wiring pattern. Testing equipment. 25. The test board has a signal wiring pattern that contacts the first terminal and connects to the ground, and the setting means outputs the test signal output from the output means and reflected by the test board. The semiconductor test apparatus according to claim 23, wherein the output timing is set using a signal. 26. The test board, wherein the test board has the same input impedance as a pin of the semiconductor device.
24. The semiconductor test apparatus according to claim 23, further comprising a test pin that contacts the terminal. 27. A delay circuit for providing a desired delay to the test signal, wherein the setting means includes a generating means for outputting the test signal and generating a predetermined reference signal, 24. The semiconductor test apparatus according to claim 23, wherein the output timing is set by setting a magnitude of the output timing. 28. The semiconductor device further comprising: a plurality of the drivers; and a plurality of delay circuits associated with the plurality of drivers, and the socket has a plurality of the first terminals associated with each of the plurality of drivers. 25. The semiconductor test apparatus according to claim 24, wherein the test board has a plurality of the signal wiring patterns associated with each of the plurality of first terminals. 29. The semiconductor test apparatus according to claim 28, wherein the shortest distance between each of the plurality of signal wiring patterns and the ground pattern is substantially the same. 30. The socket further includes a second terminal that contacts the semiconductor device and receives an electrical signal from the semiconductor device, and a short circuit that electrically connects the first terminal and the second terminal. 24. The semiconductor test apparatus according to claim 23, further comprising a short board having a pattern, and a comparator that detects the test signal output from the driver and passing through the short board. 31. A method for testing a value of a value obtained based on a time from a reference timing having a predetermined time difference to an output of the test signal until the comparator detects the test signal, for testing the semiconductor device. 31. The semiconductor test apparatus according to claim 30, further comprising: reference time setting means for setting the reference time for the comparator. 32. The semiconductor device further comprising: a plurality of the drivers; and a plurality of the comparators, wherein the socket is associated with each of the plurality of first terminals and the plurality of comparators associated with each of the plurality of drivers. A plurality of the second terminals, the short board includes a plurality of the short patterns that respectively connect the plurality of the first terminals and the plurality of the second terminals, and the reference time setting unit includes: 32. The semiconductor test apparatus according to claim 31, wherein the reference time is set independently for each of the plurality of comparators. 33. The apparatus further comprising: a plurality of the sockets; a plurality of the test boards corresponding to each of the plurality of the sockets; and a frame that integrally holds the plurality of the test boards. 24. The semiconductor test according to claim 23, wherein each of the test boards has a call-in mechanism for moving the test board to a desired position when a frame is mounted at a predetermined position in the semiconductor test apparatus. apparatus. 34. A semiconductor test apparatus for testing electrical characteristics of a semiconductor device, comprising: a first terminal that contacts the semiconductor device to apply an electrical signal to the semiconductor device; and a semiconductor terminal that contacts the semiconductor device. A socket having a second terminal for receiving an electric signal from a device; a driver for outputting a test signal to the first terminal; a short board for electrically connecting the first terminal and the second terminal; A comparator for receiving a signal input from two terminals, a means for detecting the test signal output from the driver via the short board by the comparator, and a predetermined time difference with respect to the output of the test signal by the driver. And a reference timing having the same, and a time difference obtained based on a time difference between a time when the comparator detects the test signal. Means for setting the obtained value as a reference time for testing the semiconductor device to the comparator. 35. A semiconductor device comprising: a plurality of said drivers; and a plurality of said comparators, wherein said socket is a plurality of said first terminals associated with each of said plurality of drivers and a plurality of said plurality of said terminals associated with said plurality of comparators. The short board has a plurality of the signal wiring patterns respectively connecting the plurality of the first terminals and the plurality of the second terminals, and the reference time setting means includes a plurality of the comparators 35. The semiconductor test apparatus according to claim 34, wherein the reference time is set independently for each of the following. 36. The apparatus further comprising: a plurality of the sockets; a plurality of the short boards corresponding to each of the plurality of the sockets; and a frame for integrally holding the plurality of the short boards. 35. The semiconductor test apparatus according to claim 34, wherein each of the short boards has a call-in mechanism for moving the short board to a desired position when the short board is mounted at a predetermined position.