JPH02227680A - Lsi tester - Google Patents

Abstract

PURPOSE:To reduce the size of a test head which is never reduced in test speed by providing the test head with a buffer amplifier additionally. CONSTITUTION:This tester is separated into the test head 20 where DUTs (LSI to be inspected) 7 are mounted one after another and an LSI tester main body 10 provided with a comparator 2 which receives an output signal from the same terminal of a driver 1 for applying high frequency pulses to the terminal of the DUT. Then a signal line 3 is coated double with internal and external shields 4 and 5 and the terminal of the DUT 7, the driver 1, and the comparator 2 are connected by a double shield wire 30 whose shield 5 is connected to a common potential. A high-input-impedance buffer amplifier 6 provided to this head 20 receives the potential of the signal line 3 at its input terminal and connects the output terminal having the same potential with the signal line 3 to the shield 4. Therefore, a capacitor C1 does not operate as a load and never delays a signal.

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to an LSI tester. To explain in detail, the LSI tester body and DUT (Device Under Te
LS that can reduce the influence of transmission line capacity, which hinders high-speed performance, when transmitting high-speed signals between 5t) and can respond quickly.
Regarding I tester.

<Prior art> In an LSI tester, a high-speed pattern signal (high-frequency pulse train signal) is applied from a high-speed driver (hereinafter simply referred to as driver) to a certain terminal (for example, NO1 bin) of the DUT, and the unique function of this 0131 is applied. Based on the high-speed comparator (hereinafter simply referred to as a comparator), the high-speed signal output from another terminal of the DUT or the same terminal (N01 bin)
A judgment is made to determine whether the product is good or bad.

The driver applies a pulse signal to the DUT at a timing instructed by a computer provided in the main body of the LSI tester, for example. The comparator compares the output signal of the DUT with a certain voltage level at a timing commanded by the computer, for example, and outputs the result.

The LSI is called the so-called I10 pin, and the same terminal pin has the function of being both an input terminal and an output terminal.

Two examples of this 110 pin will be explained.

Example 1> For example, a certain pattern A on the terminal pin of NO1
When a pulse train signal having a pattern B is added, a signal generated by the function of this LSI (this signal is often a signal having a certain pattern B) is output from the terminal bin of N05. This time, for example, if a pulse train signal with pattern C is applied to the terminal bin NO3, this L
Outputs a signal generated by another function of the SI. In this way, the NO1 terminal sometimes operates as an input terminal,
At some times, it operates as an output terminal.

Example 2> For example, a certain pattern D on the terminal bin of NO4
When a pulse train signal having a function is added, a pulse signal may be output from the terminal bin of NO4 at a certain timing due to the unique function of this LSI. In this case, NO
Terminal bin 4 switches from input pin to output pin at high speed. It is necessary to measure the pulse signal output from this LSI with a comparator.

As I know above, since LSI has I10 bin, LSI can be inspected no matter which terminal bin is I10 bin.
The SI tester is configured to connect a bare circuit with a driver and a comparator for each terminal of the LSI.

However, the driver and comparator in this pair do not usually operate at the same time; when the driver operates, the comparator stops its operation, and when the comparator operates, the output of the driver is set to the "old GH impedance". For example, it is controlled by the computer.

FIGS. 2 and 3 show the main parts of such an LSI tester.

In Figures 2 and 3, 10 is the main body of the LSI tester, which includes a computer that controls the LSI tester, a memory that stores various programs for testing the DUT, and an interface.
It includes a measurement module that applies various electrical signals to T and measures signals from the mouth U. Signal flow between these components and the LSI tester main body 10
Since the operation is not directly related to the present invention, the explanation of the LSI tester main body will be limited to this.

20 is a test head, which is a board equipped with an IC socket (not shown) into which DUTs are successively inserted.

Here, the LSI tester main body 10 and the test head 20 are normally placed at a convenient position. I will explain the reason.

DUTs are inserted one after another into the IC socket of the test head 20 from the handler (not shown), so the test head 20 is highly coupled to the handler. A MIB η-bar (not shown) is used, but in this case, a signal is applied from the prober to the test head 20, so the test head 20 has a strong coupling with the 10-bar. Although it is installed along the flow of the line, the main body of the LSI tester is not integrated with the handler or prober, so it is placed at a separate location.

There is a strong demand for the test head 20 to be made smaller due to restrictions on connection with a handler or a prober.

As a result of the above, the LSI tester main body 10 and the test head 20 are connected by a line 8 in FIG. 2, and are connected by a line composed of a signal line 41 and a shield 42 in FIG. Of course, the line 8 is often a shielded wire or a twisted wire.

The difference between Figures 2 and 3 will be explained. As mentioned above, the LSI tester applies a high-speed pattern signal from the driver 1 to the DUT 7. Further, the high speed signal output from the DUT 7 is determined by the comparator 2.

FIG. 2 shows this driver 1, comparator 2, and its control element 3 mounted on a test head 20.

With this configuration, driver 1 and DUT? ,D
Since the uT 7 and the comparator 2 are placed in close proximity, they are in good condition for transmitting signals at high speed. A good state for high-speed transmission means that the equivalent capacitance C^ connected to the DUT 7 is small, as shown in FIG. That is, driver 1 and DUT 7
, DUT 7 and comparator 2 are close to each other, so the line between them is short and the line capacitance C^ is small.

However, the configuration shown in FIG. 2 has a problem in that the driver 1, comparator 2, and control element 3 are arranged on the test head 20, which hinders miniaturization of the test head 20.

On the other hand, in Fig. 3, driver 1 and comparator 2 are integrated into LSI.
It is incorporated into the tester main body 10. Therefore, the test head 20 can be made much smaller than the configuration shown in FIG. The configuration shown in FIG. 3 is called a remote drive system because signals are transmitted between the drivers 1 and 0017, the DUT 7, and the comparator 2, which are located at separate locations.

However, in the configuration of FIG. 3, the capacitance CB formed between the signal line 41 and the shield 42 becomes large, and this capacitance CB becomes D.
Since it is connected to the terminal of the UT, there is a problem that the high-speed pulse is significantly delayed. This will be explained with reference to FIGS. 4 and 5.

BACKGROUND ART In recent years, devices (LSI) have become increasingly low-power, and the number of devices with large output impedance has increased.

If a large capacitive load is connected to such a device, the rise of the output signal will be delayed.

FIG. 4 is a diagram in which the DUT 7, shield wire, and comparator 2 of FIG. 3 are extracted. The shield wire is signal wire 41
An insulator is provided between the shield 42 and the capacitance CB shown in the figure. Therefore, when the signal shown in Fig. 5 (1) is output from the DUT 7 whose output impedance is R, the signal shown in Fig. 5 (2) is transmitted to the comparator 2 due to the delay of the time constant τ = R CB. It arrives as a waveform. If the comparator 2 is, for example, FIG.
) is determined to be the "old Gll" level, even if the DUT 7 outputs the signal shown in Fig. 5 [1], the comparator 2 recognizes this signal as Fig. 5 (3). . In other words, a delay time occurs (Fig. 5 (3)
reference).

At the stage of inspecting the LSI, the driver
A high-speed pattern signal is applied to T, and it is possible to know in advance at which timing a signal that becomes "old GH" or "[OI4"] will be output in response to the added pattern signal if the DUT is of good quality. Therefore, in the Sl tester, a strobe signal instructing this timing is sent to the comparator 2, and the output of the comparator when this strobe signal is applied is read to determine the quality of the DUT.

Here, it is assumed that the DUT 7 outputs the pattern signal shown in FIG. 6(1), and a strobe signal is applied to the comparator 2 at the timing shown in FIG. 6(2). However, since the signal is delayed due to the influence of the capacitor CB shown in FIG. 4, the comparator 2 recognizes the waveform in FIG. 6(1) as the waveform in FIG. 6(3). Therefore, for example, in strobe signals 21 and 22, the signals actually output by the DUT (Fig. 6 (
1)) and “Old 6H” ”” to praise” will be judged.

In order to prevent such misjudgment, the delay time τ shown in Figure 5 ■
Since it is necessary to apply a low-speed pattern signal from the driver 1 to the DUT 7 that does not cause any influence, the test speed becomes slow. The time it takes to select good LSIs from a huge number of LSIs has a significant impact on the price of the LSI, so it is time consuming.

<Problems to be Solved by the Invention> As described above, the configuration shown in FIG. 2 has the problem that the test head 20 becomes large, and the configuration shown in FIG. 3 has the problem that the testing speed of the DUT is slow.

SUMMARY OF THE INVENTION An object of the present invention is to provide an LSI tester whose test head can be made smaller without reducing test speed.

Means for Solving the Problems> In order to solve the above problems, the present invention provides a test head (20) in which LSIs to be tested (hereinafter simply referred to as DtlT) are mounted one after another, and a test head (20) that In an LSI tester separated into an LSI tester main body (10) equipped with a driver (1) that applies a high-frequency pulse signal to a terminal and a comparator (2) that receives a signal output from the same terminal of this DUT, the inner shield and A wire in which the signal wire is double coated with an outer shield, and the above-mentioned Dt
A certain terminal of the jT is connected to a comparator, and the same terminal of this DUT and a driver are connected by a signal line, and a double shielded line whose outer shield is connected to a common potential is connected to the input terminal provided in the test head (20). A high input impedance buffer amplifier is introduced, and an output terminal with the same potential as the signal line potential is connected to the inner shield.

Effect> Since the buffer amplifier keeps the potential of the inner shield always the same as that of the signal line, the capacitor C1 existing between the signal line and the inner shield is never charged with electric charge, that is, DjlT 7 When viewed from above, the capacitance C1 in the double shielded line does not act as a load and no signal delay occurs.

□〈Example〉 Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a diagram showing an embodiment of an LSI tester according to the present invention.

In FIG. 1, l is a driver, 2 is a comparator, and 7
jlllT, a 10-chip LSI f-star body, and 20 a test head, which are the same as those already explained in the conventional example, and therefore will not be explained again.

That is, the present invention employs a remote drive system in which the driver 1 and comparator 2 are provided inside the S1 tester body.6 The configuration described next is different from the conventional example.

In the present invention, the driver 1 and the DUT 7 and the DUT 7 and the comparator 2 are connected by a double shielded wire 30. That is, the output terminal of the driver 1 and the input terminal of the comparator 2 are connected to D via the signal line 3 of the double shield line 30.
Connected to a certain terminal of uT 7. and outer shield 5
One end (d) of is connected to the common potential of the LSI tester main body 10, and 1t! of the outer shield 5! ! The end (C) is connected to the common potential of the test head 20.

Further, in the present invention, the test head 20 is equipped with a buffer amplifier 6 having a high input impedance and an amplification degree of 1. This buffer amplifier 6 has an input terminal connected to a signal line 3 near the DUT 7, and an output terminal having the same potential as the signal line 3 connected to the inner shield 4.

The first [! The LSI tester operates as follows.

Since the signal line 3 and the inner shield 4 are always at the same potential due to the action of the buffer amplifier 6, the signal line 3 and the inner shield 4
Therefore, if the DUT 7 outputs a high-speed pattern signal with a waveform like that shown in Figure 6 (1), the waveform will not be charged to the capacitor in the middle of the path. Reaches comparator 2 unaffected (without delay).

Furthermore, the high-speed pattern signal (high-frequency pulse signal) transmitted from the driver 1 to the DUT 7 is also correctly transmitted by the action of the buffer amplifier 6 and the return line (outer shield 5).

On the other hand, although there is a capacitor C1 between the inner shield 4 and the outer shield 5, it does not cause a large delay because it is charged at high speed by the buffer amplifier 6 having a low output impedance.

The path of the high frequency pulse signal output from driver 1 is as follows:
(a) of the signal line 3 → (b) of the signal line 3 → 0UT7 → common potential of the test head 20 → (C) of the outer shield 5 → ld) of the outer shield 5 → common potential of the LSI tester body.

Incidentally, when the pulse to be transmitted is not high speed, the outer shield 5 does not need to be in the form of a covering and may be formed of a simple wire.

Effects of the Present Invention> As described above, according to the present invention, the only element added to the test head 20 is the buffer amplifier. A buffer amplifier is a single element (not made up of multiple electronic components) and does not require a lot of space.
On the other hand, the conventional configuration shown in FIG. 2 includes a driver and a comparator for the test head 20.

It requires many circuit elements such as control elements (consisting of DA converters, etc.). That is, in the present invention, the shape of the test head 20 can be made smaller. Also,
Since the transmission signal is not delayed without being influenced by the capacity of the transmission path, DUT inspection can be performed at high speed.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of the configuration of an LSI tester according to the present invention,
FIGS. 2 and 3 are diagrams showing a conventional example, FIGS. 4 and 5 are diagrams explaining signal delay, and FIG. 6 is a diagram explaining the operation in a comparator. 1... Driver, 2... Comparator, 3... Signal line, 4... Inner shield, 6... Buffer amplifier,
7...0 old, 10...131 tester body, 20...
・Test head, 30...double shielded wire. LSI Tess! Go to the 4 test 1) ゛Figure Figure Figure

Claims (1)

[Claims] A test head (20) on which LSIs to be tested (hereinafter simply referred to as DUTs) are mounted one after another, a driver (1) that applies a high-frequency pulse signal to a certain terminal of this DUT, and this DUT.
In the LSI tester main body (10), which is equipped with a comparator (2) that receives signals output from the same terminal of the UT, and a separate LSI tester, the signal line is double coated with an inner shield and an outer shield. A signal line connects a certain terminal of the DUT to a comparator and the same terminal of this DUT and a driver, and a double shield line whose outer shield is connected to a common potential is provided in the test head (20). , a high input impedance buffer amplifier which introduces the potential of a signal line into an input terminal and connects an output terminal having the same potential as the signal line potential to an inner shield.