JPH0712940Y2 - IC test equipment - Google Patents

IC test equipment

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Publication number
JPH0712940Y2
JPH0712940Y2 JP12940689U JP12940689U JPH0712940Y2 JP H0712940 Y2 JPH0712940 Y2 JP H0712940Y2 JP 12940689 U JP12940689 U JP 12940689U JP 12940689 U JP12940689 U JP 12940689U JP H0712940 Y2 JPH0712940 Y2 JP H0712940Y2
Authority
JP
Japan
Prior art keywords
test
terminal
during
line
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP12940689U
Other languages
Japanese (ja)
Other versions
JPH0368080U (en
Inventor
浩文 坪下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advantest Corp
Original Assignee
Advantest Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corp filed Critical Advantest Corp
Priority to JP12940689U priority Critical patent/JPH0712940Y2/en
Publication of JPH0368080U publication Critical patent/JPH0368080U/ja
Application granted granted Critical
Publication of JPH0712940Y2 publication Critical patent/JPH0712940Y2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Testing Of Individual Semiconductor Devices (AREA)
  • Tests Of Electronic Circuits (AREA)

Description

【考案の詳細な説明】 「産業上の利用分野」 この考案は被試験IC素子に対して、直流電圧、電流を印
加した時の電流、電圧を測定する直流試験と、論理パタ
ンを印加した時の出力の論理値を判定する論理試験とを
行うIC試験装置に関する。
[Detailed Description of the Device] “Industrial Application Field” This device applies a DC voltage to an IC device under test, a DC test for measuring current and voltage when a current is applied, and a logical test for applying a logical pattern. The present invention relates to an IC test device that performs a logic test for determining the logical value of the output of the.

「従来の技術」 第3図に従来のIC試験装置の一部を示す。試験装置本体
11内に設けられた直流印加測定モジュール12において端
子13から設定電圧が演算増幅器14の反転入力端に供給さ
れ、演算増幅器14の出力端がフォース線15の一端に接続
され、センス線16を通じて帰還された電圧が高入力イン
ピーダンスのセンス増幅器17を通じて演算増幅器14の反
転入力端に帰還される。演算増幅器14の出力端はガード
ドライバ18を通じてガード線19に接続される。フォース
線15、センス線16、ガード線19はそれぞれリレーススイ
ッチ21,22,23を通じて試験装置本体11の端子24,25,26に
それぞれ接続されている。
"Prior Art" Fig. 3 shows a part of a conventional IC test apparatus. Test equipment body
In the DC application measurement module 12 provided in 11, the set voltage is supplied from the terminal 13 to the inverting input terminal of the operational amplifier 14, the output terminal of the operational amplifier 14 is connected to one end of the force line 15, and is fed back through the sense line 16. The generated voltage is fed back to the inverting input terminal of the operational amplifier 14 through the high input impedance sense amplifier 17. The output terminal of the operational amplifier 14 is connected to the guard line 19 through the guard driver 18. The force line 15, the sense line 16, and the guard line 19 are connected to terminals 24, 25, and 26 of the test apparatus main body 11 through relay switches 21, 22, and 23, respectively.

試験装置本体11内の論理試験モジュール27のドライバ28
の出力側とコンパレータ29の入力側とがリレースイッチ
31を通じて端子25に接続され、端子26はリレースイッチ
32を通じて接地33に接続される。
Driver 28 of logic test module 27 in test apparatus main body 11
The output side of and the input side of the comparator 29 are relay switches.
Connected to terminal 25 through 31 and terminal 26 is a relay switch
Connected to ground 33 through 32.

端子24,25はそれぞれ2心シールド線34の一端において
その心線35,36にリレースイッチKD,KDを通じて接続
され、端子26はリレースイッチKDを通じてシールド37
に接続され、また端子25,26はそれぞれ同軸線38の一端
において内導体39、外導体41にそれぞれリレースイッチ
KL,KLを通じて接続される。
The terminals 24 and 25 are connected to the core wires 35 and 36 at one end of the two-core shield wire 34 through relay switches KD 1 and KD 2 , respectively, and the terminal 26 is shielded through the relay switch KD 3 37.
The terminals 25 and 26 are respectively connected to the inner conductor 39 and the outer conductor 41 at one end of the coaxial line 38 by a relay switch.
It is connected through KL 1 and KL 2 .

2心シールド線34の他端において心線35,36は互いに接
続されてリレースイッチKDを通じて被試験IC素子42の
1つのピンに接続される。同軸線38の他端において内導
体39はリレースイッチKLを通じて被試験IC素子42の前
記1つのピンに接続され、外導体41はリレースイッチKL
を通じて接地に接続される。
At the other end of the two-core shielded wire 34, the core wires 35 and 36 are connected to each other and connected to one pin of the IC element 42 under test through the relay switch KD 4 . At the other end of the coaxial line 38, the inner conductor 39 is connected to the one pin of the IC element under test 42 through the relay switch KL 3 , and the outer conductor 41 is connected to the relay switch KL.
4 to ground.

直流試験時にはリレースイッチ21,22,23、KD,KD,KD
,KD、をオンとし、端子13に設定電圧を印加する
と、心線35,36のリレースイッチKD側の接続点43の電
圧が心線36、センス線16を通じて演算増幅器14に帰還さ
れ、センス増幅器17が高入力インピーダンスでセンス線
16、心線26に電流が流れないから接続点43の電圧が端子
13の設定電圧と等しくなるように動作する。フォース線
15、心線35にて低インピーダンスで電流が流れ、またガ
ード線19を通じてシールド37がガードドライバ18により
駆動され、いわゆるケルビン接続が実現され、高絶縁、
高速セトリングが行われ、被試験IC素子42に設定直流電
圧を印加して直流試験が行われる。
Relay switches 21, 22, 23, KD 1 , KD 2 , KD for DC test
When 3 and KD 4 are turned on and the set voltage is applied to the terminal 13, the voltage at the connection point 43 on the relay switches KD 4 side of the core wires 35 and 36 is fed back to the operational amplifier 14 through the core wire 36 and the sense wire 16. , Sense amplifier 17 has high input impedance and sense line
16, no current flows through the core wire 26, so the voltage at the connection point 43 is the terminal
It operates so that it becomes equal to the set voltage of 13. Force line
15, the current flows with low impedance in the core wire 35, the shield 37 is driven by the guard driver 18 through the guard wire 19, so-called Kelvin connection is realized, high insulation,
Fast settling is performed, and a DC test is performed by applying a set DC voltage to the IC element under test 42.

論理試験時にはリレースイッチ31,32、KL,KL,KL,
KLをオンとし、論理パタンをドライバ28から同軸線38
を通じて被試験IC素子42に印加し、その時のIC素子42の
出力を同軸線38を通じてコンパレータ29で受信し、論理
レベルに変換する。このように同軸線38を使用すること
により、入出力側と伝送路とのインピーダンス整合をと
り、伝送波形の乱れを防止している。なお2心シールド
線34で論理パタンを伝送させようとすると、インピーダ
ンス整合がとれないため、論理パタンの波形が乱れ、正
しい試験を行うことができない。
During the logic test, relay switches 31,32, KL 1 , KL 2 , KL 3 ,
Turn on KL 4 , and set the logical pattern from driver 28 to coaxial line 38.
Is applied to the IC element 42 to be tested through, and the output of the IC element 42 at that time is received by the comparator 29 through the coaxial line 38 and converted into a logic level. By using the coaxial line 38 in this way, impedance matching between the input / output side and the transmission path is achieved, and the disturbance of the transmission waveform is prevented. In addition, if an attempt is made to transmit a logical pattern through the two-core shielded wire 34, impedance matching cannot be achieved, and the waveform of the logical pattern is disturbed, and a correct test cannot be performed.

「考案が解決しようとする課題」 以上述べたように従来のIC試験装置においては、被試験
IC素子42の1つのピンにつき、直流試験のための2心シ
ールド線34と、論理試験のための同軸線38との2本の伝
送線を使用し、かつこれらの切替えのために、リレース
イッチKD〜KD、KL〜KLの計8個も使用してい
た。
“Issues to be solved by the device” As described above, in the conventional IC test equipment,
For each pin of the IC element 42, two transmission lines, a two-core shielded wire 34 for a DC test and a coaxial wire 38 for a logic test, are used, and a relay switch is used for switching between them. A total of 8 pieces of KD 1 to KD 4 and KL 1 to KL 4 were also used.

この考案の目的は1本の伝送線(ケーブル)を使用し、
かつ少ないスイッチを使用し、しかも直流試験時にケル
ビン接続を行い、論理試験時に論理パタンの波形乱れを
伴うおそれがないIC試験装置を提供することにある。
The purpose of this device is to use one transmission line (cable),
Another object of the present invention is to provide an IC tester which uses a small number of switches and which is Kelvin connected during a DC test, and which is free from the possibility of waveform disturbance of a logic pattern during a logic test.

「課題を解決するための手段」 請求項1の考案によれば直流試験時にフォース線又はセ
ンス線が接続される第1端子と、直流試験時にセンス線
又はフォース線が接続され、論理試験時にドライバ、コ
ンパレータが接続される第2端子と、直流試験時にガー
ドドライバが接続され、論理試験時に接地に接続される
第3端子とが試験装置本体に設けられ、シールドされた
同軸線の一端において、その外導体が第1端子に接続さ
れると共に論理試験時にオンにされる第1スイッチを通
じて第3端子に接続され、内導体が第2端子に接続さ
れ、シールドが第3端子に接続され、シールドされた同
軸線の他端において、その外導体が直流試験時にオンと
される第2スイッチを通じて被試験IC素子の1つのピン
に接続されると共に論理試験時にオンとされる第3スイ
ッチを通じて接地に接続され、内導体が上記1つのピン
に接続される。
According to the invention of claim 1, the first terminal to which the force line or the sense line is connected during the DC test and the sense line or the force line during the DC test are connected, and the driver during the logic test. A second terminal to which the comparator is connected and a third terminal to which the guard driver is connected during the DC test and which is connected to the ground during the logic test are provided in the test apparatus body, and at one end of the shielded coaxial line, The outer conductor is connected to the first terminal and is connected to the third terminal through the first switch that is turned on during the logic test, the inner conductor is connected to the second terminal, the shield is connected to the third terminal, and the shield is connected. At the other end of the coaxial line, its outer conductor is connected to one pin of the IC device under test through the second switch that is turned on during the DC test and turned on during the logic test. Is connected to the ground through the third switch, the inner conductor is connected to said one pin.

請求項2の考案によれば、試験装置本体に請求項1の第
1端子、第2端子、第3端子と同様のものが設けられ、
同軸線と単線とを共通にシールドしたケーブルの一端に
おいて、その単線が第1端子に接続され、同軸線の内導
体が第2端子に接続され、外導体及びシールドが第3端
子に接続され、ケーブルの他端において、その単線が直
流試験時にオンとされる第1スイッチを通じて被試験IC
素子の1つのピンに接続され、そのピンに内導体が接続
され、外導体は論理試験時にオンとされる第2スイッチ
を通じて接地に接続される。
According to the invention of claim 2, the test device body is provided with the same terminals as the first terminal, the second terminal and the third terminal of claim 1.
At one end of the cable in which the coaxial wire and the single wire are commonly shielded, the single wire is connected to the first terminal, the inner conductor of the coaxial wire is connected to the second terminal, and the outer conductor and the shield are connected to the third terminal, At the other end of the cable, the IC under test passes through the first switch whose single line is turned on during the DC test.
The element is connected to one pin, the inner conductor is connected to the pin, and the outer conductor is connected to ground through a second switch that is turned on during the logic test.

「実施例」 第1図に請求項1の考案の実施例を示し、第3図と対応
する部分に同一符号を付けてある。この考案においては
同軸線38にシールド44が施された同軸シールド線45が使
用され、同軸シールド線45の一端においてその外導体41
は端子24に接続されると共に論理試験時にオンとされる
リレースイッチKLを通じて端子26に接続され、内導体
39は端子25に接続され、シールド44は端子26に接続され
る。同軸シールド線45の他端において外導体41は直流試
験時にオンとされるリレースイッチKDを通じて被試験
IC素子42の1つのピンに接続され、そのピンに内導体39
が接続され、また外導体41は論理試験時にオンとされる
リレースイッチKLを通じて接地に接続される。
[Embodiment] FIG. 1 shows an embodiment of the invention of claim 1, and the same reference numerals are given to the portions corresponding to those in FIG. In this invention, a coaxial shield wire 45 in which a shield 44 is applied to the coaxial wire 38 is used, and one end of the coaxial shield wire 45 has an outer conductor 41.
Is connected to the terminal 24 and is also connected to the terminal 26 through the relay switch KL 1 which is turned on during the logic test.
39 is connected to terminal 25 and shield 44 is connected to terminal 26. At the other end of the coaxial shield wire 45, the outer conductor 41 is tested under the relay switch KD 1 which is turned on during the DC test.
It is connected to one pin of IC element 42 and the inner conductor 39 is connected to that pin.
, And the outer conductor 41 is connected to ground through a relay switch KL 2 which is turned on during the logic test.

直流試験時にはリレースイッチ21,22,23、KDがオンと
される。フォース線15が同軸線38の外導体41に接続さ
れ、直流印加測定モジュール12よりの出力電圧が被試験
IC素子42のピンに印加され、その電圧が内導体39、セン
ス線16を通じて直流印加測定モジュール12に帰還されて
被試験IC素子42のピンに設定電圧が印加される。またガ
ード線19がシールド44に接続されて、シールド44がガー
ドドライバにより駆動される。従っていわゆるケルビン
接続が行われ、高絶縁、高速セトリングがなされる。
During DC test relay switches 21, 22, 23, KD 1 is turned on. The force wire 15 is connected to the outer conductor 41 of the coaxial wire 38, and the output voltage from the DC applied measurement module 12 is tested.
The voltage is applied to the pin of the IC element 42, and the voltage is fed back to the DC application measurement module 12 through the inner conductor 39 and the sense line 16 and the set voltage is applied to the pin of the IC element 42 to be tested. Further, the guard line 19 is connected to the shield 44, and the shield 44 is driven by the guard driver. Therefore, so-called Kelvin connection is performed, and high insulation and high-speed settling are performed.

論理試験時にはリレースイッチ31,32,KL,KLがオン
とされる。同軸線38の外導体41が接地され、論理試験モ
ジュール27からの論理パタンは同軸線38を通じて被試験
IC素子42へ供給され、その出力も同軸線38を通じて論理
試験モジュール27へ供給される。この時、同軸線38はそ
の入出力側とインピーダンス整合がとられ、論理パタ
ン、IC素子42の出力はその各波形が乱れることなく良好
に伝送される。
During the logic test, the relay switches 31, 32, KL 1 and KL 2 are turned on. The outer conductor 41 of the coaxial line 38 is grounded, and the logic pattern from the logic test module 27 is tested through the coaxial line 38.
It is supplied to the IC element 42 and its output is also supplied to the logic test module 27 through the coaxial line 38. At this time, the coaxial line 38 is impedance-matched with the input / output side thereof, and the logic pattern and the output of the IC element 42 are satisfactorily transmitted without the respective waveforms being disturbed.

第1図に括弧書きして示すように、フォース線15の代り
にセンス線16を接続し、センス線16の代りにフォース線
15を接続してもよい。しかしフォース線15には電流が流
れるため、内導体39よりインピーダンスが低い外導体41
にフォース線15が接続される構成が好ましい。
As shown in brackets in FIG. 1, a sense line 16 is connected instead of the force line 15 and a force line is used instead of the sense line 16.
15 may be connected. However, since an electric current flows through the force line 15, the outer conductor 41 whose impedance is lower than that of the inner conductor 39.
A configuration in which the force line 15 is connected to is preferable.

第2図に請求項2の考案の実施例を示し、第3図と対応
する部分に同一符号を付けてある。この考案においては
同軸線38と単線46とに共通のシールド44を施したケーブ
ル47が使用される。ケーブル47の一端において、単線46
は端子24に接続され、内導体39は端子25に接続され、外
導体41及びシールド44は端子26に接続される。ケーブル
47の他端において単線46は直流試験時にオンとされるリ
レースイッチKDを通じて被試験IC素子42の1つのピン
に接続され、そのピンに内導体39が接続され、外導体は
論理試験時にオンとされるリレースイッチKLを通じて
接地に接続される。
FIG. 2 shows an embodiment of the invention of claim 2, and parts corresponding to those of FIG. 3 are designated by the same reference numerals. In this invention, a cable 47 having a common shield 44 for the coaxial wire 38 and the single wire 46 is used. At one end of the cable 47, a single wire 46
Is connected to the terminal 24, the inner conductor 39 is connected to the terminal 25, and the outer conductor 41 and the shield 44 are connected to the terminal 26. cable
Single wire 46 at the other end 47 is connected to one pin of the IC under test element 42 through a relay switch KD 1 which is turned on when a DC test, the inner conductor 39 is connected to the pin, on the outer conductor during logic testing It is connected to ground through the relay switch KL 1 , which is said to be.

直流試験時にはリレースイッチ21,22,23,KDがオンと
される。フォス線15が単線46に接続され、センス線16が
内導体39に接続されて被試験IC素子42の1つのピンに設
定電圧が印加され、その際にガード線19が外導体41及び
シールド44に接続され、これらがガードドライブされ、
ケルビン接続で高絶縁、高速セトリングが行われる。
During DC test relay switches 21, 22, 23, KD 1 is turned on. The phosph wire 15 is connected to the single wire 46, the sense wire 16 is connected to the inner conductor 39, and the set voltage is applied to one pin of the IC element under test 42. At that time, the guard wire 19 is connected to the outer conductor 41 and the shield 44. Connected to, these are guard-driven,
Kelvin connection provides high insulation and fast settling.

論理試験時にはリレースイッチ31,32,KLがオンとされ
る。同軸線38の外導体41が接地され、その同軸線38を通
じて論理パタン及び被試験IC素子42の出力が伝送され、
インピーダンス整合のとれた伝送路で伝送される。
During the logic test, the relay switches 31, 32 and KL 1 are turned on. The outer conductor 41 of the coaxial line 38 is grounded, and the logical pattern and the output of the IC device under test 42 are transmitted through the coaxial line 38,
It is transmitted through a transmission line with impedance matching.

この第2図においてもフォース線15の代りにセンス線16
を接続し、センス線16の代りにフォース線15を接続して
もよい。第1図、第2図において論理試験モジュール27
はドライバ28、コンパレータ29の一方のみの場合もあ
る。
Also in FIG. 2, the sense line 16 is used instead of the force line 15.
And the force line 15 may be connected instead of the sense line 16. In FIG. 1 and FIG. 2, the logic test module 27
May be only one of the driver 28 and the comparator 29.

「考案の効果」 以上述べたようにこの考案によれば試験装置本体11と被
試験IC素子42との接続は1つのピンにつき1本の同軸シ
ールド線45又はケーブル47で済み、しかもスイッチも第
1図の例では3個、第2図の例では2個でよく、従来、
2本の伝送路と、8個のスイッチとを使用していた場合
と比較して構成が頗る簡単である。
[Effect of Device] As described above, according to the device of the present invention, the test device main body 11 and the IC element under test 42 can be connected with one coaxial shield wire 45 or cable 47 for each pin, and the switch is In the example of FIG. 1, the number of three may be two, and in the example of FIG.
The configuration is very simple compared to the case where two transmission lines and eight switches are used.

【図面の簡単な説明】[Brief description of drawings]

第1図は請求項1の考案の実施例を示す接続図、 第2図は請求項2の考案の実施例を示す接続図、 第3図は従来のIC試験装置を示す接続図である。 1 is a connection diagram showing an embodiment of the invention of claim 1, FIG. 2 is a connection diagram showing an embodiment of the invention of claim 2, and FIG. 3 is a connection diagram showing a conventional IC test apparatus.

Claims (2)

【実用新案登録請求の範囲】[Scope of utility model registration request] 【請求項1】試験装置本体に、直流試験時にフォース線
又はセンス線が接続される第1端子と、直流試験時にセ
ンス線又はフォース線が接続され、かつ論理試験時にド
ライバ、コンパレータが接続される第2端子と、直流試
験時にガードドライバが接続され、かつ論理試験時に接
地に接続される第3端子とが設けられ、 シールドされた同軸線の一端において、その外導体が上
記第1端子に接続されると共に論理試験時にオンにされ
る第1スイッチを通じて上記第3端子に接続され、内導
体が上記第2端子に接続され、シールドが上記第3端子
に接続され、 上記シールドされた同軸線の他端において、その外導体
が直流試験時にオンとされる第2スイッチを通じて被試
験IC素子の1つのピンに接続されると共に論理試験時に
オンとされる第3スイッチを通じて接地に接続され、内
導体が上記1つのピンに接続されるIC試験装置。
1. A first terminal to which a force line or a sense line is connected at the time of a direct current test, a sense line or a force line at the time of a direct current test, and a driver or a comparator at the time of a logic test are connected to a test apparatus body. A second terminal and a third terminal to which a guard driver is connected during the DC test and which is connected to the ground during the logic test are provided, and the outer conductor is connected to the first terminal at one end of the shielded coaxial line. Is connected to the third terminal through a first switch that is turned on during a logic test, the inner conductor is connected to the second terminal, the shield is connected to the third terminal, and the shielded coaxial cable At the other end, the outer conductor is connected to one pin of the IC device under test through the second switch that is turned on during the DC test and is turned on during the logic test. An IC tester in which the inner conductor is connected to the ground through the switch and the inner conductor is connected to the one pin.
【請求項2】試験装置本体に、直流試験時にフォース線
又はセンス線が接続される第1端子と、直流試験時にセ
ンス線又はフォース線が接続され、かつ論理試験時にド
ライバ、コンパレータが接続される第2端子と、直流試
験時にガードドライバが接続され、かつ論理試験時に接
地に接続される第3端子とが設けられ、 同軸線と単線とを共通にシールドしたケーブルの一端に
おいて、その単線が上記第1端子に接続され、同軸線の
内導体が上記第2端子に接続され、外導体及びシールド
が上記第3端子に接続され、 上記ケーブルの他端において、その単線が直流試験時に
オンとされる第1スイッチを通じて被試験IC素子の1つ
のピンに接続され、そのピンに内導体が接続され、外導
体は論理試験時にオンとされる第2スイッチを通じて接
地に接続されるIC試験装置。
2. A first terminal to which a force line or a sense line is connected during a direct current test, a sense line or a force line during a direct current test, and a driver or a comparator during a logical test are connected to the main body of the test apparatus. A second terminal and a third terminal to which a guard driver is connected during a DC test and which is connected to ground during a logic test are provided, and at one end of a cable in which a coaxial wire and a single wire are commonly shielded, the single wire is Connected to the first terminal, the inner conductor of the coaxial wire is connected to the second terminal, the outer conductor and the shield are connected to the third terminal, and at the other end of the cable, the single wire is turned on during the DC test. Is connected to one pin of the IC device under test through the first switch, the inner conductor is connected to the pin, and the outer conductor is grounded through the second switch that is turned on during the logic test. IC test equipment connected.
JP12940689U 1989-11-06 1989-11-06 IC test equipment Expired - Fee Related JPH0712940Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12940689U JPH0712940Y2 (en) 1989-11-06 1989-11-06 IC test equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12940689U JPH0712940Y2 (en) 1989-11-06 1989-11-06 IC test equipment

Publications (2)

Publication Number Publication Date
JPH0368080U JPH0368080U (en) 1991-07-03
JPH0712940Y2 true JPH0712940Y2 (en) 1995-03-29

Family

ID=31677035

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12940689U Expired - Fee Related JPH0712940Y2 (en) 1989-11-06 1989-11-06 IC test equipment

Country Status (1)

Country Link
JP (1) JPH0712940Y2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6331783B1 (en) * 1999-10-19 2001-12-18 Teradyne, Inc. Circuit and method for improved test and calibration in automated test equipment
JP2002040098A (en) * 2000-07-24 2002-02-06 Advantest Corp Testing device
JP5314412B2 (en) * 2008-12-19 2013-10-16 株式会社アドバンテスト Power supply device and test device

Also Published As

Publication number Publication date
JPH0368080U (en) 1991-07-03

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