KR20020043779A - Method for forming a isolation film - Google Patents

Method for forming a isolation film Download PDF

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Publication number
KR20020043779A
KR20020043779A KR1020000072897A KR20000072897A KR20020043779A KR 20020043779 A KR20020043779 A KR 20020043779A KR 1020000072897 A KR1020000072897 A KR 1020000072897A KR 20000072897 A KR20000072897 A KR 20000072897A KR 20020043779 A KR20020043779 A KR 20020043779A
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South Korea
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oxide film
film
oxide layer
device isolation
layer
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KR1020000072897A
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Korean (ko)
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김대영
박재범
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박종섭
주식회사 하이닉스반도체
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Priority to KR1020000072897A priority Critical patent/KR20020043779A/en
Publication of KR20020043779A publication Critical patent/KR20020043779A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE: A method for fabricating an isolation layer is provided to decrease the number of processes, by etching an isolating oxide layer in a predetermined portion of an active region of a peripheral circuit having a broad area of 4-10¬4 micrometer and an isolating oxide layer in a portion for an align key of a scribe lane while an etch process is performed once. CONSTITUTION: A pad oxide layer(32) and a nitride layer(33) are formed on a semiconductor substrate(31). The nitride layer, the pad oxide layer and a predetermined thickness of the semiconductor substrate are etched to form an isolation trench. The isolating oxide layer(35) is formed on the entire surface including the trench. A predetermined portion of the active region of the peripheral circuit and the isolating oxide layer in a region for the align key of the scribe lane are selectively etched to form the align key. The isolating oxide layer is planarization-etched and the nitride layer and the pad oxide layer are eliminated.

Description

소자분리막 형성 방법{Method for forming a isolation film}Method for forming a isolation film

본 발명은 소자분리막 형성 방법에 관한 것으로, 특히 한 번의 식각 공정으로 4 ∼ 104㎛의 넓은 면적을 갖는 주변회로의 활성 영역의 일정부분의 소자분리 산화막과 스크라이브-레인(Scribe-lane)의 얼라인 키(Align key)가 형성될 부위의 소자분리 산화막을 식각하여 소자 제조의 경제성을 향상시키는 소자분리막 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a device isolation film, and in particular, an etching of a device isolation oxide film and a scribe-lane in a portion of an active region of a peripheral circuit having a large area of 4 to 10 4 μm in one etching process. The present invention relates to a method of forming an isolation layer for etching an element isolation oxide film at a portion where an ign key is to be formed, thereby improving economic efficiency of device fabrication.

반도체 소자는 매년 집적도의 증가 추세를 보이고 있으며, 이러한 집적도의 증가는 소자 각각의 구성 요소 면적 및 크기의 감소를 수반하게 되어 여러 가지 공정상의 제약을 맞게 되는데 그 중에서 소자 분리가 문제된다.Semiconductor devices show an increasing trend in integration every year, and the increase in integration is accompanied by a reduction in the component area and size of each device, which results in various process constraints, among which device separation is a problem.

소자 분리 기술에는 크게 로코스(LOCOS)방법과 기판을 깍아 낸 다음에 CVD산화막으로 채운뒤에 평탄화하는 트렌치 아이솔레이션(Trench Isolation)방법이 있다.Device isolation techniques include the LOCOS method and the trench isolation method in which a substrate is scraped off and filled with a CVD oxide film and then planarized.

종래의 소자분리막 형성 방법은 도 1a에서와 같이, 트렌치 아이솔레이션 방법에 있어서, 소자분리 영역과 활성 영역이 정의된 반도체 기판(11)상에 패드(Pad) 산화막(12), 질화막(13) 및 제 1 감광막(도시하지 않음)을 순차적으로 형성한 다음, 상기 제 1 감광막을 상기 소자분리 영역 상측에만 제거되도록 선택적으로 노광 및 현상한다.A conventional device isolation film forming method is a trench isolation method, as shown in FIG. 1A, in which a pad oxide film 12, a nitride film 13, and a nitride film are formed on a semiconductor substrate 11 having a device isolation region and an active region defined therein. A photoresist film (not shown) is sequentially formed, and then the first photoresist film is selectively exposed and developed to be removed only above the device isolation region.

그리고, 상기 선택적으로 노광 및 현상된 제 1 감광막을 마스크로 상기 질화막(13), 패드 산화막 및 반도체 기판(11)을 선택 식각하여 트렌치(14)를 형성한다.In addition, the trench 14 is formed by selectively etching the nitride layer 13, the pad oxide layer, and the semiconductor substrate 11 using the selectively exposed and developed first photoresist layer as a mask.

도 1b에서와 같이, 상기 제 1 감광막을 제거한 다음, 상기 트렌치(14)를 포함한 전면에 소자분리 산화막(15)을 형성한다.As shown in FIG. 1B, after removing the first photoresist layer, the isolation oxide layer 15 is formed on the entire surface including the trench 14.

도 1c에서와 같이, 상기 소자분리 산화막(15)상에 제 2 감광막(도시하지 않음)을 도포한 다음, 상기 제 2 감광막을 주변회로의 활성 영역의 일정부분에만 제거되도록 선택적으로 노광 및 현상한다.As shown in FIG. 1C, a second photoresist film (not shown) is coated on the device isolation oxide film 15, and then the second photoresist film is selectively exposed and developed to remove only a portion of an active region of a peripheral circuit. .

그리고, 상기 선택적으로 노광 및 현상된 제 2 감광막을 마스크로 상기 소자분리 산화막(15)을 선택 식각한 후, 상기 제 2 감광막을 제거한다.After the selective isolation and etching of the device isolation oxide layer 15 using the selectively exposed and developed second photoresist layer, the second photoresist layer is removed.

도 1d에서와 같이, 상기 소자분리 산화막(15)을 시엠피(Chemical Mechanical Polishing: CMP) 방법으로 상기 트렌치(14)내에만 남으면서 평탄화 시킨 후, 상기 반도체 기판(11)상에 형성된 질화막(13) 및 패드 산화막(12)을 제거한다.As shown in FIG. 1D, the device isolation oxide film 15 is planarized while remaining only in the trench 14 by a chemical mechanical polishing (CMP) method, and then the nitride film 13 formed on the semiconductor substrate 11. And the pad oxide film 12 is removed.

도 1e에서와 같이, 상기 소자분리 산화막(15)을 포함한 전면에 제 3 감광막(도시하지 않음)을 도포한 다음, 상기 제 3 감광막을 스크라이브-레인의 얼라인 키가 형성될 부위에만 제거되도록 선택적으로 노광 및 현상한다.As shown in FIG. 1E, after applying a third photoresist film (not shown) to the entire surface including the device isolation oxide layer 15, the third photoresist film is selectively removed so as to be removed only at a portion where an align key of the scribe-lane is to be formed. Exposure and development.

그리고, 상기 선택적으로 노광 및 현상된 제 3 감광막을 마스크로 상기 소자분리 산화막(15)을 선택 식각하여 얼라인 키(16)를 형성한 다음, 상기 제 3 감광막을 제거한다.Then, the element isolation oxide film 15 is selectively etched using the selectively exposed and developed third photoresist film to form an alignment key 16, and then the third photoresist film is removed.

종래의 소자분리막 형성 방법은 주변회로의 활성 영역의 일정부분의 소자분리 산화막과 스크라이브-레인의 얼라인 키가 형성될 부위의 소자분리 산화막을 각각 두 단계의 식각 공정으로 식각하므로, 공정 횟수가 증가하여 그에 따른 비용이 증가되므로 소자 제조의 경제성을 저하시키는 문제점이 있었다.In the conventional method of forming a device isolation film, since the device isolation oxide film of a portion of the active region of the peripheral circuit and the device isolation oxide film of the portion where the align-lane of the scribe-lane are to be formed are etched by two etching processes, the number of processes is increased. As a result, the cost is increased, thereby lowering the economics of device manufacturing.

본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로 한 번의 식각 공정으로 4 ∼ 104㎛의 넓은 면적을 갖는 주변회로의 활성 영역의 일정부분의 소자분리 산화막과 스크라이브-레인의 얼라인 키가 형성될 부위의 소자분리 산화막을 식각하여 공정 횟수를 감소시키는 소자분리막 형성 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems. In one etching process, an element isolation oxide film and an alignment key of a scribe-lane in a portion of an active region of a peripheral circuit having a large area of 4 to 10 4 µm are formed. It is an object of the present invention to provide a method for forming an isolation layer for reducing the number of processes by etching the isolation oxide layer of the portion to be.

도 1a내지 도 1e는 종래의 소자분리막 형성 방법을 나타낸 공정 단면도1A to 1E are cross-sectional views illustrating a conventional method of forming a device isolation film.

도 2a내지 도 2d는 본 발명의 실시 예에 따른 소자분리막 형성 방법을 나타낸 공정 단면도2A to 2D are cross-sectional views illustrating a method of forming a device isolation film according to an embodiment of the present invention.

< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>

11, 31 : 반도체 기판 12, 32 : 패드 산화막11 and 31: semiconductor substrate 12 and 32: pad oxide film

13, 33 : 질화막 14, 34 : 트렌치13, 33: nitride film 14, 34: trench

15, 35 : 소자분리 산화막 16, 36 : 얼라인 키15, 35: device isolation oxide film 16, 36: alignment key

본 발명의 소자분리막 형성 방법은 반도체 기판 상에 패드 산화막과 질화막을 형성하고 상기 질화막, 패드 산화막 및 일정 두께의 반도체 기판을 식각하여 소자분리용 트렌치를 형성하는 단계, 상기 트렌치를 포함한 전면에 소자분리 산화막을 형성하는 단계, 상기 주변회로부의 활성 영역의 일정부분과 스크라이브-레인의 얼라인 키 예정 영역의 소자분리 산화막을 선택 식각하여 얼라인 키를 형성하는 단계 및 상기 소자분리 산화막을 평탄화 식각 공정을 실시한 후, 상기 질화막과 패드 산화막을 제거하는 단계를 포함하여 이루어짐을 특징으로 한다.In the method of forming a device isolation film of the present invention, forming a pad oxide film and a nitride film on a semiconductor substrate and etching the nitride film, the pad oxide film, and a semiconductor substrate having a predetermined thickness to form a device isolation trench, device isolation on the entire surface including the trench. Forming an oxide layer, forming an alignment key by selectively etching a portion of an active region of the peripheral circuit portion and a device isolation oxide film in an alignment key predetermined region of a scribe-lane, and planarizing etching the device isolation oxide film After the implementation, the step of removing the nitride film and the pad oxide film is characterized in that it is made.

상기와 같은 본 발명에 따른 소자분리막 형성 방법의 바람직한 실시 예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Referring to the accompanying drawings, preferred embodiments of the device isolation film forming method according to the present invention as described above in detail as follows.

도 2a 내지 도 2d는 본 발명의 실시 예에 따른 소자분리막 형성 방법을 나타낸 공정 단면도이다.2A through 2D are cross-sectional views illustrating a method of forming an isolation layer in accordance with an embodiment of the present invention.

본 발명의 실시 예에 따른 소자분리막 형성 방법은 도 2a에서와 같이, 트렌치 아이솔레이션 방법에 있어서, 소자분리 영역과 활성 영역이 정의된 반도체 기판(31)상에 패드 산화막(32), 질화막(33) 및 제 1 감광막(도시하지 않음)을 순차적으로 형성한 다음, 상기 제 1 감광막을 상기 소자분리 영역 상측에만 제거되도록 선택적으로 노광 및 현상한다.In the method of forming an isolation layer according to an exemplary embodiment of the present invention, as shown in FIG. 2A, in the trench isolation method, the pad oxide layer 32 and the nitride layer 33 are formed on the semiconductor substrate 31 on which the isolation region and the active region are defined. And sequentially forming a first photosensitive film (not shown), and then selectively exposing and developing the first photosensitive film to be removed only above the device isolation region.

그리고, 상기 선택적으로 노광 및 현상된 제 1 감광막을 마스크로 상기 질화막(33), 패드 산화막(32) 및 반도체 기판(31)을 선택 식각하여 트렌치(34)를 형성한다.The trench 34 may be formed by selectively etching the nitride layer 33, the pad oxide layer 32, and the semiconductor substrate 31 using the selectively exposed and developed first photoresist layer as a mask.

도 2b에서와 같이, 상기 제 1 감광막을 제거한 다음, 상기 트렌치(34)를 포함한 전면에 소자분리 산화막(35)을 형성한다.As shown in FIG. 2B, after removing the first photoresist layer, the device isolation oxide layer 35 is formed on the entire surface including the trench 34.

도 2c에서와 같이, 상기 소자분리 산화막(35)상에 제 2 감광막(도시하지 않음)을 도포한 다음, 상기 제 2 감광막을 4 ∼ 104㎛의 넓은 면적을 갖는 주변회로의 활성 영역의 일정부분과 스크라이브-레인의 얼라인 키가 형성될 부위에만 제거되도록 선택적으로 노광 및 현상한다.As shown in FIG. 2C, a second photosensitive film (not shown) is coated on the device isolation oxide layer 35, and then the second photosensitive film is coated with a predetermined area of an active region of a peripheral circuit having a large area of 4 to 10 4 μm. It is selectively exposed and developed so that only the portion where the alignment key of the portion and the scribe-lane will be formed is removed.

그리고, 상기 선택적으로 노광 및 현상된 제 2 감광막을 마스크로 상기 소자분리 산화막(35)을 500 ∼ 3000Å의 깊이로 선택 식각한 후, 상기 제 2 감광막을 제거한다.Then, the device isolation oxide film 35 is selectively etched to a depth of 500 to 3000 Pa by using the selectively exposed and developed second photosensitive film as a mask, and then the second photosensitive film is removed.

여기서, 상기 스크라이브-레인의 소자분리 산화막(35)의 선택 식각 공정으로 얼라인 키(36)를 형성한다.Here, the alignment key 36 is formed by a selective etching process of the device isolation oxide layer 35 of the scribe-lane.

도 2d에서와 같이, 상기 소자분리 산화막(35)을 CMP 방법으로 상기 트렌치(33)내에만 남으면서 평탄화 시킨 후, 상기 반도체 기판(31)상에 형성된 질화막(33) 및 패드 산화막(32)을 제거한다.As shown in FIG. 2D, the device isolation oxide film 35 is planarized while remaining only in the trench 33 by the CMP method, and then the nitride film 33 and the pad oxide film 32 formed on the semiconductor substrate 31 are removed. do.

본 발명의 소자분리막 형성 방법은 한 번의 식각 공정으로 4 ∼ 104㎛의 넓은 면적을 갖는 주변회로의 활성 영역의 일정부분의 소자분리 산화막과 스크라이브-레인의 얼라인 키가 형성될 부위의 소자분리 산화막을 식각하므로, 공정 횟수가 감소되어 그에 따른 비용이 절감되므로 소자 제조의 경제성을 향상시키는 효과가 있다.In the method for forming an isolation layer of the present invention, the isolation of a portion of an element where an alignment key of a scribe-lane is formed and a portion of an isolation region of an active region of a peripheral circuit having a large area of 4 to 10 4 μm is formed in one etching process. Since the oxide film is etched, the number of processes is reduced and thus the cost is reduced, thereby improving the economics of device manufacturing.

Claims (3)

반도체 기판 상에 패드 산화막과 질화막을 형성하고 상기 질화막, 패드 산화막 및 일정 두께의 반도체 기판을 식각하여 소자분리용 트렌치를 형성하는 단계;Forming a pad oxide film and a nitride film on the semiconductor substrate, and etching the nitride film, the pad oxide film, and the semiconductor substrate having a predetermined thickness to form a device isolation trench; 상기 트렌치를 포함한 전면에 소자분리 산화막을 형성하는 단계;Forming a device isolation oxide film on the entire surface including the trench; 상기 주변회로부의 활성 영역의 일정부분과 스크라이브-레인의 얼라인 키 예정 영역의 소자분리 산화막을 선택 식각하여 얼라인 키를 형성하는 단계;Forming an alignment key by selectively etching a portion of an active region of the peripheral circuit portion and an element isolation oxide film of an alignment key predetermined region of a scribe-lane; 상기 소자분리 산화막을 평탄화 식각 공정을 실시한 후, 상기 질화막과 패드 산화막을 제거하는 단계를 포함하여 이루어짐을 특징으로 하는 소자분리막 형성 방법.And removing the nitride film and the pad oxide film after performing the planarization etching process of the device isolation oxide film. 제 1 항에 있어서,The method of claim 1, 상기 소자분리 산화막을 상기 주변회로의 활성 영역의 면적이 4 ∼ 104㎛인 경우에 식각함을 특징으로 하는 소자분리막 형성 방법.And etching the device isolation oxide film when the area of the active region of the peripheral circuit is 4 to 10 4 µm. 제 1 항에 있어서,The method of claim 1, 상기 소자분리 산화막을 500 ∼ 3000Å의 깊이로 식각함을 특징으로 하는 소자분리막 형성 방법.And etching the device isolation oxide film to a depth of 500 to 3000 microns.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100460146B1 (en) * 2002-02-19 2004-12-04 삼성전자주식회사 Method manufacturing of a semiconductor device
KR100802221B1 (en) * 2005-12-30 2008-02-11 주식회사 하이닉스반도체 Method for forming semiconductor device
US7485543B2 (en) 2005-12-30 2009-02-03 Hynix Semiconductor Inc. Method for manufacturing semiconductor device with overlay vernier

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100460146B1 (en) * 2002-02-19 2004-12-04 삼성전자주식회사 Method manufacturing of a semiconductor device
KR100802221B1 (en) * 2005-12-30 2008-02-11 주식회사 하이닉스반도체 Method for forming semiconductor device
US7485543B2 (en) 2005-12-30 2009-02-03 Hynix Semiconductor Inc. Method for manufacturing semiconductor device with overlay vernier

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