KR20020037091A - Method for fabricating capacitor of semiconductor device - Google Patents

Abstract

PURPOSE: A method for fabricating a capacitor of a semiconductor device is provided to prevent an increase of a resistance between a BC-plug and a storage poly electrode by using an OCS(One Cylinder Storage node) process on a cell pad. CONSTITUTION: The first interlayer dielectric(102) and the second interlayer dielectric(104), and an etch stopper layer(106) are deposited on a substrate. A photoresist pattern is formed thereon. A groove portion is formed by etching selectively the etch stopper layer(106) and the second interlayer dielectric(104). The photoresist pattern is removed. The third interlayer dielectric(110) is deposited thereon. An anti-reflective coating layer is deposited on the third interlayer dielectric(110). A photoresist layer is formed on the anti-reflective coating layer. A storage poly hole is formed by etching the anti-reflective coating layer and the third interlayer dielectric(110). A self-aligned BC is formed by etching the third interlayer dielectric(110) and the first interlayer dielectric(102). The etch stopper layer(106) is removed. A spacer(116) is formed on both sidewalls of the storage poly hole and the self-aligned BC. A polysilicon layer is deposited thereon. The fourth interlayer dielectric is deposited on the polysilicon layer. A BC-plug(118a) and a storage poly electrode(118b) are formed by etching back the fourth interlayer dielectric and the polysilicon layer.

Description

Method for fabricating capacitor of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and in particular, an increase in resistance between "BC-plug" and "storage poly electrode" when capacitors are manufactured by applying an OCS process on a cell pad. The present invention relates to a method of manufacturing a capacitor of a semiconductor device to prevent the process and simplify the process.

In the era of deep submicron, the integration of semiconductor devices has increased, and as a result, the size of unit devices has been reduced. As a result, the size of the conductive plug for connecting the device to the device and the space and width between the metal wirings are also reduced. In recent years, the design of the device may be directly performed when designing a device for securing a process margin. The process is performed by forming a direct contact (DC) and a buried contact (BC) through a cell pad process without performing a contact process.

1A to 1E show a conventional process flowchart showing a method of manufacturing a capacitor by applying the OCS process on the cell pad. Referring to this, the manufacturing method is classified into a fifth step as follows.

As a first step, as shown in FIG. 1A, the first interlayer insulating film 12 made of BPSG material and the second interlayer insulating film 14 made of HTO material are sequentially stacked on the insulating substrate having the cell pad 10, and then the cell pad is formed. These first and second interlayer insulating films are selectively etched to expose a predetermined portion of the surface of (10), respectively, to form a buried contact (h1).

As a second step, as shown in Figure 1b, after forming the spacer 16 of the nitride film material on both inner walls of the BC (h1), and depositing a polysilicon film on the resultant to sufficiently fill the inside of the BC (h1), The back surface of the second interlayer insulating film 14 is etched back to form a BC-plug 18 made of polysilicon in BC (h1).

As a third step, an etch stopper film 20 made of a nitride film is deposited on the second interlayer insulating film 14 including the BC plug 18 as shown in FIG. 1C, and a PE-OXIDE material is deposited thereon. A third interlayer insulating film 22 and a non-reflective coating film (ARC) 24 made of PE-SION are sequentially stacked. Subsequently, the non-reflective coating film 24 and the third interlayer insulating film 22 are selectively etched to a portion where the etch stopper film 20 is formed using the photoresist pattern (not shown) defining the storage electrode forming portion as a mask. S-POLY hole (h2) is formed.

As a fourth step, as shown in FIG. 1D, a polysilicon layer 26 is deposited on the resultant to a thickness of about 500 m 3, and a fourth interlayer insulating layer of USG material is formed thereon so that the inside of the storage poly hole h2 is sufficiently filled. 28).

As a fifth step, as shown in FIG. 1E, the fourth interlayer insulating film 28 and the polysilicon film 26 are etched back until the anti-reflective coating film 24 is removed to form a separate storage poly electrode 26a. The process of this process is completed by removing the fourth interlayer insulating film 28 by the wet etching method.

However, when the capacitor is manufactured by applying the above process, the process proceeds in such a manner that the storage poly-electrode 26a is formed on the BC-plug 18 while the following two problems occur in manufacturing the device. .

First, the number of ongoing processes increases, which complicates the process, increases production costs, and lengthens the production schedule.

Second, an increase in resistance caused by foreign matter generation between the BC-plug 18 and the storage poly electrode 26a interface causes a failure of the last data into row free charge time (TRDL). The defect may be polymer components generated during an etching process for forming the storage poly hole h2 or FAB. It is a phenomenon caused by the subsequent process (storage poly electrode forming process) in which the contaminants in the internal environment are not completely removed through the cleaning operation and some of them are attached to the surface of the BC-plug 18 as foreign matter. .

Accordingly, an object of the present invention is that, in the etching process for forming the storage poly hole, the hole etching is stopped in the etch stopper film, and then self-aligned by the etching process using the etch stopper film as a mask. By changing the capacitor fabrication process to form BC, the "BC-plug" and "storage poly electrode" are deposited in-situ, reducing the resistance between the BC plug and the storage poly electrode and simplifying the process. To provide a capacitor manufacturing method of a semiconductor device to achieve the.

1a to 1e is a process flowchart showing a capacitor manufacturing method applying a conventional OCS process,

2A to 2I are process flowcharts showing a capacitor manufacturing method to which the OCS process according to the present invention is applied.

In order to achieve the above object, the present invention includes the steps of sequentially stacking a first interlayer insulating film, a second interlayer insulating film and an etch stopper film on an insulating substrate provided with a cell pad; Etching the etch stopper film and the second interlayer insulating film using a photosensitive film pattern defining a BC forming part as a mask to form recesses to be used as a part of BC on the upper side of the cell pad; Depositing a third interlayer insulating film on the resultant to fill the recess portion; Forming a storage poly hole by etching the third interlayer insulating layer until the surface of the etch stopper layer is exposed using the photoresist pattern defining the storage electrode forming portion as a mask; By using the etch stopper film at the bottom of the storage poly hole as a mask so as to expose the surface of the cell pad, the remaining third interlayer insulating film and the first interlayer insulating film at the bottom thereof are sequentially etched to self-align BC. Forming a; Removing the etch stopper film used as a mask; Forming insulating spacers at both inner walls of the storage poly holes and the BC; Depositing a polysilicon film on the resultant in-situ, and depositing a fourth interlayer insulating film thereon to fill the inside of the storage poly hole; Etching back the fourth interlayer dielectric layer and the polysilicon layer to expose the surface of the third interlayer dielectric layer to simultaneously form a BC-plug and a storage poly electrode; Removing the third and fourth interlayer insulating films remaining around the storage poly electrode; And removing the insulating spacer outside the storage poly electrode.

When the capacitor is manufactured by applying the above process, the BC formation process using the etch stopper film as a mask is also involved in the etching process for forming the storage poly hole, so that the BC-plug and the storage poly electrode may be formed at the same time. It becomes possible. As a result, the BC-plug formation process can be skipped, which not only simplifies the process but also reduces the resistance between the BC-plug and the storage polyelectrode.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

2A to 2I are process flowcharts illustrating a capacitor manufacturing method using the OCS process proposed in the present invention. Referring to this, the manufacturing method is classified into ninth steps as follows.

As a first step, as shown in FIG. 2A, a first interlayer insulating film 102 made of BPSG material, a second interlayer insulating film 104 made of HTO material, and an etch stopper film made of nitride film are formed on an insulating substrate provided with the cell pad 100. After sequentially stacking 106, a photosensitive film pattern 108 defining a BC forming portion is formed thereon.

As a second step, the etch stopper film 106 and the second interlayer insulating film 104 are selectively etched using the photosensitive film pattern 108 as a mask, as shown in FIG. After the recess t is to be used, the photoresist pattern 108 is removed.

As a third step, a third interlayer insulating film 110 of HDP material is deposited to a sufficient thickness so that the inside of the recess t is filled on the resultant as shown in FIG. 2C, and the non-reflective coating film 112 of SiON material is deposited thereon. E). Subsequently, a photoresist pattern 114 defining a storage electrode forming portion is formed on the antireflective coating layer 112.

As a fourth step, as shown in FIG. 2D, the anti-reflective coating layer 112 and the third interlayer insulating layer 110 are sequentially etched until the surface of the etch stopper layer 106 is exposed, using the photoresist pattern 114 as a mask. After forming the storage poly hole h2 penetrating through the third interlayer insulating layer 110, the photoresist layer pattern 114 is removed. Subsequently, the third interlayer insulating film 110 in the recess t and the first lower portion of the recess t are formed using the remaining etch stopper layer 106 at the bottom of the storage poly hole h2 as a mask so that the surface of the cell pad 100 is exposed. The interlayer insulating film 102 is sequentially etched. As a result, self-aligned BC h1 penetrating the first and second interlayer insulating films 102 and 104 is formed.

As a fifth step, the etch stopper film 106 used as a mask is removed as shown in FIG. 2E.

As a sixth step, as shown in FIG. 2F, spacers 116 made of a nitride film are formed on both inner walls of the storage poly holes h2 and BC h1, respectively.

As a seventh step, a polysilicon film 118 having a thickness of 500 microseconds is deposited on the resultant as shown in FIG. 2G in situ. In this process, BC (h1) is almost filled with a polysilicon film. Subsequently, a fourth interlayer insulating layer 120 of USG material is deposited on the polysilicon layer 118 to a sufficient thickness so that the inside of the storage poly hole h2 is filled.

As an eighth step, as shown in FIG. 2H, the fourth interlayer insulating film 120 and the polysilicon film 118 are etched back until the anti-reflective coating film 112 is completely removed to form a BC-plug made of polysilicon. 118a and the storage poly electrode 118b are formed. The etch back process is performed to separate the storage poly electrodes 118b adjacent to each other.

As a ninth step, as shown in FIG. 2I, the third and fourth interlayer insulating layers 110 and 120 remaining around the storage poly electrode 118b are removed by wet etching, and the storage poly electrode 118a is removed. The process of this process is completed by removing the outer insulating spacer 116 by a wet etching method.

When the process is performed in this way, during the etching process for forming the storage poly hole h2, the hole etching is stopped in the etch stopper layer 106, and BC (h1) is then left on the bottom surface of the hole h2. Since the etching stopper film 106 is formed by an etching process using the etch stopper film 106 as a mask, it is possible to deposit a polysilicon film in the in-situ method in the BC (h1) and the storage poly hole (h2). That is, the BC-plug 118b and the storage poly electrode 118a can be formed at the same time by one film deposition process.

As a result, it is possible to skip the separate film deposition process and etching process required for conventional BC-plug formation, thereby simplifying the process, and the problem of resistance between the BC plug 118b and the storage poly electrode 118a. Can be solved.

In addition, in this case, since the contact area between the dielectric film to be formed later and the storage poly-electrode can be secured wider than the conventional structure, an additional effect of increasing the capacitance of the capacitor can be obtained.

As described above, according to the present invention, in the etching process for forming the storage poly hole, the BC forming process using the etch stopper film as a mask is accompanied, and the "BC-plug" and the "storage poly electrode" are in situ. By changing the capacitor manufacturing process so that the process is formed all at once, 1) the existing film deposition process and etching process required for BC-plug formation can be skipped, and the process can be simplified. 2) "BC-plug" And the resistance between the "storage poly electrode" can be reduced, and 3) the capacitance of the capacitor can be increased.

Claims (11)

Sequentially stacking a first interlayer insulating film, a second interlayer insulating film, and an etch stopper film on an insulating substrate having a cell pad; Etching the etch stopper film and the second interlayer insulating film using a photosensitive film pattern defining a BC forming part as a mask to form recesses to be used as a part of BC on the upper side of the cell pad; Depositing a third interlayer insulating film on the resultant to fill the recess portion; Forming a storage poly hole by etching the third interlayer insulating layer until the surface of the etch stopper layer is exposed using the photoresist pattern defining the storage electrode forming portion as a mask; By using the etch stopper film at the bottom of the storage poly hole as a mask so as to expose the surface of the cell pad, the remaining third interlayer insulating film and the first interlayer insulating film at the bottom thereof are sequentially etched to self-align BC. Forming a; Removing the etch stopper film used as a mask; Forming insulating spacers at both inner walls of the storage poly holes and the BC; Depositing a polysilicon film on the resultant in-situ, and depositing a fourth interlayer insulating film thereon to fill the inside of the storage poly hole; Etching back the fourth interlayer dielectric layer and the polysilicon layer to expose the surface of the third interlayer dielectric layer to simultaneously form a BC-plug and a storage poly electrode; Removing the third and fourth interlayer insulating films remaining around the storage poly electrode; And And removing the insulating spacer outside the storage poly electrode. The method of claim 1, wherein the first interlayer insulating layer is formed of a BPSG material. The method of claim 1, wherein the second interlayer insulating layer is formed of an HTO material. The method of claim 1, wherein the third interlayer insulating layer is formed of an HDP material. The method of claim 1, wherein the fourth interlayer insulating layer is formed of a USG material. The method of claim 1, wherein the insulating spacer is formed of a nitride film material. The method of claim 1, wherein the third and fourth interlayer insulating layers are removed by a wet etching method. The method of claim 1, wherein the insulating spacer is removed by a wet etching method. The method of claim 1, further comprising depositing a non-reflective coating film made of SiON after the deposition of the third interlayer insulating film. The method of claim 9, wherein when the non-reflective coating layer is further deposited, the non-reflective coating layer is also removed during the etchback process of the fourth interlayer insulating layer and the polysilicon layer. The method of claim 1, wherein the etch stopper film is formed of a nitride film material.