KR20020034700A - Manufacturing method for mos transister - Google Patents
Manufacturing method for mos transister Download PDFInfo
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- KR20020034700A KR20020034700A KR1020000065174A KR20000065174A KR20020034700A KR 20020034700 A KR20020034700 A KR 20020034700A KR 1020000065174 A KR1020000065174 A KR 1020000065174A KR 20000065174 A KR20000065174 A KR 20000065174A KR 20020034700 A KR20020034700 A KR 20020034700A
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- drain
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- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000005468 ion implantation Methods 0.000 claims abstract description 16
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 15
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 14
- 150000002500 ions Chemical class 0.000 claims abstract description 13
- 239000000872 buffer Substances 0.000 claims abstract description 12
- 239000012535 impurity Substances 0.000 claims abstract description 8
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
Abstract
Description
본 발명은 모스 트랜지스터 제조방법에 관한 것으로, 특히 선택적 성장법을 이용하여 얇은 접합을 형성하는 공정에서, 성장된 박막의 두께를 균일하게 하여 정확한 고농도 소스 및 드레인의 윤곽(PROFILE)을 얻는데 적당하도록 한 모스 트랜지스터 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a MOS transistor, in particular in the process of forming a thin junction by using a selective growth method, the thickness of the grown thin film is uniform so as to be suitable for obtaining an accurate high concentration source and drain profile (PROFILE) It relates to a MOS transistor manufacturing method.
도1a 내지 도1c는 종래 모스 트랜지스터 제조공정 수순단면도로서, 이에 도시한 바와 같이 기판(1)의 상부전면에 게이트산화막(2)과 다결정실리콘(3)을 증착하고 패터닝하여 게이트를 형성한 후, 그 게이트의 측면 기판(1)에 저농도 불순물 이온을 주입하여 저농도 소스 및 드레인(4)을 형성하는 단계(도1a)와; 상기 구조의 상부전면에 절연막을 증착하고, 그 절연막을 건식식각하여 상기 게이트의 측면에 측벽(5)을 형성한 후, 상기 측벽(5)의 측면에 노출된 저농도 소스 및 드레인(4) 영역의 상부측으로 선택적 에피 성장층(6)을 성장시키는 단계(도1b)와; 상기 선택적 에피 성장층(6)을 이온주입버퍼로 사용하는 이온주입공정으로 상기 측벽(5)의 측면 기판(1) 하부에 고농도 소스 및 드레인(7)을 형성하는 단계(도1c)로 구성된다.1A to 1C are cross-sectional views of a conventional MOS transistor fabrication process. As shown in FIG. 1A to 1C, a gate oxide film 2 and a polysilicon 3 are deposited and patterned on an upper surface of a substrate 1 to form a gate. Implanting low concentration impurity ions into the side substrate 1 of the gate to form a low concentration source and drain 4 (FIG. 1A); An insulating film is deposited on the upper surface of the structure, and the insulating film is dry etched to form sidewalls 5 on the side surfaces of the gate, and then the low concentration source and drain 4 regions exposed on the side surfaces of the sidewalls 5 are formed. Growing a selective epitaxial growth layer 6 to the upper side (FIG. 1B); In the ion implantation process using the selective epitaxial growth layer 6 as an ion implantation buffer, a high concentration source and drain 7 are formed below the side substrate 1 of the sidewall 5 (FIG. 1C). .
이하, 상기와 같이 구성된 종래 모스 트랜지스터 제조방법을 좀 더 상세히 설명한다.Hereinafter, the conventional MOS transistor manufacturing method configured as described above will be described in more detail.
먼저, 도1a에 도시한 바와 같이 반도체 기판(1)의 상부전면에 게이트산화막(2)과 다결정실리콘(3)을 증착하고, 사진식각공정을 통해 상기 다결정실리콘(3)과 게이트산화막(2)의 일부를 제거하여 게이트를 형성한다.First, as shown in FIG. 1A, the gate oxide film 2 and the polycrystalline silicon 3 are deposited on the upper surface of the semiconductor substrate 1, and the polysilicon 3 and the gate oxide film 2 are formed by a photolithography process. Remove part of it to form a gate.
그 다음, 특정 도전형의 불순물 이온을 저농도로 주입하여 상기 게이트의 측면 기판(1)의 하부에 저농도 소스 및 드레인(4)을 형성한다.Next, a low concentration source and drain 4 are formed in the lower portion of the side substrate 1 of the gate by implanting impurity ions of a specific conductivity type at a low concentration.
그 다음, 도1b에 도시한 바와 같이 상기 구조의 상부전면에 절연막을 증착하고, 그 증착된 절연막을 건식식각하여 측벽(5)을 형성한다.Next, as shown in FIG. 1B, an insulating film is deposited on the upper surface of the structure, and the sidewall 5 is formed by dry etching the deposited insulating film.
그 다음, 상기 측벽(5)의 측면 하부측에서 노출된 저농도 소스 및 드레인(4)의 상부측에만 단결정실리콘층을 성장시켜 보다 얇은 고농도 소스 및 드레인을 형성하기 위한 선택적 에피 성장층(6)을 형성한다.Next, an optional epitaxial growth layer 6 is formed to grow a single crystal silicon layer only on the upper side of the low concentration source and drain 4 exposed at the lower side of the sidewall 5 to form a thinner high concentration source and drain. Form.
이때, 선택적 에피 성장층(6)은 단결정 성장의 특성상 그 측면부가 경사지게 형성된다. 즉 상부면이 하부면보다 그 면적이 작게 형성되어, 상기 측벽(5)과의 접촉부가 다른 곳에 비하여 그 두께가 얇게 형성되어진다.At this time, the selective epitaxial growth layer 6 is formed inclined at the side part due to the characteristics of the single crystal growth. That is, the area of the upper surface is smaller than that of the lower surface, and the contact portion with the side wall 5 is formed to be thinner than other places.
그 다음, 도1c에 도시한 바와 같이 상기 선택적 에피 성장층(6)을 이온주입의 버퍼로 사용하는 이온주입공정으로 상기 선택적 에피 성장층(6)의 하부에 고농도 소스 및 드레인(7)을 형성한다.Next, as shown in FIG. 1C, a high concentration source and drain 7 are formed under the selective epitaxial growth layer 6 by an ion implantation process using the selective epitaxial growth layer 6 as an ion implantation buffer. do.
이때 고농도 소스 및 드레인(7)은 상기 버퍼로 사용하는 선택적 에피 성장층(6)의 측면부의 두께가 중앙부의 두께에 비하여 얇은 이유로 그 윤곽(PROFILE)이 불균일하게 형성된다. 즉 동일한 에너지로 불순물 이온을 주입하는 경우 버퍼가 얇은 영역에서는 이온이 더 깊이 주입되고, 버퍼가 두꺼운 영역에서는 이온이 상대적으로 얇게 주입되어 불균일한 윤곽을 갖게 된다.At this time, the high concentration source and drain 7 has a non-uniform profile (PROFILE) because the thickness of the side portion of the selective epitaxial growth layer 6 used as the buffer is thinner than that of the central portion. In other words, when impurity ions are implanted with the same energy, ions are implanted deeper in the region where the buffer is thin, and ions are implanted relatively thinly in the region where the buffer is thick, resulting in uneven contour.
상기한 바와 같이 종래 모스 트랜지스터 제조방법은 보다 얇은 두께의 고농도 소스 및 드레인을 형성하기 위하여 단결정 실리콘층을 성장시켜 이를 이온주입버퍼로 사용하였으며, 그 단결정 실리콘층의 두께 차에 의해 주입되는 이온의 주입 깊이가 달라 고농도 소스 및 드레인의 윤곽이 불균일하게 형성되어 모스 트랜지스터의 특성이 열화되는 문제점이 있었다.As described above, in the conventional MOS transistor manufacturing method, a single crystal silicon layer was grown to form a thinner, thicker source and drain, and used as an ion implantation buffer, and implantation of ions implanted by the difference in thickness of the single crystal silicon layer. Due to the different depths, the contours of the highly concentrated source and drain are formed unevenly, thereby degrading the characteristics of the MOS transistor.
이와 같은 문제점을 감안한 본 발명은 균일한 윤곽을 갖는 고농도 소스 및 드레인을 갖는 모스 트랜지스터 제조방법을 제공함에 그 목적이 있다.It is an object of the present invention to provide a MOS transistor manufacturing method having a high concentration source and drain having a uniform contour.
도1a 내지 도1c는 종래 모스 트랜지스터의 제조공정 수순단면도.1A to 1C are cross-sectional views illustrating a manufacturing process of a conventional MOS transistor.
도2a 내지 도2d는 본 발명 모스 트랜지스터의 제조공정 수순단면도.2A to 2D are cross-sectional views of a manufacturing process of the MOS transistor of the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
1:기판2:게이트산화막1: Substrate 2: Gate oxide film
3:다결정실리콘4:저농도 소스 및 드레인3: polycrystalline silicon 4: low concentration source and drain
5:측벽6:선택적 에피 성장층5: side wall 6: selective epitaxial growth layer
7:고농도 소스 및 드레인8:실리사이드7: high concentration source and drain 8: silicide
상기와 같은 목적은 기판의 상부에 게이트를 형성하고, 불순물 이온을 주입하여 그 게이트의 측면 기판하부에 저농도 소스 및 드레인을 형성하는 단계와; 상기 기판의 측면에 측벽을 형성한 후, 상기 측벽의 측면에서 노출된 저농도 소스 및 드레인 영역의 상부에 측면이 경사진 선택적 에피 성장층을 성장시키는 단계와; 상기 선택적 에피 성장층의 상부에 상부면이 평탄한 실리사이드를 형성한 후, 상기 실리사이드와 선택적 에피 성장층을 이온주입버퍼로 사용하는 이온주입공정으로 윤곽이 균일한 고농도 소스 및 드레인을 형성하는 단계로 구성함으로써 달성되는 것으로, 이와 같은 본 발명을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.The above object is to form a gate on top of the substrate, implanting impurity ions to form a low concentration source and drain under the side substrate of the gate; Forming a sidewall on the side of the substrate, and then growing a selective epitaxially inclined sidewall on top of the low concentration source and drain regions exposed at the side of the sidewall; After forming a silicide having a flat top surface on top of the selective epitaxial growth layer, an ion implantation process using the silicide and the selective epitaxial growth layer as an ion implantation buffer to form a high concentration source and drain having a uniform contour. This is achieved by, when described in detail with reference to the accompanying drawings, the present invention as follows.
도2a 내지 도2d는 본 발명 모스 트랜지스터 제조공정 수순단면도로서, 이에 도시한 바와 같이 기판(1)의 상부에 게이트산화막(2)과 다결정실리콘(3)을 증착하고 패터닝하여 게이트를 형성한 후, 불순물 이온주입공정을 통해 상기 게이트의 측면 기판(1)의 하부에 저농도 소스 및 드레인(4)을 형성하는 단계(도2a)와; 상기 구조의 상부전면에 절연막을 증착하고, 그 절연막을 건식식각하여 상기 게이트의 측면에 측벽(5)을 형성한 후, 상기 측벽(5)의 측면에 노출된 저농도 소스 및 드레인(4) 영역의 상부측으로 선택적 에피 성장층(6)을 성장시키는 단계(도2b)와; 상기 선택적 에피 성장층(6)의 상부전면에 상부면이 평탄한 실리사이드(8)를 형성하는 단계(도2c)와; 상기 상부면이 평탄한 실리사이드(8)와 선택적 에피 성장층(6)을 이온주입버퍼로 사용하는 이온주입공정으로 상기 측벽(5)의 측면 기판(1) 하부에 고농도 소스 및 드레인(7)을 형성하는 단계(도2d)로 구성된다.2A to 2D are cross-sectional views of a manufacturing process of the MOS transistor according to the present invention. As shown therein, a gate oxide film 2 and a polysilicon 3 are deposited and patterned on the substrate 1 to form a gate. Forming a low concentration source and drain 4 under the side substrate 1 of the gate through an impurity ion implantation process (FIG. 2A); An insulating film is deposited on the upper surface of the structure, and the insulating film is dry etched to form sidewalls 5 on the side surfaces of the gate, and then the low concentration source and drain 4 regions exposed on the side surfaces of the sidewalls 5 are formed. Growing a selective epitaxial growth layer 6 to the top side (FIG. 2B); Forming a silicide 8 having a flat top surface on the top surface of the selective epitaxial growth layer 6 (FIG. 2C); A high concentration source and drain 7 is formed under the side substrate 1 of the sidewall 5 by an ion implantation process using the silicide 8 having the flat top surface and the selective epitaxial growth layer 6 as an ion implantation buffer. It consists of a step (Fig. 2d).
이하, 상기와 같이 구성된 본 발명 모스 트랜지스터 제조방법을 좀 더 상세히 설명한다.Hereinafter, the MOS transistor manufacturing method of the present invention configured as described above will be described in more detail.
먼저, 도2a에 도시한 바와 같이 반도체 기판(1)의 상부전면에 게이트산화막(2)과 다결정실리콘(3)을 증착하고, 사진식각공정을 통해 상기 다결정실리콘(3)과 게이트산화막(2)의 일부를 제거하여 게이트를 형성한다.First, as shown in FIG. 2A, the gate oxide film 2 and the polysilicon 3 are deposited on the upper surface of the semiconductor substrate 1, and the polysilicon 3 and the gate oxide film 2 are formed by a photolithography process. Remove part of it to form a gate.
그 다음, 특정 도전형의 불순물 이온을 저농도로 주입하여 상기 게이트의 측면 기판(1)의 하부에 저농도 소스 및 드레인(4)을 형성한다.Next, a low concentration source and drain 4 are formed in the lower portion of the side substrate 1 of the gate by implanting impurity ions of a specific conductivity type at a low concentration.
그 다음, 도2b에 도시한 바와 같이 상기 구조의 상부전면에 절연막을 증착하고, 그 증착된 절연막을 건식식각하여 측벽(5)을 형성한다.Next, as shown in FIG. 2B, an insulating film is deposited on the upper surface of the structure, and the sidewall 5 is formed by dry etching the deposited insulating film.
그 다음, 종래와 동일한 방법으로 상기 측벽(5)의 측면 하부측에서 노출된 저농도 소스 및 드레인(4)의 상부측에만 단결정실리콘층을 성장시켜 상기 측벽(5)과의 접촉부가 다른 곳에 비하여 얇게 형성되어지는 선택적 에피 성장층(6)을 형성한다.Then, a single crystal silicon layer is grown only on the upper side of the low concentration source and drain 4 exposed at the lower side of the side wall 5 in the same manner as the conventional method, so that the contact portion with the side wall 5 is thinner than other places. The selective epitaxial growth layer 6 to be formed is formed.
그 다음, 도2c에 도시한 바와 같이 상기 선택적 에피 성장층(6)의 상부에 실리사이드(8)를 형성한다. 이때의 실리사이드(8)는 그 상부면이 평탄하도록 형성한다.Next, as illustrated in FIG. 2C, silicide 8 is formed on top of the selective epitaxial growth layer 6. At this time, the silicide 8 is formed so that its upper surface is flat.
그 다음, 도2d에 도시한 바와 같이 상기 실리사이드(8)와 선택적 에피 성장층(6)을 이온주입의 버퍼로 사용하는 이온주입공정으로 상기 선택적 에피 성장층(6)의 하부에 고농도 소스 및 드레인(7)을 형성한다.Next, as shown in FIG. 2D, a high concentration source and drain is formed under the selective epitaxial growth layer 6 by an ion implantation process using the silicide 8 and the selective epitaxial growth layer 6 as buffers for ion implantation. (7) is formed.
이때 고농도 소스 및 드레인(7)은 상기 버퍼로 사용하는 실리사이드(8)와 선택적 에피 성장층(6)의 두께가 균일하므로, 주입되는 이온의 깊이도 균일하게 되어 그 윤곽이 균일하게 형성된다.At this time, since the thick source and drain 7 have a uniform thickness of the silicide 8 and the selective epitaxial layer 6 used as the buffer, the depth of implanted ions is also uniform, and the contour is uniformly formed.
상기한 바와 같이 본 발명은 고농도 소스 및 드레인의 두께를 얇게 형성하기 위한 에피층을 성장시키고, 그 에피층의 불균일한 두께를 실리사이드의 형성으로 균일하게 함으로써, 주입되는 이온의 깊이를 균일하게 하여 고농도 소스 및 드레인의 윤곽을 균일하게 하여 모스 트랜지스터의 특성이 열화되는 것을 방지하는 효과가 있다.As described above, the present invention grows an epitaxial layer for forming a thin thickness of a high concentration source and a drain, and makes the non-uniform thickness of the epilayer uniform by the formation of silicide, thereby making the depth of implanted ions uniform and high concentration. The contour of the source and drain can be made uniform to prevent deterioration of the characteristics of the MOS transistor.
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