KR20000041699A - Manufacturing method of mos transistor - Google Patents
Manufacturing method of mos transistor Download PDFInfo
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- KR20000041699A KR20000041699A KR1019980057653A KR19980057653A KR20000041699A KR 20000041699 A KR20000041699 A KR 20000041699A KR 1019980057653 A KR1019980057653 A KR 1019980057653A KR 19980057653 A KR19980057653 A KR 19980057653A KR 20000041699 A KR20000041699 A KR 20000041699A
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- forming
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- drain
- mos transistor
- epitaxial layer
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 230000002265 prevention Effects 0.000 claims description 2
- 238000004904 shortening Methods 0.000 abstract 1
- 150000004767 nitrides Chemical class 0.000 description 11
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 238000005468 ion implantation Methods 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 239000012535 impurity Substances 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 4
- 229910021342 tungsten silicide Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Abstract
Description
본 발명은 모스 트랜지스터 제조방법에 관한 것으로, 특히 소스 및 드레인 사이의 기판영역에 채널영역과 평행하게 절연층을 형성하여, 펀치 쓰루(PUNCH THROUGH)를 방지하는데 적당하도록 한 모스 트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS transistor manufacturing method, and more particularly, to a MOS transistor manufacturing method in which an insulating layer is formed in a substrate region between a source and a drain in parallel with a channel region so as to be suitable for preventing punch through. .
일반적으로, 256M DRAM 급인 0.2
도1a 내지 도1c는 종래 모스 트랜지스터 제조공정 수순단면도로서, 이에 도시한 바와 같이 기판(1)에 필드산화막(2)을 형성하고, 그 필드산화막(2)이 형성된 기판(1)의 상부전면에 게이트산화막(3), 다결정실리콘(4), 텅스텐 실리사이드(5), 산화막(6), 질화막(7)을 순차적으로 증착하는 단계(도1a)와; 사진식각공정을 통해 상기 증착된 질화막(7), 산화막(6), 텅스텐 실리사이드(5), 다결정실리콘(4), 게이트산화막(3)의 일부를 순차적으로 식각하여 게이트를 형성하고, 그 게이트의 측면 기판(1) 하부에 저농도 불순물 이온을 이온주입하여 저농도 소스 및 드레인(8)을 형성하는 단계(도1b)와; 상기 게이트의 측면에 측벽(9)을 형성하고, 불순물 이온을 이온주입하여 고농도 소스 및 드레인(10)을 형성하는 단계(도1c)를 포함하여 구성된다.1A to 1C are cross-sectional views of a conventional MOS transistor manufacturing process, in which a field oxide film 2 is formed on a substrate 1 and a top surface of the substrate 1 on which the field oxide film 2 is formed. Depositing the gate oxide film 3, the polysilicon 4, the tungsten silicide 5, the oxide film 6, and the nitride film 7 sequentially (FIG. 1A); Through the photolithography process, a portion of the deposited nitride film 7, oxide film 6, tungsten silicide 5, polysilicon 4, and gate oxide film 3 are sequentially etched to form a gate, and Implanting low concentration impurity ions under the side substrate 1 to form a low concentration source and drain 8 (FIG. 1B); Forming a sidewall 9 on the side of the gate and implanting impurity ions to form a high concentration source and drain 10 (FIG. 1C).
이하, 상기와 같은 종래 모스 트랜지스터 제조방법을 좀 더 상세히 설명한다.Hereinafter, a method of manufacturing the conventional MOS transistor as described above will be described in more detail.
먼저, 도1a에 도시한 바와 같이 기판(1)의 상부에 포토레지스트를 도포하고, 노광 및 현상하여 상기 기판(1)의 일부를 노출시키는 패턴을 형성하고, 그 노출된 기판(1)을 식각하여 트랜치구조를 형성한 후, 상기 포토레지스트를 제거하고 그 트랜치구조가 형성된 기판(1)의 상부전면에 산화막을 증착하고, 평탄화하여 상기 트랜치구조 내에 위치하는 필드산화막(2)을 형성한다.First, as shown in FIG. 1A, a photoresist is applied on an upper portion of the substrate 1, exposed and developed to form a pattern for exposing a part of the substrate 1, and the exposed substrate 1 is etched. After the formation of the trench structure, the photoresist is removed and an oxide film is deposited on the upper surface of the substrate 1 on which the trench structure is formed, and then planarized to form a field oxide film 2 positioned in the trench structure.
그 다음, 상기 필드산화막(2)이 형성된 기판(1)의 상부전면에 게이트산화막(3), 다결정실리콘(4), 텅스텐 실리사이드(5), 산화막(6), 질화막(7)을 순차적으로 증착한다.Subsequently, the gate oxide film 3, the polycrystalline silicon 4, the tungsten silicide 5, the oxide film 6, and the nitride film 7 are sequentially deposited on the upper surface of the substrate 1 on which the field oxide film 2 is formed. do.
그 다음, 도1b에 도시한 바와 같이 상기 질화막(7)의 상부전면에 포토레지스트를 도포하고, 노광 및 현상하여 패턴을 형성한 후, 그 패턴이 형성된 포토레지스트를 식각마스크로 사용하는 식각공정으로, 상기 순차적으로 증착된 질화막(7), 산화막(6), 텅스텐 실리사이드(5), 다결정실리콘(4) 및 게이트산화막(3)을 식각하여 게이트와 그 게이트를 보호하는 캡(CAP) 층을 형성한다.Next, as shown in FIG. 1B, a photoresist is applied to the upper surface of the nitride film 7, exposed and developed to form a pattern, and then the photoresist on which the pattern is formed is used as an etching mask. Etching the sequentially deposited nitride film 7, oxide film 6, tungsten silicide 5, polysilicon 4 and gate oxide film 3 to form a gate and a cap layer protecting the gate. do.
그 다음, 상기 포토레지스트를 제거하고, 상기 게이트의 최상층인 질화막(7)을 이온주입마스크로 사용하는 이온주입공정으로, 상기 게이트의 측면 기판(1) 하부에 저농도 소스 및 드레인(8)을 형성한다.Then, the photoresist is removed, and an ion implantation process using the nitride layer 7, which is the uppermost layer of the gate, as an ion implantation mask, forms a low concentration source and drain 8 under the side substrate 1 of the gate. do.
그 다음, 도1c에 도시한 바와 같이 상기 저농도 소스 및 드레인(8)과 게이트의 상부전면에 절연막을 증착하고, 그 절연막을 건식식각하여 상기 게이트의 측면에 측벽(9)을 형성한다.Then, as shown in FIG. 1C, an insulating film is deposited on the low concentration source and drain 8 and the upper surface of the gate, and the sidewall 9 is formed on the side of the gate by dry etching the insulating film.
그 다음, 상기 측벽(9) 및 질화막(7)을 이온주입마스크로 사용하는 이온주입공정으로, 고농도 불순물 이온을 이온주입하여 상기 측벽(9)의 측면 기판(1) 하부에 고농도 소스 및 드레인(10)을 형성한다.Next, in the ion implantation process using the sidewall 9 and the nitride film 7 as an ion implantation mask, high concentration impurity ions are implanted to form a high concentration source and drain under the side substrate 1 of the sidewall 9. 10) form.
그러나, 상기와 같은 종래 모스 트랜지스터 제조방법은 반도체 장치의 집적화가 심화되면서, 채널영역인 상기 저농도 소스와 저농도 드레인 사이가 짧아지게 되고, 이에 따라 펀치 쓰루(PUNCH THROUGH)가 발행하여 모스 트랜지스터의 특성이 열화되는 문제점이 있었다.However, in the conventional method of manufacturing a MOS transistor, as the integration of a semiconductor device is intensified, a short distance between the low concentration source and the low concentration drain, which is a channel region, is shortened. There was a problem of deterioration.
이와 같은 문제점을 감안한 본 발명은 채널길이가 짧아지는 경우에도, 펀치 쓰루현상을 방지할 수 있는 모스 트랜지스터 제조방법을 제공함에 그 목적이 있다.It is an object of the present invention to provide a MOS transistor manufacturing method capable of preventing punch through phenomenon even when the channel length is shortened.
도1a 내지 도1c는 종래 모스 트랜지스터 제조공정 수순단면도.1A to 1C are cross-sectional views of a conventional MOS transistor manufacturing process.
도2a 내지 도2d는 본 발명 모스 트랜지스터 제조공정 수순단면도.2A to 2D are cross-sectional views of a MOS transistor manufacturing process of the present invention.
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
21:기판 22:절연막21: substrate 22: insulating film
23:에피층 24:필드산화막23: epi layer 24: field oxide film
25:게이트 26:저농도 소스 및 드레인25: gate 26 low concentration source and drain
27:측벽 28:고농도 소스 및 드레인27: side wall 28: high concentration source and drain
상기와 같은 목적은 기판 상에 절연막 패턴을 형성하고, 그 절연막 패턴이 형성된 기판에 상기 절연막 패턴이 매몰되도록 에피층을 성장시키는 펀치쓰루 방지막 및 소자형성영역 형성단계와; 상기 절연막 패턴의 상부영역에 해당하는 에피층의 상부에 게이트를 형성하는 게이트 형성단계와; 상기 게이트의 측면 에피층 하부에 저농도 소스 및 드레인을 형성하는 저농도 소스 및 드레인 형성단계와; 상기 게이트의 측면에 측벽을 형성하고, 상기 측벽의 측면 에피층 하부에 고농도 소스 및 드레인을 형성하는 고농도 소스 및 드레인 형성단계를 포함하여 구성함으로써 달성되는 것으로, 이와 같은 본 발명을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.The above object is achieved by forming an insulating film pattern on a substrate, and forming a punch-through prevention film and an element formation region for growing an epitaxial layer so that the insulating film pattern is buried in the substrate on which the insulating film pattern is formed; A gate forming step of forming a gate over an epitaxial layer corresponding to an upper region of the insulating layer pattern; A low concentration source and drain forming step of forming a low concentration source and drain under the side epitaxial layer of the gate; It is achieved by forming a sidewall on the side of the gate, and a high concentration source and drain forming step of forming a high concentration source and drain under the side epilayer of the sidewall, see the accompanying drawings of the present invention When described in detail as follows.
도2a 내지 도2d는 본 발명 모스 트랜지스터 제조공정 수순단면도로서, 이에 도시한 바와 같이 기판(21)의 상부에 절연막(22)을 증착하고, 사진식각공정을 통해 상기 절연막(22)을 패터닝하는 단계(도2a)와; 상기 절연막(22) 패턴이 상부에 형성된 기판(21)을 시드(SEED)로 하는 단결정성장에 의해 상기 절연막(22)을 매몰시키는 에피층(23)을 형성하고, 상기 절연막(22) 패턴과 소정거리 이격된 위치의 에피층(23) 및 그 하부의 기판(21)에 필드산화막(24)을 형성하는 단계(도2b)와; 상기 에피층(23)의 상부전면에 게이트산화막, 다결정실리콘, 실리사이드, 산화막 및 질화막을 순차적으로 증착하고, 패터닝하여 상기 절연막(22) 패턴의 상부영역에 해당하는 에피층(23) 상에 게이트(25)를 형성하고, 그 게이트(25)의 측면 에피층(23) 하부에 저농도 소스 및 드레인(26)을 형성하는 단계(도2c)와; 상기 게이트(25)의 측면에 측벽(27)을 형성하고, 그 측벽(27)의 측면 하부 에피층(23)에 고농도 소스 및 드레인(28)을 형성하는 단계(도2d)로 구성된다.2A through 2D are cross-sectional views of a manufacturing method of a MOS transistor according to an embodiment of the present invention, in which an insulating film 22 is deposited on an upper portion of a substrate 21, and then the insulating film 22 is patterned through a photolithography process. (FIG. 2A); An epitaxial layer 23 is formed in which the insulating film 22 is buried by single crystal growth using the substrate 21 having the pattern of the insulating film 22 formed thereon as a seed (SEED). Forming a field oxide film 24 on the epitaxial layer 23 at a distance and the substrate 21 below it (FIG. 2B); The gate oxide film, the polysilicon, the silicide, the oxide film, and the nitride film are sequentially deposited on the upper surface of the epitaxial layer 23, and patterned to form a gate on the epitaxial layer 23 corresponding to the upper region of the insulating film 22 pattern. 25, and forming a low concentration source and drain 26 under the side epi layer 23 of the gate 25 (FIG. 2C); A sidewall 27 is formed on the side of the gate 25, and a high concentration source and drain 28 are formed on the lower side epi layer 23 on the sidewall 27 (FIG. 2D).
이하, 상기와 같이 구성된 본 발명 모스 트랜지스터 제조방법을 좀 더 상세히 설명한다.Hereinafter, the MOS transistor manufacturing method of the present invention configured as described above will be described in more detail.
먼저, 도2a에 도시한 바와 같이 기판(21)의 상부에 산화막 등의 절연막(22)을 증착하고, 사진식각공정을 통해 상기 절연막(22)을 패터닝하여 염원하는 채널의 크기와 동일한 크기의 절연막(22) 패턴을 형성한다. 이때 절연막(22)의 두께는 400~700
그 다음, 도2b에 도시한 바와 같이 상기 절연막(22) 패턴이 형성된 기판(1)을 단결정성장시켜, 에피층(23)을 형성한다. 이때의 에피층(23)은 모스 트랜지스터가 실질적으로 형성될 기판으로 작용하며, 상기 절연막(22)의 상부측으로 500
그 다음, 사진식각공정을 통해 상기 형성된 절연막(22) 패턴으로 부터 소정거리 이격되도록 트랜치구조를 형성하고, 그 트랜치구조가 형성된 에피층(23)의 상부전면에 산화막을 증착하고, 평탄화하여 상기 트랜치구조 내에 위치하는 필드산화막(24)을 형성한다.Next, a trench structure is formed to be spaced apart from the formed insulating layer 22 pattern by a photolithography process, an oxide film is deposited on the upper surface of the epi layer 23 on which the trench structure is formed, and the planarized trench is formed. A field oxide film 24 located in the structure is formed.
그 다음, 도2c에 도시한 바와 같이 상기 필드산화막(24)이 형성된 에피층(23)의 상부전면에 게이트산화막, 다결정실리콘, 실리사이드, 산화막 및 질화막을 순차적으로 증착한다.Then, as shown in FIG. 2C, a gate oxide film, a polycrystalline silicon, a silicide, an oxide film, and a nitride film are sequentially deposited on the upper surface of the epitaxial layer 23 on which the field oxide film 24 is formed.
그 다음, 상기 최상층에 증착된 질화막의 상부에 포토레지스트를 도포하고, 노광 및 현상하여 게이트 패턴을 형성한 후, 그 패턴이 형성된 포토레지스트를 식각마스크로 사용하는 식각공정으로, 상기 절연막(22) 패턴의 상부영역에 해당하는 에피층(23)의 상부에 게이트(25)를 형성한다.Next, a photoresist is applied over the nitride film deposited on the uppermost layer, exposed and developed to form a gate pattern, and an etching process using the photoresist on which the pattern is formed as an etching mask is performed. The gate 25 is formed on the epi layer 23 corresponding to the upper region of the pattern.
그 다음, 상기 포토레지스트 패턴을 제거하고, 불순물 이온을 이온주입하여 상기 게이트(25)의 측면 에피층(23) 하부에 저농도 소스 및 드레인(26)을 형성한다. 이때, 저농도 소스 및 드레인(26)은 상기 절연막(22) 패턴의 상부측인 500
그 다음, 도2d에 도시한 바와 같이 상기 저농도 소스 및 드레인(26)과 게이트(25)의 상부전면에 절연막을 증착하고, 건식식각하여 상기 게이트(25)의 측면에 측벽(27)을 형성한다.Next, as shown in FIG. 2D, an insulating film is deposited on the low concentration source and drain 26 and the upper surface of the gate 25, and dry-etched to form sidewalls 27 on the side of the gate 25. .
그 다음, 상기 게이트의 최상층인 질화막과 상기 측벽(27)을 이온주입 마스크로 하는 이온주입공정으로 상기 측벽(27)의 측면 에피층(23) 하부에 고농도 소스 및 드레인(28)을 형성한다.Next, a high concentration source and drain 28 is formed under the side epitaxial layer 23 of the sidewall 27 by an ion implantation process using the nitride layer, which is the uppermost layer of the gate, and the sidewall 27 as an ion implantation mask.
이와 같이 본 발명은 상기 채널영역 하부측인 저농도 소스와 드레인의 사이에 절연층을 형성하여 펀치쓰루의 발생을 방지할 수 있다. 이와 같이 기판의 하부에 절연막을 형성한 구조인 실리콘 온 인슐레이터(silicon on insulator)구조는 플로팅(floating)이 발생할 수 있으나, 본 발명에서와 같이 소스와 드레인 사이에만 절연층을 형성하는 구조는 실리콘 온 인슐레이터 구조의 문제인 플로팅이 발생하지 않게 된다.As described above, the present invention can prevent the occurrence of punchthrough by forming an insulating layer between the low concentration source and the drain which is the lower side of the channel region. As described above, the silicon on insulator structure, which is a structure in which an insulating layer is formed on the lower portion of the substrate, may float, but the structure in which the insulating layer is formed only between the source and the drain may be silicon on. Floating, which is a problem of the insulator structure, does not occur.
상기한 바와 같이 본 발명은 모스 트랜지스터를 형성하기 이전에 소스와 드레인의 사이영역에 절연막을 형성함으로써, 펀치 쓰루현상이 발생하는 것을 방지하여 모스 트랜지스터의 특성을 향상시키는 효과가 있다.As described above, the present invention has an effect of improving the characteristics of the MOS transistor by preventing the punch-through phenomenon by forming an insulating film in the region between the source and the drain before forming the MOS transistor.
Claims (3)
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|---|---|---|---|
| KR1019980057653A KR20000041699A (en) | 1998-12-23 | 1998-12-23 | Manufacturing method of mos transistor |
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| KR1019980057653A KR20000041699A (en) | 1998-12-23 | 1998-12-23 | Manufacturing method of mos transistor |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100473476B1 (en) * | 2002-07-04 | 2005-03-10 | 삼성전자주식회사 | Semiconductor device and Method of manufacturing the same |
| KR100493018B1 (en) * | 2002-06-12 | 2005-06-07 | 삼성전자주식회사 | Method for fabricating a semiconductor device |
-
1998
- 1998-12-23 KR KR1019980057653A patent/KR20000041699A/en not_active Application Discontinuation
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100493018B1 (en) * | 2002-06-12 | 2005-06-07 | 삼성전자주식회사 | Method for fabricating a semiconductor device |
| KR100473476B1 (en) * | 2002-07-04 | 2005-03-10 | 삼성전자주식회사 | Semiconductor device and Method of manufacturing the same |
| US7009255B2 (en) | 2002-07-04 | 2006-03-07 | Samsung Electronics Co., Ltd. | Semiconductor device having punch-through structure off-setting the edge of the gate electrodes |
| US7259069B2 (en) | 2002-07-04 | 2007-08-21 | Samsung Electronics Co., Ltd. | Semiconductor device and method of manufacturing the same |
| US7268043B2 (en) | 2002-07-04 | 2007-09-11 | Samsung Electronics Co., Ltd. | Semiconductor device and method of manufacturing the same |
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