KR20020031493A - A forming method of local interconnection using shorting stopper and etching stopper - Google Patents

Abstract

PURPOSE: A local metallization method of semiconductor devices is provided to enhance an etch margin and to prevent a short between a conductive pattern and a gate electrode by using a short prevention insulating layer and an etch stopper. CONSTITUTION: A gate pattern(130) having a short prevention insulating layer(1000) is formed on a semiconductor substrate(110). A capping layer(140) is formed on the gate pattern. After depositing a first insulating layer(150) on the capping layer, a CMP is performed by using the capping layer as a polishing stopper. After forming a second insulating layer(160) on the resultant structure, a contact plug(200) is formed by sequentially patterning the second and first insulating layers and the capping layer. An etch stopper(170) and a third insulating layer(180) are sequentially formed on the resultant structure. Then, a bit line(190) is formed to connect to the contact plug. Preferably, a first etch stopper(2000) is formed on the first insulating layer(150).

Description

A forming method of local interconnection using shorting stopper and etching stopper}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming local wiring using an insulating film for preventing short circuits and an etch stop film.

As the semiconductor devices are highly integrated, the application of the local wiring forming process is generally increasing, and the local wiring forming process is being actively applied to DRAM and SRAM cells.

FIG. 1 is a cross-sectional view illustrating a method of forming a local wiring of a semiconductor device according to the prior art.

Referring to FIG. 1, the contact plug 100 is connected to an impurity region 20 of the semiconductor substrate 10 at a lower side thereof, and is connected to a conductive pattern at an upper side thereof, for example, to a bit line 90 in the case of a DRAM device. The impurity region 20 and the bit line 90 of the substrate 10 are electrically connected to each other.

As the design rule becomes smaller, the space area between the gate patterns 30 becomes narrower. Accordingly, the contact plug 100 has a relatively thin and long shape, and thus the upper bit line 90 and the lower semiconductor. The impurity regions 20 of the substrate are connected. In order to form the contact plug 100, the insulating holes 50 and the capping film 40 must be etched to form contact holes, but the thick insulating film 50 makes it difficult to etch deep contact holes.

Furthermore, even if the contact plug 100 is formed by forming a contact hole and filling a conductive material, the contact plug 100 has a thin portion connected to the impurity region 20 of the semiconductor substrate 10 to increase resistance. The bottom of the contact plug 100 is not connected to the impurity region 20 of the semiconductor substrate 10 at all.

In order to solve this problem, the step difference of the insulating film is lowered, but the low step level of the insulating film causes a phenomenon of insufficient etching margin during the etching process for forming the bit line 90.

In the etching process for forming the bit line 90, the etch stop layer 70 was formed to prevent etching, but since there are minute errors in the etching selectivity and the uniformity and flatness of the wafer, the bit line 90 may be formed using the gate electrode pattern ( 30) is formed close to the capping film 40 formed thereon. Therefore, the lack of an etching margin provides a cause of short circuit between the bit line 90 and the gate electrode of the gate pattern 30.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of forming local wirings of a semiconductor device for solving an etching margin according to a height of an insulating layer and a short phenomenon between a conductive pattern and a gate pattern.

1 is a cross-sectional view illustrating a method for forming a local wiring of a semiconductor device according to the prior art.

2 to 6 are cross-sectional views illustrating a method for forming local wirings of a semiconductor device in accordance with a first embodiment of the present invention.

7 to 9 are cross-sectional views illustrating a method for forming local wirings of a semiconductor device in accordance with a second embodiment of the present invention.

10 is a cross-sectional view illustrating a method of forming local wirings of a semiconductor device in accordance with a third embodiment of the present invention.

<Description of Signs of Major Parts of Drawings>

110: semiconductor substrate 120: impurity region of the substrate

130: gate pattern 131: oxide film

132 polysilicon 133: silicide

134: spacer 140: capping film

150: first insulating film 160: second insulating film

170: second etch stop film 180: third insulating film

190: bit line 200: contact plug

1000: short circuit prevention insulating film 2000: first etch stop film

In the method for forming a local wiring of a semiconductor device according to an aspect of the present invention for solving the above technical problem, after forming a gate pattern formed on top of an insulating film for preventing short circuit on a semiconductor substrate, and forming a capping film on the gate pattern, A CMP is performed by depositing a first insulating film on the capping film and using the capping film as an abrasive blocking layer. Subsequently, a second insulating layer is formed on the first insulating layer, and the second insulating layer, the first insulating layer, and the capping layer are patterned to form a contact plug connected to an impurity region of the semiconductor substrate. Subsequently, an etch stop layer is formed on the resultant, a third insulating layer is formed on the etch stop layer, and the insulating layers are etched to form a conductive pattern connected to the contact plug.

Here, after the CMP using the capping layer as the polishing blocking layer, the etch stop layer may be further formed on the first insulating layer. The etch stop layer is preferably formed of any one selected from the group consisting of SiN, SiON, BN, and CN.

In addition, the short-circuit prevention insulating film is formed of any one selected from the group of insulating films consisting of SiN, SiON, BN, CN, it is preferable that the thickness is formed in the range of 300 kPa to 1000 kPa.

Preferably, the second insulating film is formed of any one of BPSG and FOx, and has a thickness in the range of 500 mW to 2000 mW.

According to a preferred embodiment of the present invention, the conductive pattern forms word lines in SRAM and bit lines in DRAM.

According to another aspect of the present invention, there is provided a method of forming a local wiring of a semiconductor device. A gate pattern is formed on a semiconductor substrate, a capping layer is formed on the gate pattern, and a first insulating layer is formed on the chipping layer. Deposit and run CMP. Subsequently, a first etch stop layer is formed on the first insulating layer, a second insulating layer is formed on the first etch stop layer, and the second insulating layer, the first etch stop layer, the first insulating layer, and the capping layer are patterned to form a semiconductor. A contact plug connected to the impurity region of the substrate is formed. Subsequently, a second etch stop layer and a third insulating layer are sequentially formed on the resultant, and the insulating layers are etched to form a conductive pattern connected to the contact plug.

Here, the second insulating film is formed of any one of BPSG and FOx, the thickness is preferably formed in the range of 500 kPa to 2000 kPa.

In addition, the etch stop layer is formed of any one selected from the group consisting of SiN, SiON, BN, CN, the thickness is preferably formed in the range of 100 to 1000 kHz.

According to preferred embodiments of the present invention, the conductive pattern forms a word line in an SRAM and a bit line in a DRAM.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present embodiment is not limited to the embodiments disclosed below, but will be implemented in various forms, and only these embodiments are intended to complete the disclosure of the present invention, and fully scope the scope of the invention to those skilled in the art. It is provided to inform you.

2 to 6 are cross-sectional views illustrating a method for forming mutual wirings according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view of a semiconductor substrate (a gate pattern 130 having a short circuit prevention insulating film 1000 formed thereon). It is sectional drawing shown in order to demonstrate the formation on 110).

Referring to FIG. 2, the gate pattern 130 may include a gate oxide layer 131, a polysilicon layer 132, a silicide layer 133, and an insulating film 1000 for preventing short circuits on the semiconductor substrate 110. Etch it. Subsequently, an insulating film for spacers, for example, an oxide film such as an oxide film is stacked on the entire surface of the semiconductor substrate, and then spacers 134 are formed by anisotropic etching. Subsequently, impurities are implanted into the semiconductor substrate 110 to form the impurity region 120.

The silicide film 133 is formed by stacking a tungsten film on the polysilicon film 132 and subsequently performing heat treatment and cleaning to reduce the resistance by changing the tungsten film into a tungsten-silicon film.

The short-circuit prevention insulating layer 133 prevents a short by keeping the silicide layer 133, which is a conductive material of the bit line and the gate pattern 130, when the bit line is formed (see 190 in FIG. 6). Do this. For this purpose, the short-circuit prevention insulating film 133 may be formed to have a thickness of 300 mW to 1000 mW. The short-circuit prevention insulating film 133 may use a material selected from SiN, SiON, BN, or CN.

The spacer 134 serves to prevent damage to the gate pattern 130 when forming the contact hole and is formed of a nitride film. The impurity region 120 is formed by ion implantation and heat treatment of an n-type or p-type impurity according to a metal oxide silicon (MOS) structure.

3 illustrates a process of forming a capping layer 140 on the gate pattern 130 on the semiconductor substrate 110, and then stacking the first insulating layer 150 and performing CMP using the capping layer 140 as an abrasive blocking layer. It is shown.

Referring to FIG. 3, the capping layer 140 is formed of a material of SiN or SiON, and in order to minimize the height between the impurity region 120 and the bit line (see 190 of FIG. 6) of the semiconductor substrate 110. CMP treatment is performed to the top of the capping layer 140. Since the short-circuit prevention insulating film 1000 is provided even when CMP is performed to the top of the capping film 140, even when the bit line 190 of FIG. 6 is formed to the capping film 140 in a subsequent process, the silicide 133 is uniform with the silicide 133. The distance is maintained and no shorting problem occurs.

4, after stacking and planarizing the second insulating layer 160 on the first insulating layer 150, the second insulating layer 160 and the first insulating layer 150 are exposed to expose the impurity region 120 of the semiconductor substrate 110. ) And the capping layer 140 are etched to form a contact hole, and then a cross-sectional view of filling a conductive material in the contact hole is illustrated.

The second insulating layer 160 is an oxide protective layer formed using a film such as BPSG or FOx having a flow characteristic as a film formed to prevent scratches during a subsequent CMP process.

If the stepped portion of the second insulating layer 160 is high, the contact plug 200 becomes thinner at the portion where the contact plug 200 is connected to the impurity region 120 of the semiconductor substrate, thereby increasing resistance, or the lowermost portion of the contact plug 200 has impurities in the semiconductor substrate. The phenomenon of not being connected to the region 120 occurs at all, which causes a fatal error in the operation of the semiconductor device. Therefore, the thickness of the second insulating layer 160 is preferably reduced as much as possible within the range that no short is generated between the bit line 190 of FIG. 6 and the silicide 133 of the gate pattern. As a result, the thickness of the second insulating layer 160 is preferably in the range of 500 kV to 2000 kV.

Tungsten is preferably used as the conductive material to fill the contact hole.

5 is a cross-sectional view illustrating a process of forming an etch stop layer 170 on the second insulating layer 160 and the contact plug 200.

The etch stop layer 170 primarily blocks the etching when the etching process is performed to form the bit line 190 (FIG. 6). The etch stop layer 170 is preferably any one selected from SiN, SiON, BN or CN, the thickness is preferably formed in the range of 100 ~ 1000Å.

6 is a cross-sectional view illustrating a process of forming the third insulating layer 180 on the etch stop layer 170 and forming the bit line 190 to be connected to the contact plug 200 at the bottom.

The bit line 190 is most preferably formed by etching only the third insulating layer 180 and the etch stop layer 170 and then filling the conductive material, but actually only the third insulating layer 180 and the etch stop layer 170 are formed. As shown in FIG. 6, the third insulating layer 170, the etch stop layer 170, the second insulating layer 180, the first insulating layer 150, and the capping layer may be formed due to the etching selectivity and the uniformity of the wafer during etching. Up to a portion of 140 may be etched. In severe cases, the short-circuit prevention insulating film 1000 may be etched to expose the short-circuit prevention insulating film 1000. However, since the etching rate is reduced in the hard etch stop layer 170 and the capping layer 140, the hard short-circuit preventing insulating layer 1000 is no longer etched. Therefore, the short-circuit prevention insulating film 1000 serves to prevent short between the silicide layer 133 and the bit line 190, thereby increasing the etching margin during the etching process for forming the bit line.

As a result, the first insulating film 150 in which the contact plug is formed by controlling the thickness of the second insulating film 160 in the process of performing CMP using the capping film 140 as the polishing blocking layer and forming the second insulating film 160; The step difference of the second insulating layer 160 may be lowered, and the short phenomenon occurring between the silicide 133 and the bit line of the gate pattern may be prevented by using the insulating film 1000 for preventing short circuits.

The bit line 190 has been described taking the case of a DRAM structure as an example, and the case of the structure of an SRAM can be applied to the above embodiment by replacing the bit line 190 with a word line.

7 to 9 are cross-sectional views illustrating a method for forming local wirings of a semiconductor device in accordance with a second embodiment of the present invention. Compared with the first embodiment, the second embodiment forms only two etch stop layers 2000 and 170 without forming a short circuit prevention insulating film, thereby forming local wiring. Hereinafter, in the second embodiment, the same process and materials are not mentioned in comparison with the first embodiment, and the description will be given based on the difference.

FIG. 7 is a cross-sectional view illustrating a process from forming the gate pattern 130 to forming the first etch stop layer 2000.

Referring to FIG. 7, a gate pattern 130 is formed on the semiconductor substrate 110, and a capping layer 140 is formed on the gate pattern 130. Subsequently, CMP is performed after stacking the first insulating layer 150 on the gate pattern 130. Subsequently, a first etch stop layer 2000 is formed on the first insulating layer 150.

Here, unlike the first embodiment described above, the gate pattern 130 is formed without an insulating film for preventing a short circuit on the silicide 133. In addition, when CMPing the first insulating layer 150, CMP is not performed until the capping layer 140 is exposed as in the first embodiment. This is because in the second embodiment, since there is no short-circuit prevention insulating film in the first embodiment described above, a short may occur between the bit line 190 and the silicide 133 of the gate pattern. For example, the polishing degree of the CMP is polished so that the thickness from the capping film 140 to the CMP surface is in the range of 500 kPa to 2000 kPa.

During the etching process for forming the bit line 190, which is a conductive pattern, the first etch stop layer 2000 serves to prevent the etching further below the first etch stop layer 2000. Preference is given to using the material of either BN or CN.

8 is a cross-sectional view illustrating a process of forming a contact plug 200 and forming a second etch stop layer 170 after forming the second insulating layer 160 on the first etch stop layer 2000. 9 is a cross-sectional view illustrating a process of forming a bit line 190 as a conductive pattern by etching the third insulating layer 180 and the second insulating layer 160 after forming the third insulating layer 180. As a result, the forming process, the material, and the like are the same as in the above-described first embodiment.

8 and 9, the second etch stop layer 170 primarily blocks the etching during the etching process for forming the bit line 190, and the first etch stop layer 2000 is no longer used. It prevents etching. In principle, the bit line must be formed by filling only the third insulating layer 180 and the second etch stop layer 170 to fill the conductive material. However, the second insulating layer 160 is also etched due to the etching selectivity and the wafer unevenness. Becomes Therefore, the first etch stop layer 2000 increases the etching margin during the etching process for forming the bit line.

10 is a cross-sectional view illustrating a method of forming local wirings of a semiconductor device in accordance with a third embodiment of the present invention. The third embodiment includes a structure including both the first embodiment and the second embodiment, and the procedures, functions, materials, and the like of the local wiring forming process refer to the first embodiment and the second embodiment.

Referring to FIG. 10, a short circuit prevention insulating film 1000 and a first etch stop film 2000 and a second etch stop film 170 may be provided. The heat may further reduce the short circuit between the silicide 133 and the bit line 190 of the gate pattern 130.

In the above-described embodiments, the bit line has been described taking the case of the DRAM structure as an example, and the case of the structure of the SRAM can be applied to the above-described embodiments by changing the bit line into a word line.

According to the interconnection forming method according to the present invention, by using the insulating film and the etch stop layer for preventing the short circuit as in the above embodiment, it is possible to increase the etching margin according to the height of the first insulating film and the second insulating film, which is connected to the semiconductor substrate The resistance occurring at the bottom of the contact plug can be reduced. In addition, a short between the conductive pattern and the gate electrode can be prevented.

Claims (14)

Forming a gate pattern on the semiconductor substrate, wherein the insulating film for preventing a short circuit is formed on the top; Forming a capping layer on the gate pattern; Depositing a first insulating film on the capping film and performing CMP using the capping film as an abrasive blocking layer; Forming a second insulating film on the first insulating film; Patterning the second insulating layer, the first insulating layer, and the capping layer to form a contact plug connected to the impurity region of the semiconductor substrate; Forming an etch stop layer on the resultant, and forming a third insulating layer on the etch stop layer; And Forming a conductive pattern connected to the contact plug by etching the insulating layers. The method of claim 1, further comprising forming an etch stop layer on the first insulating layer after CMPing the first insulating layer using the capping layer as an abrasive blocking layer. The method of claim 2, wherein the etch stop layer is formed of any one selected from the group consisting of SiN, SiON, BN, and CN. The method of forming a local wiring of a semiconductor device according to claim 1, wherein the short-circuit prevention insulating film is formed of any one selected from the group of insulating films consisting of SiN, SiON, BN, and CN. The method of forming a local wiring of a semiconductor device according to claim 1, wherein a thickness of the insulating film for preventing a short circuit is formed in a range of 300 mW to 1000 mW. The method of claim 1, wherein the second insulating layer is formed of any one of BPSG and FOx. The method of forming a local wiring of a semiconductor device according to claim 1, wherein the thickness of the second insulating film is in a range of 500 mW to 2000 mW. The method of claim 1, wherein the conductive pattern is used as a word line in an SRAM and a bit line in a DRAM. Forming a gate pattern on the semiconductor substrate; Forming a capping layer on the gate pattern; Depositing a first insulating film on the chipping film and executing CMP; Forming a first etch stop layer on the first insulating layer; Forming a second insulating layer on the first etch stop layer; Patterning the second insulating layer, the first etch stop layer, the first insulating layer, and the capping layer to form a contact plug connected to the impurity region of the semiconductor substrate; Sequentially forming a second etch stop layer and a third insulating layer on the resultant material; And Forming a conductive pattern connected to the contact plug by etching the insulating layers. The method of claim 9, wherein the second insulating layer is formed of any one of BPSG and FOx. The method of forming a local wiring of a semiconductor device according to claim 9, wherein the thickness of the second insulating film is in the range of 500 kV to 2000 kV. The method of claim 9, wherein the etch stop layer is formed of any one selected from the group consisting of SiN, SiON, BN, and CN. The method of claim 9, wherein the thickness of the etch stop layer is in a range of 100 kV to 1000 kV. 10. The method of claim 9, wherein the conductive pattern forms a word line in an SRAM and a bit line in a DRAM.