KR20020028492A - Method of forming a contact hole in a semiconductor device - Google Patents
Method of forming a contact hole in a semiconductor device Download PDFInfo
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- KR20020028492A KR20020028492A KR1020000059515A KR20000059515A KR20020028492A KR 20020028492 A KR20020028492 A KR 20020028492A KR 1020000059515 A KR1020000059515 A KR 1020000059515A KR 20000059515 A KR20000059515 A KR 20000059515A KR 20020028492 A KR20020028492 A KR 20020028492A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
Abstract
Description
본 발명은 반도체 소자의 콘택홀 형성 방법에 관한 것으로, 특히 탄소 화합물 또는 SiOC 계열의 화합물로 이루어진 제 1 절연막 및 산화물 계열의 제 2 절연막의 이중 구조로 층간 절연막을 형성한 후 콘택홀을 형성하기 위한 식각 공정 및 세정 공정을 실시하면 상부보다 바닥 부분이 더 넓은 콘택홀을 형성하여 접촉 저항을 안정적으로 확보할 수 있어 소자의 신뢰성을 향상시킬 수 있고, 동작 속도 및 수율을 향상시킬 수 있는 반도체 소자의 콘택홀 형성 방법에 관한 것이다.The present invention relates to a method for forming a contact hole in a semiconductor device, and in particular, to form a contact hole after forming an interlayer insulating film with a double structure of a first insulating film and an oxide-based second insulating film made of a carbon compound or a SiOC series compound. The etching process and the cleaning process form a contact hole with a wider bottom portion than the upper portion, thereby ensuring stable contact resistance, thereby improving the reliability of the device, and improving the operation speed and yield of the semiconductor device. It relates to a contact hole forming method.
반도체 소자의 집적도가 증가함에 따라 배선의 폭이 감소함과 동시에 콘택홀의 크기도 감소한다. 따라서 콘택홀의 크기에 대한 콘택홀의 깊이의 비(aspect ratio)가 증가한다. 그럼, 종래의 반도체 소자의 콘택홀 형성 방법을 도 1(a) 및 도 1(b)를 이용하여 설명한다.As the integration degree of the semiconductor device increases, the width of the wiring decreases and the size of the contact hole decreases. Therefore, the ratio ratio of the depth of the contact hole to the size of the contact hole increases. Then, a conventional method for forming a contact hole in a semiconductor device will be described with reference to FIGS. 1 (a) and 1 (b).
도 1(a)를 참조하면, 소정의 구조가 형성된 반도체 기판(11) 상부에 금속 배선(12)을 형성한다. 금속 배선(12)을 포함한 전체 구조 상부에 층간 절연막(13) 및 하드 마스크층(14)을 형성한다. 하드 마스크층(14) 상부에 감광막(15)을 형성한 후 노광 및 현상 공정을 실시하여 패터닝한다.Referring to FIG. 1A, a metal wiring 12 is formed on an upper portion of a semiconductor substrate 11 having a predetermined structure. An interlayer insulating film 13 and a hard mask layer 14 are formed over the entire structure including the metal wiring 12. After the photosensitive film 15 is formed on the hard mask layer 14, exposure and development processes are performed to pattern the photoresist film 15.
도 1(b)를 참조하면, 패터닝된 감광막(15)을 마스크로 하드 마스크층(14) 및 층간 절연막(13)을 식각하여 금속 배선(12)을 노출시키는 콘택홀(16)을 형성한다. 이후 감광막(15)을 제거하고, 식각 공정에서 생성되는 잔류물을 제거하기 위한 세정 공정을 실시한다.Referring to FIG. 1B, the hard mask layer 14 and the interlayer insulating layer 13 are etched using the patterned photoresist 15 as a mask to form a contact hole 16 exposing the metal wiring 12. Thereafter, the photoresist film 15 is removed and a cleaning process for removing residues generated in the etching process is performed.
상기와 같은 공정으로 높은 애스펙트비를 가지는 콘택홀을 형성하면, 콘택홀의 입구 크기에 비해 하지층과 접촉되는 콘택홀의 바닥 부분의 크기가 작게 형성된다. 콘택홀의 입구 크기와 바닥 부분의 크기의 차이는 콘택홀의 깊이 및 애스펙트비가 증가한다.When the contact hole having a high aspect ratio is formed by the above process, the size of the bottom portion of the contact hole in contact with the underlying layer is smaller than the contact hole inlet size. The difference between the size of the contact hole and the size of the bottom portion increases the depth and aspect ratio of the contact hole.
콘택홀의 입구 크기과 바닥 부분의 크기의 차이는 콘택의 접촉 저항을 확보하는데 지대한 문제를 야기시킨다. 즉, 콘택에서의 접촉 저항은 접촉하는 면적에 반비례하는 특성-일반적인 현상으로 전류가 흐를 때 저항은 면적에 반비례한다-이 있기 때문에 콘택홀의 바닥 부분의 크기가 감소하면 접촉 저항이 증가하게 된다.The difference between the size of the contact hole inlet and the size of the bottom portion causes a great problem in ensuring contact resistance of the contact. In other words, the contact resistance in the contact is inversely proportional to the contact area, which is a general phenomenon, and the resistance is inversely proportional to the current flow.
반도체 소자의 집적도가 더욱 증가하게 되면 콘택 크기가 감소함에 따라 약간의 크기 변화에 대하여도 접촉 저항은 크게 변화한다. 예를들어 콘택홀의 크기가 0.4㎛인 경우 0.04㎛의 크기 감소는 5%의 크기 감소에 해당하지만, 콘택홀의 크기가 0.2㎛인 경우 0.04㎛의 크기 감소는 10%의 크기 감소를 의미한다. 이를 콘택 면적으로 환산할 경우 각각 1.21배와 1.44배의 감소를 의미하며 이 값 만큼의 접촉 저항이 증가한다. 이러한 접촉 저항의 증가는 반도체 소자의 동작에 치명적인 영향을 초래한다.As the degree of integration of semiconductor devices increases further, the contact resistance changes significantly even with slight size changes as the contact size decreases. For example, when the size of the contact hole is 0.4 μm, the size reduction of 0.04 μm corresponds to a size reduction of 5%. However, when the size of the contact hole is 0.2 μm, the size reduction of 0.04 μm means a size reduction of 10%. When converted into contact area, it means 1.21 times and 1.44 times reduction, respectively, and the contact resistance increases by this value. This increase in contact resistance causes a fatal effect on the operation of the semiconductor device.
본 발명의 목적은 콘택홀의 입구보다 바닥 부분이 더 큰 콘택홀을 형성하여 접촉 저항을 감소시킬 수 있는 반도체 소자의 콘택홀 형성 방법을 제공하는데 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a contact hole in a semiconductor device capable of reducing contact resistance by forming a contact hole having a larger bottom portion than an entrance of a contact hole.
본 발명의 다른 목적은 식각률이 서로 다른 막으로 이중 층간 절연막을 형성하여 콘택홀을 형성할 때 안정적인 접촉 저항을 확보할 수 있어 소자의 신뢰성 및 동작 속도를 향상시킬 수 있는 반도체 소자의 콘택홀 형성 방법을 제공하는데 있다.Another object of the present invention is to form a double interlayer insulating film with a different etching rate to ensure a stable contact resistance when forming a contact hole, the method of forming a contact hole of a semiconductor device that can improve the reliability and operation speed of the device To provide.
본 발명에서는 금속 배선 상부에 탄소 화합물 또는 SiOC 계열의 화합물로 이루어진 제 1 절연막 및 산화물 계열의 제 2 절연막의 이중 구조로 층간 절연막을 형성한 후 콘택홀을 형성하기 위한 식각 공정 및 세정 공정을 실시하여 상부보다 바닥 부분이 더 넓은 콘택홀을 형성한다. 이에 의해 접촉 저항을 안정적으로 확보할 수 있어 소자의 신뢰성을 향상시킬 수 있고, 동작 속도 및 수율을 향상시킬 수 있다.In the present invention, an interlayer insulating film is formed in a double structure of a first insulating film and an oxide-based second insulating film made of a carbon compound or an SiOC series compound on the metal wiring, and then an etching process and a cleaning process are performed to form contact holes. The bottom portion forms a wider contact hole than the top portion. As a result, the contact resistance can be stably secured, the reliability of the device can be improved, and the operation speed and the yield can be improved.
도 1(a) 및 도 1(b)는 종래의 반도체 소자의 콘택홀 형성 방법을 설명하기 위해 도시한 소자의 단면도.1 (a) and 1 (b) are cross-sectional views of a device for explaining a method for forming a contact hole in a conventional semiconductor device.
도 2(a) 내지 도 2(c)는 본 발명에 따른 반도체 소자의 콘택홀 형성 방법을 설명하기 위해 도시한 소자의 단면도.2 (a) to 2 (c) are cross-sectional views of a device for explaining a method for forming a contact hole in a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for main parts of the drawings>
11 및 21 : 반도체 기판12 및 22 : 금속 배선11 and 21: semiconductor substrate 12 and 22: metal wiring
13 : 층간 절연막14 및 25 : 하드 마스크층13 interlayer insulating film 14 and 25 hard mask layer
15 및 26 : 감광막16 및 27 : 콘택홀15 and 26: photosensitive film 16 and 27: contact hole
23 : 제 1 절연막24 : 제 2 절연막23: first insulating film 24: second insulating film
본 발명에 따른 반도체 소자의 콘택홀 형성 방법은 소정의 구조가 형성된 반도체 기판 상부에 금속 배선을 형성하는 단계와, 상기 금속 배선을 포함한 전체 구조 상부에 탄소 화합물 또는 SiOC 게열의 화합물로 이루어진 제 1 절연막 및 산화물로 이루어진 제 2 절연막을 순차적으로 형성하여 이중 구조의 층간 절연막을 형성하는 단계와, 상기 층간 절연막 상부에 하드 마스크층 및 감광막 패턴을 형성하는 단계와, 상기 감광막 패턴을 마스크로 하드 마스크층, 제 2 절연막 및 제 1 절연막을 순차적으로 제거하여 콘택홀을 형성하는 단계와, 상기 감광막 패턴을 제거한 후 세정 공정을 실시하여 상기 제 1 절연막을 더 식각함으로써 상부보다 바닥 부분이 더 넓은 콘택홀을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.The method for forming a contact hole in a semiconductor device according to the present invention includes forming a metal wiring on an upper portion of a semiconductor substrate having a predetermined structure, and a first insulating layer formed of a compound of carbon compound or SiOC sequence on the entire structure including the metal wiring. And sequentially forming a second insulating film made of an oxide to form an interlayer insulating film having a double structure, forming a hard mask layer and a photosensitive film pattern on the interlayer insulating film, and using the photosensitive film pattern as a mask, a hard mask layer; Forming a contact hole by sequentially removing the second insulating film and the first insulating film, and performing a cleaning process after removing the photoresist film pattern to further etch the first insulating film to form a contact hole having a wider bottom portion than an upper portion thereof. Characterized in that it comprises a step.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 2(a) 내지 도 2(c)는 본 발명에 따른 반도체 소자의 콘택홀 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도이다.2 (a) to 2 (c) are cross-sectional views of devices sequentially shown to explain a method for forming contact holes in a semiconductor device according to the present invention.
도 2(a)를 참조하면, 소정의 구조가 형성된 반도체 기판(21) 상부에 금속 배선(21)을 형성한다. 금속 배선(22)을 포함한 전체 구조 상부에 제 1 절연막(23) 및 제 2 절연막(24)으로 구성된 이중 구조의 층간 절연막을 형성하고, 하드 마스크층 (25)을 형성한다. 하드 마스크층(25) 상부에 감광막(26)을 형성한 후 노광 및 현상 공정을 실시하여 패터닝한다. 제 1 절연막(24)은 저유전율의 탄소 화합물 또는 SiOC 계열의 화합물을 이용하여 1000∼2000Å의 두께로 형성한다. 제 2 절연막(25)은 BPSG, PSG, FSG, PE-TEOS, PE-SiH4, HDP USG, HDP PSG, APL등의 산화물을 이용하여 5000∼20000Å의 두께로 형성한다. 또한, 하드 마스크층(25)은 SiN, Si 리치 SiN, SiON, Si 리치 SiON을 이용하여 1000∼2000Å의 두께로 형성한다.Referring to FIG. 2A, the metal wiring 21 is formed on the semiconductor substrate 21 on which a predetermined structure is formed. A double layer interlayer insulating film composed of the first insulating film 23 and the second insulating film 24 is formed over the entire structure including the metal wiring 22, and the hard mask layer 25 is formed. After the photoresist layer 26 is formed on the hard mask layer 25, exposure and development processes are performed to pattern the photoresist layer 26. The first insulating film 24 is formed to a thickness of 1000 to 2000 GPa using a low dielectric constant carbon compound or a SiOC series compound. The second insulating film 25 is formed to a thickness of 5000 to 20,000 kPa using oxides such as BPSG, PSG, FSG, PE-TEOS, PE-SiH 4 , HDP USG, HDP PSG, and APL. The hard mask layer 25 is formed to a thickness of 1000 to 2000 GPa using SiN, Si rich SiN, SiON, and Si rich SiON.
도 2(b)를 참조하면, 패터닝된 감광막(26)을 마스크로 하드 마스크층(24), 제 2 절연막(24) 및 제 1 절연막(23)을 순차적으로 식각하여 금속 배선(22)을 노출시키는 콘택홀(27)을 형성한다. 하드 마스크층(25)은 CF4, O2및 Ar의 혼합 가스를 이용하여 식각한다. 제 2 절연막(24)은 CHF3와 O2의 혼합 가스 또는 C4F8, O2, CO 및Ar의 혼합 가스를 이용하여 식각한다. 또한, 제 1 절연막(23)은 저유전율 탄소 화합물로 형성하였을 경우 O2, N2, SO2및 Ar의 혼합 가스 또는 O2, N2및 Ar의 혼합 가스를 이용하여 식각하고, SiOC 계열의 화합물로 형성하였을 경우 CF4, CH2F2, CO 및 Ar의 혼합 가스를 이용하여 식각한다.Referring to FIG. 2B, the hard mask layer 24, the second insulating film 24, and the first insulating film 23 are sequentially etched using the patterned photoresist 26 as a mask to expose the metal wiring 22. Contact holes 27 are formed. The hard mask layer 25 is etched using a mixed gas of CF 4 , O 2, and Ar. The second insulating film 24 is etched using a mixed gas of CHF 3 and O 2 or a mixed gas of C 4 F 8 , O 2 , CO, and Ar. In addition, when the first insulating film 23 is formed of a low dielectric constant carbon compound, the first insulating film 23 is etched using a mixed gas of O 2 , N 2 , SO 2, and Ar, or a mixed gas of O 2 , N 2, and Ar. When formed with a compound is etched using a mixed gas of CF 4 , CH 2 F 2 , CO and Ar.
도 2(c)를 참조하면, 감광막(26)을 제거한 후 식각 공정에서 발생되는 잔류물을 제거하기 위한 세정 공정을 실시한다. NH4F와 EG의 혼합 용액을 이용하여 세정 공정을 실시하면 탄소 화합물로 이루어진 제 1 절연막(23)이 더 식각된다. 이에 의해 콘택홀의 바닥 부분이 상부보다 더 커지게 된다. 한편, 제 1 절연막(23)을 SiOC 계열의 화합물로 형성할 경우에는 산소 플라즈마를 이용한 감광막(26) 제거시 SiOC의 결합이 깨지게 된다. 이후, 100:1∼500:1의 BOE 용액을 이용하여 세정 공정을 실시하면 식각률의 차이에 의해 콘택홀의 바닥 부분이 상부보다 더 커지게 된다.Referring to FIG. 2C, after the photoresist layer 26 is removed, a cleaning process for removing residues generated in the etching process is performed. When the cleaning process is performed using a mixed solution of NH 4 F and EG, the first insulating film 23 made of the carbon compound is further etched. This makes the bottom portion of the contact hole larger than the top. On the other hand, when the first insulating film 23 is formed of a SiOC-based compound, the bonding of SiOC is broken when the photosensitive film 26 is removed using oxygen plasma. Subsequently, when the cleaning process is performed using a BOE solution of 100: 1 to 500: 1, the bottom portion of the contact hole is larger than the top due to the difference in the etching rate.
상술한 바와 같이 본 발명에 의하면 탄소 화합물 또는 SiOC 계열의 화합물로 이루어진 제 1 절연막 및 산화물 계열의 제 2 절연막의 이중 구조로 층간 절연막을 형성한 후 콘택홀을 형성하기 위한 식각 공정 및 세정 공정을 실시하면 상부보다 바닥 부분이 더 넓은 콘택홀이 형성된다. 이에 의해 접촉 저항을 안정적으로 확보할 수 있어 소자의 신뢰성을 향상시킬 수 있고, 동작 속도 및 수율을 향상시킬 수 있다.As described above, according to the present invention, an interlayer insulating film is formed of a double structure of a first insulating film and an oxide-based second insulating film made of a carbon compound or a SiOC series compound, followed by etching and cleaning processes for forming contact holes. The bottom has a wider contact hole than the top. As a result, the contact resistance can be stably secured, the reliability of the device can be improved, and the operation speed and the yield can be improved.
Claims (11)
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| KR1020000059515A KR20020028492A (en) | 2000-10-10 | 2000-10-10 | Method of forming a contact hole in a semiconductor device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100743631B1 (en) * | 2005-11-08 | 2007-07-27 | 주식회사 하이닉스반도체 | Method of manufacturing semiconductor device |
| KR100751669B1 (en) * | 2002-12-27 | 2007-08-23 | 주식회사 하이닉스반도체 | Method of forming a contact-hole in a semiconductor device |
| KR100802311B1 (en) * | 2006-12-26 | 2008-02-11 | 동부일렉트로닉스 주식회사 | Method for fabricating cmos image sensor |
-
2000
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100751669B1 (en) * | 2002-12-27 | 2007-08-23 | 주식회사 하이닉스반도체 | Method of forming a contact-hole in a semiconductor device |
| KR100743631B1 (en) * | 2005-11-08 | 2007-07-27 | 주식회사 하이닉스반도체 | Method of manufacturing semiconductor device |
| US7439177B2 (en) | 2005-11-08 | 2008-10-21 | Hynix Semiconductor Inc. | Method of manufacturing semiconductor device for improving contact hole filling characteristics while reducing parasitic capacitance of inter-metal dielectric |
| KR100802311B1 (en) * | 2006-12-26 | 2008-02-11 | 동부일렉트로닉스 주식회사 | Method for fabricating cmos image sensor |
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