KR20020028159A - Massively parallel interface for electronic circuit - Google Patents

Abstract

A wide range of permanent or permanent interconnects, such as interconnecting integrated circuits (ICs) to test and burn-in equipment, interconnecting modules in electronic devices, interconnecting computers and other peripherals in a network, or interconnecting other electronic circuits. Some embodiments of a massively parallel interface structure that can be used for temporary applications are disclosed. A preferred embodiment of the bulk parallel interface structure provides a bulk parallel integrated circuit test assembly. Mass parallel interface structures preferably use one or more substrates to establish a connection between one or more integrated circuits and one or more test modules on a semiconductor wafer. One or more layers on the intermediate substrate preferably comprise MEMS and / or thin film fabrication spring probes. The parallel interface assembly provides tight signal pad pitch and compliance and preferably enables parallel testing or burn-in of multiple ICs using commercial wafer probing equipment. In some preferred embodiments, the parallel interface assembly structure has a detachable standard electrical connector component, reducing assembly manufacturing cost and manufacturing time. These structures and assemblies enable high speed testing in the form of wafers.

Description

Mass parallel interface for electronic circuits {MASSIVELY PARALLEL INTERFACE FOR ELECTRONIC CIRCUIT}

Integrated circuits are typically tested in wafer form (wafer sort) before being packaged. During wafer sorting, integrated circuits are tested at one time, even though there may be hundreds or hundreds of thousands of identical integrated circuit boards placed on the wafer. The packaged integrated circuit is then tested again and burned-in as needed.

Parallel testing at the wafer level is limited in number due to the large number of interconnects and the limited size of electronic circuitry that can be placed close to the wafer under test, and so far in low pin count devices. It is limited.

Attempts have been made to burn in ICs in wafer form. However, wafer level burn-in has many problems, such as thermal expansion between the connector and the silicon wafer under test. Conventional structures, such as large area substrates with a large number of fanout traces electrically connected to pin or socket connectors, are typically implemented to manage the connection between the IC under test, test electronics, and power management electronics. .

The density of integrated circuits on semiconductor wafers continues to increase due to semiconductor device scale with more gates and memory bits per unit silicon area. In addition, the use of larger semiconductor wafers (with nominal direct 8 inches or 12 inches) is becoming common. However, semiconductor test costs are increasing in cost per unit silicon area. Thus, semiconductor testing is inadequately increasing with time, making it a greater cost in the total manufacturing cost of each integrated circuit device.

Moreover, chip scale packaging (CSP) and other small footprint packages are obsolete traditional package IC handlers for testing and burn-in.

In some conventional representative substrate integrated circuit (IC) test substrates, electrical contact between the test substrate and the integrated circuit wafer is typically provided by a tungsten needle probe. However, tungsten needle probe technology cannot meet the interconnect structure requirements of advanced semiconductors with higher pin counts, smaller pad pitches, and higher clock frequencies.

Although the new technology provides spring probes for other probing applications, there are inherent limitations such as limited pitch, limited pin count, variable flexibility levels, limited probe tip terrain, material limitations and high manufacturing costs. Have.

"Selectively Releasing Conductive Runner and Substrate Assembly Having Non-Planar Areas" (US Patent No. 5,166,774 (24 November 1992)) by K. Banerji, A. Suppelsa and W. Mullen III, describes a number of conductive materials attached to a substrate. Runners and substrate assemblies having a runner, wherein at least a portion of the conductive runner has a substrate for selectively releasing the conductive runner from the substrate when the non-planar region is subjected to a predetermined stress. To start.

"Selective Releasing Conductive Runner and Substrate Assembly" (US Patent No. 5,280,139 (18 January 1994)) by A. Suppelsa, W. Mullen III and G. Urbish, describes a number of conductive runners attached to a substrate. A runner and substrate assembly having a low adhesion to the substrate for selectively releasing the conductive runner from the substrate when at least a portion of the conductive runner is subjected to a predetermined stress.

D. Pedder, Bare Die Testing, U.S. Patent No. 5,786,701 (28 July 1998), "a testing station in which microbumps of conductive material are placed on the interconnect trace ends of a multilayer interconnect structure-these ends are connected to the pattern of contact pads on the die to be tested. The integrated circuit at the "bare die stage", which has a low profile, in the interconnect structure and other connections provided thereon, to facilitate the testing of the die prior to separation from the wafer using microbumps, distributed in a pattern accordingly. A testing device for testing (IC) is disclosed.

"Surface Mount Electrical Connector" (US Patent No. 5,152,695 (06 October 1992)) by D. Grabbe, I. Korsunsky and R. Ringer states that "cantilevered spring arm with the connector extending obliquely to the outside. Disclosed is a connector having a platform with a spring arm having a protruding contact surface, and in one embodiment, wherein the terrain of the arm provides a compound wife.

"Partly Replaceable Device for Testing a Multi-Contact Integrated Circuit Chip Package" (US Patent No. 5,847,572 (08 December 1998)) by H. Iwasaki, H. Matsunaga and T. Ohkubo, describes a "side edge portions. In a test device for testing an integrated circuit (IC) chip each having a set of lead pins, the test device comprises a contact unit each having a socket base, a contact support member and a socket contact number, and An anisotropic conductive sheet assembly each having an elastic insulating sheet and a conductive member, wherein the anisotropic conductive sheet assembly is aligned to contact each of the socket contact members of the contact unit to hold each conductive member, the test element being a socket contact In order to establish electrical communication between the member and the conductive member of the anisotropic conductive sheet assembly, the socket contact member is connected with the anisotropic sheet assembly. Having a contact container detachably mounted on the socket base to be in contact, each of the contact units can be replaced by a new contact unit if the socket contact member becomes partially fatigued, to facilitate maintenance of the test element, Furthermore, the lead pin of the IC chip is electrically connected to a test circuit board having a shortest path formed by the socket contact member and a part of the conductive member of the anisotropic conductive sheet assembly.

"Method of Mounting a Substrate Structure to a Circuit Board" by W. Berg (US Patent No. 4,758,927 (19 July 1988)) describes a substrate having a pad of conductive material exposed to one main surface of the substrate, and a contact pad. The structure is mounted to a substrate having alignment features in a predetermined position relative to the contact pad of the circuit board, the substrate structure being electrically connected to the contact pad of the substrate structure and extending from the substrate structure in a cantilever manner. The alignment element has a plate portion and is also distributed with respect to the plate portion and has an alignment feature that can engage the alignment feature of the circuit board, and when engaged, aligns for movement parallel to the entire plane of the circuit board. Holding the device, the circuit board is attached to the plate portion of the alignment element so that the leads are placed in a position selected for the alignment characteristics of the circuit board. In the position of the alignment element, the leads of the circuit board rest on the contact pads of the circuit board, and the clamp member maintains the electrical conductor contact with the contact pads of the circuit board.

"Controlled Adhesion Conductor" (US Patent No. 5,121,298 (09 June 1992)) by D. Sarma, P. Palanisamy, J. Hearn, and D. Schwaz describes a composition useful for printing a controllable adhesive conductive pattern on a printed substrate. Silver comprises finely divided copper powder, screening agent and binder, which provides controllable adhesion of the copper layer formed after the binder is sintered to the substrate so that the layer responds to thermal stress It is disclosed that a composition can serve to enhance the good adhesion between the copper particles in order to provide a good mechanical strength to the copper layer so that the binder can lift off, and incidentally, the binder can withstand the lift off without breaking. "

"Thin-FIlm Electrothermal Device" (US Pat. No. 4,423,401 (27 December 1983)) by R. Mueller uses "thin film multilayer technology to have low resistance metal-to-metal contact and distinct on-off characteristics. Building micro-small electromechanical switches, electrothermally activated switches are fabricated on conventional hybrid circuit boards using processes compatible with those used to make thin film circuits, and in a preferred form, The switch includes a cantilever drive member having an elastically bendable strip of rigid insulating material (ie silicon nitride) to which a metal (ie nickel) heating element is attached, the free end of the cantilever member being applied to the heating member. And the metal contacts to be engaged with the cantilever member are mounted.

"Multi-Layer Ceramic Package" by S. lbrahim and J. Elsner (US Patent No. 4,320,438 (16 March 1982)), "In a multi-layer package, has a thin conductive pattern of a plurality of ceramic layers, There is an internal cavity of a package to which a plurality of chips interconnected to form an array is adhered, and the chip or chip array is connected to the metallized conductive pattern at variable thin film layer levels through short wire bonds, each thin film layer level With this particular conductive pattern, the conductive pattern on each thin film layer is interconnected by tunneling through an opening filled with a metallization material or by edged metallization, so that the conductive pattern is ultimately mounted to the metallized substrate at the bottom of the ceramic package. Connected to a number of pads on the surface, although high compositional densities are achieved, the connecting leads are alternately having entirely different package levels It is possible to obtain 10 mil space and 10 mil size of wire bond lands because they are "staggered" or connected in. In the end, there is a greater compositional density, but between the wire bonds Interference is present, and such interference elements disclose a multilayer ceramic package, which is a limitation previously to achieve high component density networks in multilayer ceramic packages.

"Probe Assembly for Testing Integrated Circuits" by F. McQuade and J. Lander (US Patent No. 5,416,429 (16 May 1995) describes a probe card of insulating material having a central opening, a smaller opening attached to the probe card. Four probe probes each having a rectangular frame with a flexible thin film member having a conductive ground plane sheet, an attached dielectric film attached to a ground plane, and a spring alloy copper In a probe assembly for testing an integrated circuit comprising a probe wing trace of alloy copper, each probe wing has a cantilevered leaf spring extending to a central opening, the probe wing Terminate at a set of aligned individual probe fingers provided by each end of the trace. It has tips arranged along a straight line and spaced apart to correspond to the spacing of each contact pad along the edge of the IC being tested Four spring clamps are each adjustable for one of the leaf spring parts Has a cantilever portion in contact with the leaf spring portion of each probe wing to provide a restriction, four separate spring clamp adjustment means for individually adjusting the pressure limit imposed by each of the spring clamps on each probe wing. The individual spring clamp adjustment means have spring biased flatforms attached to the frame member by three screws and spring washers, respectively, so that the spring clamps have a probe finger on each probe wing. Moved in any desired direction to align the tip position Is facing. "Discloses that.

D. Pedder, "Structure for Testing Bare Integrated Circuit Devices" (Patent Application No. EP 0 731 369 A2 (filed 14 February 1996)) and U.S. Patent No. 5,764,070 (09 June 1998) said, "In order to achieve a predetermined connection, a multi-layer printed-substrate probe arm is mounted with a tip of an MCM-D type substrate having a row of microbumps underneath thereof. A bare probe IC or a test probe structure for making a connection to a wafer to be tested, wherein the probe arm is supported at a shallow angle on the surface of the device or wafer, and the MCM-D type substrate is used to interface with the device under test. And four such probe arms can be provided, one on each side of the device under test. "

"Method of Mounting Resilient Contact Structure to Semiconductor Devices" (USPatent No. 5,829,128 (03 November 1998)) by B. Eldridge, G. Grube, I. Khandros and G. Mathieu, "Method of Making Temporary Connections Between Electronic Components" (US Patent No. 5,832,601 (10 November 1998)), "Method of Making Contact Tip Structure" (US Patent No. 5,864,946 (02 February 1999)), "Mounting Spring Elements on Semiconductor Devices" (US Pat. Np. 5,884,398 ( 23 March 1999)), "Method of Buring-in Semiconductor Devices" (US Patent No. 5,878,486 (09 March 1999)), and "Method of Exercising Semiconductor Devices" (US Pattent No. 5,897,326 (28 April 1999)). Discloses that an elastic contact structure is attached that is directly mounted to a bond pad on a semiconductor die prior to a die partitioned from the semiconductor wafer, which is a circuit in which a plurality of terminals are disposed on a surface thereof. On a semiconductor die having a substrate or the like To allow the semiconductor die to be implemented (ie, tested and / or burned-in.) The semiconductor die can then be partitioned from the semiconductor wafer, whereby the semiconductor die and the (wired substrate, semiconductor package, etc.) The same elastic contact structure is used to effect the interconnection between the different electronic components Burn-in at a temperature of at least 150 ° using the all-metallic composite interconnect member of the present invention as an elastic contact structure. (burn-in) may be performed and may be completed in less than 60 minutes ". Although the contact tip structure disclosed by B. Eldridge et al. Can provide an elastic contact structure, each structure is individually mounted to bond pads on a semiconductor die, requiring complex and expensive manufacturing. In addition, contact tip structures are made from wires, often limiting the resulting topography for the tip of the contact. Moreover, such contact tip structures may not meet the needs of small pitch applications (ie, typically about 50 μm for peripheral probe cards or about 75 μm for area arrays). ”

"Sockets for Electronic Components and Method of Connecting to Electroic Components, (US Patent N. 5,772,451 (30 June 1998)) by T. Dozier II, B Eldridge, G. Grube, I. Khandros and G. Mathieu Surface-mount, solder-down sockets enable electronic components, such as semiconductor packages, to be releasedably mounted on a circuit board.Elastic contact structures extend from the top surface of the support substrate. And a solder-ball (or other suitable) contact structure is disposed on the bottom surface of the support substrate, and a composite interconnect element is used as the elastic contact structure disposed over the support substrate. The selected ones of the elastic contact structures on top of the substrate are then connected to the corresponding ones of the contact structures on the bottom surface of the supporting substrate. In this embodiment, pressure contact is made between the elastic contact structure and the extending connection point of the semiconductor package having a contact force that is generally normal to the top surface of the supporting substrate In an embodiment intended to receive a BGA-type semiconductor package, the elastic contact structure and the support Pressure contact is made between the elongated connection points of the semiconductor package having a contact force that is generally parallel to the top surface of the substrate.

Other techniques disclose probe tips on springs made with batch mode processors such as thin film or microelectromechanical system (MEMS) processes.

"Photolithographically Patterned Spring Contact" by D. Smith and S. Alimonda (US Patent No. 5,613,861 (25 March 1997), US Patent No. 5,848,685 (15 December 1998) and International Patent Application No. PCT / US96 / 08018 (30 May 1996) discloses a lithographic patterned spring contact formed on a substrate and electrically connecting contact pads on two devices. The spring contact also compensates for thermal and mechanical changes and other environmental factors. Stress of spring contacts The gradient causes the free portion of the spring to bend up and away from the substrate An anchor portion is secured to the substrate and electrically connected to a first contact pad on the substrate The spring contact is made of an elastic material, The free end is elastically in contact with the second contact pad, causing the two contact pads to contact each other. ” While the disclosed photolithographic pattern springs can meet many IC probing needs, the small vertical compliance that handles the planarity compliance required for reliable operation of many current IC prober systems with small springs ( The vertical compliance of many probing systems is typically about 0.004 "-0.0010", which often requires the use of a tungsten needle probe.

The round trip transit time between the device under test and the conventional test device is often longer than the stimulus for response times of high speed electronic circuits. It would be desirable to provide a test interface system that reduces this transition time by placing high speed test electronics close to the device under test while meeting space and cost constraints. Furthermore, it would be desirable to provide a test interface system that minimizes the cost, complexity, tooling, and rotation time required to modify test structures for testing different devices. The development of such a system will constitute a major technological advance.

Probes with many, hundreds, or even hundreds of thousands of pads for one or more devices on a semiconductor wafer, such as for large numbers of parallel testing and / or burn-in applications, while providing a single force across all probes across the entire wafer It would be desirable to provide a test interface system that provides contact, wherein the pads can be placed close to each other with a minimum spacing of less than 1 mil. It also configures and manages the interconnect between the device under test and the tester electronics while maintaining signal integrity and power and ground stability, ensuring that two or more adjacent pads are contacted by a single test probe tip. It would be desirable to provide such a test interface. Furthermore, it would be desirable to provide such a test structure, which preferably provides planarity compliance with the device under test. The development of such a system would constitute additional technical advantages.

In addition, such a test provides thermal isolation between the test electronics and the device under test, while providing continuous contact with many, hundreds, or even hundreds of thousands of pads to one or more devices on a semiconductor wafer, preferably over a wide temperature range. It would be desirable to provide a system. It would also be desirable to provide a system for separate thermal control of the test system and the device under test.

It is also desirable to provide a test interface system that can be used to quickly detect ground shorts on any die and isolate power from the die with the detected power to ground short before the test electronics are damaged. Would be preferred. It also ensures that the magnetic inductance and magnetic capacitance of each signal line is below a value that will adversely affect the test signal integrity, and that mutual inductance or mutual capacitance between signal line pairs and between signal line pairs and power or ground lines In order to ensure that the value is adversely affected, it would be desirable to provide a test interface structure that can detect that many, hundreds or even hundreds of thousands of pads are made reliably and that each of the contacts is within the contact resistance specification. It would also be desirable to provide a test interface structure that provides stimulus and response detection and analysis to many, hundreds or even hundreds of thousands of die under test and preferably provides diagnostic tests on failed die in parallel to subsequent testing of all other dies. Would be desirable.

Moreover, it would be desirable to provide a large array interface system that can reliably and repeatedly make contact with many, hundreds, or even hundreds of thousands of pads without the need to periodically stop, inspect, and / or clean probe interface structures.

It is also desirable to provide a system for massively parallel interconnects between electrical components, such as between computer systems using spring probes in the interconnect structure to provide high pin count, small pitch, low cost manufacturing and customizable spring tips. Would be preferred.

Summary of the Invention

Of a bulk parallel interface integrated circuit test assembly using one or more substrates to establish a connection between one or more integrated circuits on a semiconductor wafer and one or more test modules electrically connected to the integrated circuits on the semiconductor wafer through the substrate. Several embodiments are disclosed. One or more layers on the intermediate substrate preferably comprise a MEMS and / or thin film fabrication spring probe. Bulk parallel interface assembly provides tight pad patches and preferably enables parallel testing or burn-in of multiple ICs. In some preferred embodiments, bulk parallel interface assembly structure reduces assembly manufacturing cost and manufacturing time. It includes a separate standard electrical connector component. These massively parallel interface structures and assemblies allow for high speed testing in the form of wafers and allow test electronics to be placed close to the wafer. Preferred embodiments of the bulk parallel interface assembly provide thermal expansion consistent with the wafer under test and provide a thermal path for system electronics. An optional bulk parallel interface architecture provides a bulk parallel connection interface that can be used in a wide variety of circuits, such as interconnecting computers in a network and interconnecting other electronic circuits.

Brief description of the drawings

1 is a plan view of a linear array of photolithographically patterned springs prior to release from a substrate,

2 is a plan view of a linear array of photolithographically patterned springs after release from the substrate,

3 is a side view of a first short length photolithographically patterned spring having a first effective radius and height after the short length spring is released from the substrate, FIG.

4 is a side view of a second long length photolithographically patterned spring having a second large effective radius and height after the long length spring is released from the substrate;

5 is a perspective view of an opposing photolithographic spring having an interleaved spring tip pattern before the spring is released from the substrate;

6 is a perspective view of an opposing photolithographic spring having an interleaved spring tip pattern after the spring is released from the substrate,

FIG. 7 illustrates a first opposing pair of interpolated multiple-point photolithographic spring probes in contact with one trace on an integrated circuit device, and interpolation in contact with one pad on the integrated circuit device. Top view of a second opposing pair of multiple-point photolithographic spring probes,

8 is a top view of an opposing single-point photolithographic spring probe, before the spring is released from the substrate,

9 is a top view of a parallel and opposing single point photolithographic spring probe after the spring is released from the substrate in contact with one pad on the integrated circuit device,

10 is a front view of a shoulder-point photolithographic spring probe,

11 is a partial cross-sectional view of a shoulder-point photolithographic spring probe in contact with a trace on an integrated circuit element;

12 is a perspective view of multiple shoulder-point photolithographic spring probes,

13 is a partial cross-sectional view of a multi-layer spring probe substrate providing components integrated with control impedances;

14 is a partial plan view of a substrate in which a plurality of trace distribution regions are defined on a probe face of the substrate, between a plurality of spring probes and a plurality of via contacts;

FIG. 15 is a partial cutaway view of a mass parallel test assembly having test electronics positioned proximate the wafer under test. FIG.

16 is a partial perspective view of a mass parallel interconnect assembly,

FIG. 17 is a partial enlargement of a mass parallel test assembly with an intermediate system substrate showing the staged pitches and distribution across the substrate, the system substrate, and a flex circuit with a pad matrix. Cross-section,

18 is an enlarged plan view of a wafer, a circular substrate, and a rectangular system substrate;

19 is an enlarged plan view of a wafer, a plurality of rectangular substrates, and a rectangular system substrate;

20 is a partial cross-sectional view of one embodiment of a flexible circuit substrate,

FIG. 21 is a partial cross-sectional view of an alternative embodiment of a flexible circuit having a flex circuit membrane structure; FIG.

22 is a partial perspective view of a flexible membrane circuit structure in which the flexible region is defined as an extension of the electronic test card structure;

FIG. 23 is a partial perspective view of an alternative flexible circuit structure in which the flexible circuit is attached to the electronic test card structure; FIG.

FIG. 24 illustrates a preferred flex circuit of the test electronics module in which the flex circuit is wound around the power and ground buss structure and preferably includes a thermal path across the flex circuit between the power module and the buss bar. Partial cross-sectional view of one embodiment of a region,

25 is a partial cross-sectional view of an alternative embodiment of the flex circuit region of the test electronic module, in which a plurality of power modules mounted on an inner surface of the flex circuit are disposed in thermal contact with a plurality of bus bars;

FIG. 26 is a partial cross-sectional view of a second alternative embodiment of the flex circuit region of the test electronic module, in which the power module is electrically connected to the outer surface of the flex circuit and disposed in thermal contact with the bus bar; FIG.

FIG. 27 illustrates a test electronics module in which an integrated module base provides a pad metric different than a first flat area and the power module is disposed in thermal contact with the bus bar in electrical connection to the pad matrix and the one or more bus bars. Perspective view of an alternative embodiment of,

FIG. 28 is a partial cut assembly view of an alternate mass parallel test assembly with an intermediate system substrate with the flexible spring probe placed on the bottom of the system substrate.

FIG. 29 is a partial cutaway assembly view of another alternate mass parallel test assembly with an intermediate system substrate, wherein the interposer structure provides electrical connection between the substrate and the system substrate; FIG.

30 is a partially cut away assembly view of a basic mass parallel test assembly in which a substrate with a spring probe is directly connected to a test electronic module;

31 is a partially enlarged cross sectional view of a basic mass parallel test assembly showing pitch and distribution staged across a flex circuit having a substrate and pad matrix;

FIG. 32 is a partial cut assembly view of a bulk parallel burn-in test assembly with a burn-in test module directly connected to the system board and provided with separate temperature control systems for the wafer under test and the test electronic module. FIG.

33 is a first enlarged cross sectional view illustrating a mass parallel test assembly and alignment hardware and procedure;

34 is a second enlarged cross-sectional view illustrating a mass parallel test assembly and alignment hardware and procedure;

35 is a partial schematic block diagram of a test circuit for a mass parallel test system;

36 is a partial cutaway view of a mass parallel interface assembly to which a plurality of interface modules are connected, through a plurality of probe spring interposers and a system interconnection board structure;

FIG. 37 is a partially cut away assembly view of an alternate mass parallel interface assembly having a plurality of interface modules connected thereto, through a system board and system interconnect board structure; FIG.

38 is a systematic block diagram of a connection between a plurality of computer systems using a mass parallel interface assembly, and

39 is a schematic block diagram of a connection between a plurality of electronic circuits using a mass parallel interface assembly.

The present invention relates to the field of high-band electronic systems, as well as integrated circuit (IC) testing and burn-in structure processes. More particularly, the present invention has photolithography-patterned spring contacts and photolithographically patterned spring contacts for testing or burn-in of integrated circuits, electronic systems or An improved system interconnect assembly is provided for interconnecting a large number of signals between subsystems.

1 is a plan view 10 of a linear array 12 of photolithographically patterned springs 14a-14n prior to release from substrate 16. Conductive springs 14a-14n are typically deposited metal 17 (ie, in FIG. 13), such as photolithographic patterning, followed by low and high energy plasma and sputter deposition processes, as is well known in the semiconductor industry. Formed on the substrate layer 16 by successive layers (such as layers 17a, 17b). The continuous layer 17 has different inherent stress levels. The release region 18 of the substrate 16 is processed by undercut etching, so that portions of the spring contacts 14a-14n overlying the release region 18 are the result of inherent stresses between the deposited metallic layers. , Is released from the substrate 16 and extends (ie, bent) away from the substrate 16. The fixed regions 15 (FIGS. 3, 4) of the deposited metal traces remain fixed to the substrate 16, typically from spring contacts 14a-14n (ie redistribute or fan out). Used for routing (such as for redistribution or fan-out). 2 is a perspective view 22 of a linear array 12 of photolithographically patterned springs 14a-14n after release from the substrate 16. The spring contacts 14a-14n may now be formed into a high density array with a precise pitch 20 of about 0.001 inches.

3 shows the first effective spring angle 30a (which is in the capital) after the patterned spring 14 has been released from the planar anchor region 15 and released from the release region 18a of the substrate 16. Side view 26a of first photolithographically patterned spring 14 having a short length 28a formed to define a full circle), spring radius 31a, and spring height 32a to be. 4 shows a second having a short length 28b formed to define a second large effective spring angle 30b after the patterned spring 14 is released from the release area 18b of the substrate 16. Side view 26b of photolithographically patterned spring 14. The effective topography of the formed spring tip 14 is extremely customizable based on the intended application. Of course, spring tips are typically flexible so that they can be used in many applications.

The patterned spring probe 14 is extremely small relative to the spring pitch 20 used to bring the plurality of spring probes 14 into contact with power or ground pads on the integrated circuit elements 44 (FIGS. 18, 19). Can be spring to improve current carrying capacity. Of course, for a massively parallel interconnect assembly 78 (78a in FIG. 15) with an array 12 (FIG. 1) of spring probes 14, the device under test (DUT) 44 under test. Multiple spring probes 14 can be used to probe the I / O pads 47 on the IC substrate 48 (FIG. 9) as shown above (FIGS. 18, 19). Allow all spring probe contacts 14 to prove for continuity after engaging the spring contacts 14 to the wafer 104 under test (FIG. 15), prior to starting the testing procedure, prior to the mass parallel interface assembly 78 and wafers. Ensure complete electrical contact between the elements 44 (FIG. 15) on 104.

Improved Structure for Small Springs : FIG. 5 is a first perspective view of opposing photolithographic springs 34a, 34b having an interleaved spring tip pattern before the spring is released from the substrate. 6 is a perspective view of opposing interpolated photolithographic springs 34a and 34b after the spring is released from the substrate.

Interpolated photolithographic springs 34a and 34b each have a plurality of spring contact points 24. When spring contacts are used to power the integrated circuit element 44 or to the ground trace 46 or pad 47, the largest electrical resistance occurs at the point of contact. Thus, interpolated spring contact 34 having a plurality of contact points 24 inherently lowers the resistance between spring contact 34 and trace 46 or pad 47. As noted above, many applications are found in many applications, such as for high quality electrical connections or bulk parallel interface assemblies 78 (FIG. 15) for integrated circuit devices 44, such as probes of integrated circuit devices 44 during testing. An interpolated spring probe 34 of can be used.

FIG. 7 is a top view 42 of opposing interpolated photolithographic spring pairs 34a and 34b in contact with the same trace 46 or pad 46 on the integrated circuit device (DUT) under test. Interpolated spring contact pairs 34a and 34b cause all of the springs 34a and 34b having a plurality of contact points 24 to contact the same trace 46 or pad 47, respectively. As shown in FIG. 5, when a zigzag pattern is created between two springs 34a and 34b on the substrate 16, a number of tips 24 are established on each spring 34a and 34b. Before the interpolated spring probes 34a and 34b are released from the substrate 16, the interpolated points 24 are placed in the overlapping interpolation area 36. When interpolated spring probes 34a and 34b are released from substrate 16, interpolated spring points 24 remain in close proximity to each other, within the contact area defined between springs 34a and 34b. The interpolated spring pairs 34a and 34b can then be arranged such that both interpolated spring probes 34a and 34b contact the same trace 46 as the device 44 under test to provide increased reliability. have. Of course, because each interpolated spring 34a, 34b includes a plurality of spring points 24, the contact with the trace 44 is increased while overheating over the plurality of contact points 24. Or the potential of current arcing is minimized.

8 is a top view of parallel and opposing single-point photolithographic springs 14 before the springs 14 are released from the substrate 16. As described above for interpolated springs 34a and 34b, parallel springs 14 may also be disposed such that spring tips 24 of multiple springs contact a single trace 46 on element 44. have. Of course, the opposing spring probes 14 overlap one another on the substrate 16 such that, upon release from the substrate 16 over the release region 18, the spring tips 24 lie close to each other. 9 is a top view of parallel and opposing single point photolithographic springs 14 after the spring 14 is released from the substrate 16, wherein the parallel and opposing single point photographic springs 14 are integrated circuit elements. Contact with a single pad 47 on 44.

FIG. 10 is a front view of a shoulder-point photolithographic spring probe spring 50 with a point 52 extending from the shoulder 54. FIG. 11 is a partial cross-sectional view of a shoulder-point photolithographic spring 50 in contact with trace 46 on an integrated circuit device. 12 is a perspective view of multiple shoulder-point photolithographic springs 50. The single point spring probe 14 is typically conductive trace 46 on the integrated circuit device 22 by passing through an existing oxide layer on the trace 46 or pad 47, typically by one sharp probe tip 24. ) Provides good physical contact. However, in the case of an integrated circuit device having a semiconductor wafer 104 or a relatively flexible trace 46 or pad 47, one long probe tip 24, as in the IC substrate 48 or other circuitry, It can penetrate beyond the depth of trace 46.

Thus, the shoulder-point photolithographic spring 50 includes the shoulder 54 as well as one or more extending points 52, which points 52 may be provided to provide good electrical contact to the traces 46. While providing transmission, shoulder 54 prevents spring 50 from penetrating too deep into element 44 or wafer 104. Since the topography of the spring probe 50 is extremely controllable by the photolithographic screening and etching process, the detailed topography of the shoulder-point photolithographic spring 50 is easily achieved.

13 is a partial cross-sectional view 56 of an ultra high frequency spring probe substrate 16. One or more conductive reference planes 58a, 58b, 58c, 58d and vias, for embodiments where the spring probe 61 and associated electrical conductors 60, 68, 64 over or through the substrate 16 are required for impedance matching. (vias) 65a, 65b, 65c may be preferably added in or on the substrate 16. Substrate 6 may also include alternate ground reference planes 58a, 58b, 58c, 58d connected to reference planes 58a, 58b, 58c, 58d to effectively provide a shouldered coaxial transmission line environment 63. Can be. Of course, the impedance control surfaces 58a, 58b, 58c, 58d are not limited to the flat surface shown in FIG.

The insulating layer 66 is fixed to the probe spring 61 above but not surrounding the tip 24 (FIG. 2), as well as the trace 60 connected to the via 68 at the spring probe 61. It may be deposited over a portion of the probe spring 61, such as on an area. Conductive layer 58d may be deposited on top of insulating layer 66 to provide a coaxial controlled low impedance connection. Alternative conductive layer 58 and dielectric material 66 may be integrated into substrate 16, as is preferred for embodiments requiring a decoupling capacitor in proximity to probe spring 61. In the case of the substrate 16, which is a conductive material such as silicon, a thin oxide side 57 is preferably deposited between the substrate 16 and the conductive reference plane 58c, so that the high pressure between the spring probe 61 and the ground planes 58a, 58b is increased. Capacitance structure 59 may be formed. Of course, one or more assembled components 69, such as passive components 69 (i.e. typically capacitors, resistors and / or inductors) or active component elements 69, are placed on the surfaces 62a and 62 of the substrate. It can be integrated into.

The fixture 15 of the spring probe 61 typically extends a relatively short distance across the substrate 16. The trace 60 lying on the surface of the substrate 16 is electrically connected to the fixture 15 of the spring probe 61, and electrically connects the probe spring 61 to the via 68. The trace may be composed of a material different from the spring probe 61 and is preferably composed of a material having high electrical conductivity (ie, copper or gold).

14 shows a plurality of distribution fanout traces 60 on the probe face 62a of the substrate 16 between the plurality of spring probes 61 and the plurality of via contacts 70. Partial plan view 72 of the substrate 16 is defined. As noted above, the spring probe 61, which is preferably a photolithographically formed spring 61, can now be formed with a pitch of about 0.001 inches. Trace 60 is routed on probe face 62a to connect to via contact region 70, which is preferably arranged in a matrix over the surface of substrate 16. In the substrate 16 shown in FIG. 14, the via contact region 70 is disposed at the probe face first distribution pitch 74a and the probe face second distribution pitch 74b.

As the size and design of the integrated circuit device 44 become smaller and more complex, the fine pitch 20 provided by the small spring probe tip 61 becomes increasingly important (Fig. 2). And as both of the required test assemblies are downsized, the difference in flatness between the one or more integrated circuits 44 placed on the wafer 104 and the substrate 16 including the large number of spring probes 61 becomes important.

As described in FIG. 14, the probe surface of the substrate 16, such as to prevent the substrate 16 from damaging the wafer 104 under test or to set the spring probe tip 24 to operate at an optimal contact angle. A lower standoff 75 is preferably provided on 62a. The lower stand of 75 is preferably made of a relatively soft material, such as polyimide, to avoid damage to the semiconductor wafer 104 under test. In addition, to avoid damaging the active elements 44 of the semiconductor wafer 104, when the mass parallel interface assembly 78 is aligned with the elements 44 on the semiconductor wafer 104, the standoff 75, A stand of 75 is preferably arranged such that it is aligned with a saw street 136 (FIGS. 18, 19) on a semiconductor wafer 104 where no active device 44 or test structure is present. . In addition, the height of the lower standoff 75 is preferably selected to limit the maximum compression of the spring probes 61a-61n to prevent damage to the spring probes 61a-61n.

The substrate 16 also typically has one or more alignment marks 77 (FIG. 14) on the probe surface 62a such that the substrate 16 is precisely aligned with the wafer 104 to be tested. ).

Bulk parallel interface assembly for testing and burn-in. FIG. 15 is a partially cut assembly view of a mass parallel test assembly 78a with an intermediate system substrate 72. 16 is a partial perspective view 110 of a mass parallel interface assembly 78a. FIG. 17 illustrates an intermediate system substrate 82, system substrate 82, and electronic connectors 119a-119n pad matrix 88 showing the staged pitches and distribution across the substrate 16. 15 is a partially enlarged cross-sectional view of a mass parallel test assembly 78a having a flex circuit 90 with FIG. As shown in FIGS. 15 and 17, the interface assembly 78a typically has a semiconductor wafer 104 having one or more collector circuits 44 separated by a sow street 136 (FIGS. 18, 19). Is placed in connection with.

The mass parallel interface assembly 78a can include hundreds of thousands of spring probe tips 61a-61n while providing adequate mechanical support for the interface assembly 78a to effectively operate in a typical integrated circuit test environment. Provide electrical interconnection for The interface assembly 78a is readily used for applications that require extremely high pin counts for tight pitches or high frequencies. Of course, interface assembly 78a provides electrical contact for all traces (FIG. 7), and input and output pads 47 (FIG. 7) for one or more integrated circuits 44 under test on wafer 104. 9 is provided.

As shown in FIG. 15, a plurality of electrically conductive spring probe tips 61a-61n rest on the lower probe surface 62a of the substrate 16, and the one or more test devices 44 on the wafer 104. It is aligned with the fine spring pitch 20 (FIGS. 1, 17) needed to interconnect to a particular pad 47 (FIG. 17) on the top. The spring probe tips 61a-61n can have a variety of tip topography, such as one point spring 14, interpolated spring 34, or shoulder point spring 50, with low manufacturing costs, well controlled uniformity, To achieve extremely fine pad pitch 20 and large pin counts, they are typically fabricated on substrate 16 using thin film or MEMS processing methods. In some embodiments, flexible connections 64a-64n are constructed in accordance with photolithographic springs, such as those disclosed in US Pat. No. 5,848,685 or US Pat. No. 5,613,861, described above or incorporated herein by reference. Spring probes 61a-61n on the probe surface 62a of the substrate 16 engage with pads 47 on each die 44 of the wafer 104.

The fixed trace portions 15, 60 (FIGS. 3, 14) are then aligned with the substrate distribution pitches 74a, 74b so that the vias 68a-68n are distributed relatively uniformly across the substrate 916. Routed to the plurality of metallized vias 68a-68n. Electrically conductive traces 60 are preferably fabricated on one or both sides of the substrate 16 to provide dispersion of the conductive connections 64a-64n across the connector face 62b of the substrate 16.

Probe tips 61a-61n are electrically connected to electrically conductive connections 64a-64n through metallized vias 68a-68n in substrate 916. Each of the plurality of electrical connections 64a-64n is electrically connected to the plurality of electrically conductive pads 84a-84n of the bottom surface 139a on the system substrate 82. Preferred metallized via electrical connections 68a-68n (such as manufactured by Micro Substrate Corporation, Tempe, AZ) within substrate 16 first create holes in substrate 16 and then laser or other drilling. Using the drilling method, they are typically produced by standard PTH methods or extrusion methods. The hole is then filled or plated with a conductive material such as by plating or extrusion. After the conductive vias 68a-68n are formed, they are typically polished back to provide a flat, smooth surface. The capacitor is preferably mounted or installed in the substrate 16 (FIG. 13) to provide close proximity de-coupling to the IC wafer under test.

The substrate 16 preferably consists of silicon, glass, ceramic, ceramic glass or other suitable substrate material, and preferably has a coefficient of thermal expansion that matches the coefficient of thermal expansion TCE of the wafer 104. In some preferred embodiments of the parallel interface assembly 78, the substrate 16 is relatively thin such that the substrate 16, the spring probes 61a-61n, and the preferred flexible connections 64a-64n are the wafer 104 under test. Provide increased planarity compliance.

In alternative embodiments of the substrate 16, the starting substrate 16 (ie, such as the silicon substrate 16) is etched by a plasma etching process or a wet anisotropic etch processor, so that the substrate (such as is practiced in the MEMS industry). 16, through holes (ie, vias) are created. The substrate 16 is thinned by atmospheric plasma ion etching prior to the generation of the through holes, so that fine pitch holes can be defined in the desired silicon wafer 16 to produce the flexible substrate 16. The flexible substrate 16 is one on the wafer 104 as a pressure differential (such as described with reference to FIG. 32) is provided between the probe face 62a of the substrate 16 and the connector substrate 62b. The surface of the device 44 under test is compliant. As described, the holes are filled or plated with a conductive material by plating or extrusion. After the conductive vias 68a-68n are formed, they are typically polished back to provide a flat and flexible surface. The capacitor is preferably mounted or installed in the substrate 16 (FIG. 13) to provide close de-coupling to the IC wafer 104 under test.

Electrically conductive connections 64a-64n are located on upper connector face 62b of substrate 16 and are connected to vias 68a-68n. Electrically conductive connections 64a-64n can typically be aligned with substrate distribution pitches 74a, 74b, and preferably connection pitch 122 that can be redistributed on upper connector face 62b of substrate 16. (Fig. 17). In some preferred embodiments of the substrate 16, the electrically conductive connections 64a-64n are preferably distributed relatively uniformly over the substrate 16.

The electrically conductive connections 64a-64n are preferably arranged in an area array having an array pitch 122 such as 0.5 mm, 1.00 mm or 1.27 mm, so that the plated through holes (PTH) 86a-on the system substrate 82 are aligned. 86n) provides a reasonable density to match (typically aligned with system substrate pitch 126) and does not rely on improved system substrate 82 including blind conductive vias 86a-86n. This allows for the dispersion of signals on multiple layers within the system substrate 82.

Electrically conductive connections 64a-64n in contact with conductive pates 84a-84n on the underside of system substrate 82 provide electrical connection between substrate 16 and system substrate 82. Electrically conductive connections 64a-64n also provide lateral compliance between the substrate 16 and the system substrate 82 with different coefficients of thermal expansion (ie, for low TCE substrate 916 and relatively high TCE system substrate 82). .

In an alternative embodiment of the mass parallel interface system 78b (FIG. 27), the spring probes 64a-64n on the side of the board 16 connector 62b are attached to the pad matrix 88 on the test electronic modules 92a-92k. To interlock.

The electrically conductive connecting portions 64a-64n are preferably uniformly distributed across the upper connector face 62b of the substrate 16. Similarly, the conductive pads 84a-84n preferably have the system substrate 82 evenly distributed across the bottom surface 139a. The distributed layout of the electrically conductive connections 64a-64n and the conductive pads 84a-84n provides a pad pitch 124 (ie, about 0.020-0.050 inches) associated with the large connector pitch 122, thereby providing a relatively large size. Conductive pads 84a-84n and / or electrically conductive connections 64a-64n can be used. The dispersed pitches 122 and 124 and the relatively large connections may cause the interface assembly 78a and the wafer 104 to rise even in the case of the substrate 16 and the system substrate 82 made of materials having different coefficients of thermal expansion (TCE). When affected by the increased temperature, it improves the high quality electrical connection between the substrate 16 and the system substrate 82 over a wide range of operating temperatures.

Electrically conductive connections 64a-64n are permanently (ie, such as by solder or conductive epoxy) or semi-permanently (ie, on corresponding metal pads that engage tips 24 of flexible spring probes 64a-64n). To the system board 82).

In a preferred embodiment of the mass parallel interconnect assembly 78a shown in FIG. 15, the plurality of electrically conductive connections 64a-64n are flexible spring probes 64a-64n. In the embodiment of the substrate 16 where the electrically conductive connections 64a-64n are the flexible electrical connections 64a-64n, the flexible electrically conductive connections 64a-64n are typically about 4-10 mils to provide compliance. In comparison to the spring probe tips 61a-61n, it is made using a longer spring length 28 and a larger spring angle 30b (which may be up to 360 degrees). In some embodiments, flexible connections 64a-64n are compliant with photolithographic springs, such as those disclosed in US Pat. No. 5,848,685 or US Pat. No. 5,613,861, which are typically integrated as described above or incorporated herein by reference. Is built.

Conductive pads 84a-84n on the bottom side of system substrate 82 are typically aligned with pad pitch 124 (FIG. 17) such that conductive pads 84a-84n are upper connector side 62b of substrate 16. Align with electrically conductive connections 64a-64n.

Conductive pads 84a-84n on the bottom side of system substrate 82 are routed to conductive pads 84a-84n, which are typically aligned with system substrate pitch 126. Electrically conductive connections 128a-128n, which can be aligned within one or more connection regions 132, are placed on top of the system substrate 82 and routed to conductive pads 86a-84n. Electrically conductive connections 128a-128n are typically within a connection region 132 having a system substrate pad matrix pitch 120 aligned with the flex circuit pad matrix pitch 134 for each of the test electronic modules 92a-92k. Aligned.

The system substrate matrix pitch 120 is typically a flex circuit electrical connector located in a flex circuit 90 that is typically aligned with a plurality of pad matrices 88 (FIG. 16) having a flex circuit pad matrix pitch 134. 119a-119n and electrically conductive connections 128a-128n are selected to be aligned.

The test electronic modules 94a-94k are the basic schematic diagrams for most embodiments of the opposing parallel interface test assemblies 78a-78d. The test electronic modules 92a-92k are mounted in parallel (ie, as shown in FIG. 15) so that one or more rows 139 on the wafer 104 along with the test electronic modules 92a-92k are mounted. 18, 19 or column 139 form an array of modules 92a-92k that provide electronic support for a portion of die 44, respectively.

16 is a partial perspective view 110 of a mass parallel interface assembly 78a with a test electronic module 92 mounted to the frame 102. Each of the illustrated test electronic modules 92 has a preferred flex circuit 90 and one or more power control modules 100 having a pat matrix of electrical contacts 119. The flex circuit 90 for each of the test electronic modules 92 is mounted to one or more buss bars 98a-98h and extends downward through the frame 102. Bus bars 98a-98h are secured to frame 102 by electrically isolated fasteners 112, providing a very rigid structure. The frame 102 preferably includes a test electronic module alignment as well as a means 116 (FIG. 15) for securing the frame to the system alignment pin 114 and the frame 102 to the wafer chuck 106. Guide 118. Assembly 110 preferably includes other means for securing test electronic modules 92a-92k, such as a card cage (not shown), located under frame 102.

Substrate 16 interfaces to system substrate 82 which provides a standard interface to test electronics at a wide pitch. This also makes the substrate 16 the basic unit so that only the substrate 16 needs to be changed for the new device (DUT) design 44 under test or if the spring probe 61 needs to be replaced. The combined use of the substrate 16 with the popnut trace 60 and the standard pitch system substrate 82 for the small pitch spring probes 61a-61n is cost and turnaround for the test and burn-in assembly 78. decrease time)

System substrate 82, typically made of ceramic, high density printed wiring substrate, or glass substrate, provides an alignment surface with respect to substrate 16. Due to the larger pitch 122, 124 (FIG. 17) of the connection between the system substrate 82 and the substrate 16, such a reference is typically achieved by mechanical means. Of course, the system board 82 provides a first level routing interface between the tassel electronic modules 92a-92k and the substrate 16. Each of the tester electronic modules 92a-92n is attached to the system substrate 82 via a membrane or flex circuit 90.

In the interface assembly 78a shown in FIG. 15, the probe tips 61a-61n are flexible to provide planar compliance between the substrate 16 and the semiconductor wafer 104. Of course, the electrically conductive connections 64a-64n, which are preferably flexible conductive springs 14, provide flatness compliance between the substrate 16 and the semiconductor wafer 104. Thus, interface assembly 78a provides flatness compliance between substrate 16 and wafer 104. Of course, the interface assembly 78a also has a coefficient of thermal expansion (TCE) between the substrate 16 (typically composed of ceramic, ceramic glass, glass or silicon) and the system substrate 82 (typically composed of glass epoxy material). Accept the difference.

The flexible connections 64a-64n are preferably disposed on a standardized layout pattern that can match the standardized power and ground pad patterns (ie, assignments) on the system board 82 so that the system boards 82 are next to each other. It is possible to use the substrate 16 arranged to engage another integrated circuit element 44. The system substrate 82 can be adapted to the dedicated substrate 16 for testing of a variety of different devices 44, thereby reducing the operating cost for the system substrate 82.

Lower substrate standoffs 75, typically larger than other features on the substrate 16 (except for the spring tips 61a-61n), preferably lie on the lower surface 62a of the substrate 16, By coinciding with saw streets 94 on the semiconductor wafer 104 under test, it prevents the wafer under test 104 from colliding with the substrate 16 and protects the active area on the semiconductor wafer 104 from damage. prevent.

Contact between the test electronics module 92a-92k and the system substrate 82 is achieved by solder, pressure contact, or spring contact 119, 128. The spring probe tips 119 and 128 (FIG. 17) may have various tip geometries such as one point spring 14, interleaved spring 34 or shoulder point spring 50. And are typically fabricated on the substrate 16 using thin film or MEMS processing methods to achieve low manufacturing costs, well controlled uniformity, extremely fine pat pitch 20 and large pin counts. In some embodiments, flexible connections 119 and 128 are in compliance to photolithographic springs, such as those disclosed in US Pat. No. 5,848,685 or US Pat. No. 5,613,861, incorporated herein by reference or incorporated herein by reference. Is built.

The configuration shown in FIG. 15 brings power through the power module 100 switchable from the pin electronic device card 94 to the system board 82 and the input / output signal 148 (FIGS. 2, 23). This configuration has the advantage of reducing routing congestion in the flex circuit or membrane 90.

The structure of the interface assembly 78a provides an extremely short electrical distance between the probe tips 61a-61n and the control impedance environment at the system board 82, allowing the interface assembly 78a to be used in high frequency applications. In embodiments where one or two surfaces 62a and 62b of the substrate 16 are required for impedance control, one or more conductive reference planes may be added within the substrate 16 above, below or above and below the trace. Can be. For very high frequency applications, the substrate 16 is regularly (FIG. 13) using one or two reference planes 58a using vias 65a and 65b to effectively provide a shielded coaxial transmission line environment 63. 58b) (FIG. 13), which may include an alternate ground reference trace.

18 is an enlarged layer plan view of wafer 104, circular substrate 16, and rectangular system substrate 82. In the case of a substrate 16 composed of silicon, which may preferably be selected to match the thermal expansion coefficient (TCE) of the wafer 104, the silicon substrate 16 is preferably manufactured by a processor similar to the wafer 104. Substrate 16 may be fabricated from circular wafer substrate 16.

19 is an enlarged layer plan view of the wafer 104, the plurality of rectangular substrates 16a, 16b, 16c, 16d and the rectangular system substrate 82. In the case of a substrate preferably made of ceramic material, the silicon substrate 16 may preferably be made of one or more rectangular ceramic substrates 16a, 16b, 16c, 16d. Any one of the substrates 16, 16a-16b may be such as one or more top standoffs 133 placed on the connector side of the substrate 16, such as to limit the vertical running of the substrate relative to the system substrate 82. A travel limit mechanism.

As can be seen in FIGS. 18 and 19, elements 44, each comprising a plurality of pads 47, are formed on a wafer 104, and saw streets are arranged in rows 137 and columns 139. Are arranged across the wafer 104 by a series of rows 137 and columns 139, which are placed between the two columns. As can be seen in the system board 82 in FIGS. 18 and 19, the electrically conductive connections 128a-128n overlying the top surface of the system board 82 are typically aligned within one or more connection regions 132, Connect to flex circuit connector 119 (FIG. 17), which is preferably aligned within one or more pad matrix 88 (FIG. 16) of similar numbers.

In some preferred embodiments of the mass parallel interface assembly 78, each of the test electronic modules 92 (ie 92a) is the same as the other test electronic modules (ie 92b-92k), such that the same number of test components By the same test capacity). In some embodiments of the mass parallel interface assembly 78, a similar number of elements 44 are routed to each test electronic module 92a-92k.

In alternative embodiments of the mass parallel interface assembly 78, different numbers of devices 44 may be used, such as for external heat 139 of the device 44 under test on a particular wafer 106, such as for test electronic module 92. (I.e. 92a). For a plurality of standard test electronic modules 92a-92k having the same number of test components, system control 230 or by programming the test electronics 92 to bypass testing for unused test circuits 94. ), A test electronic module 92 having a capacity larger than the number of devices 44 connected can still be used.

20 is a partial cross-sectional view of one embodiment of a flexible circuit substrate 142a having a polyimide layer 144a and opposing conductive layers 146a and 46b. FIG. 21 is a partial cross-sectional view of an alternative embodiment of flexible circuit 90, having a dielectric flex circuit membrane structure 142b and opposing conductive layers 146a, 146b. In some embodiments of flex circuit 90, flex circuit membrane structure 142 is inherently flexible. In an alternative embodiment of flex circuit 90, flex circuit 142 is rigid in the region where one or two conductive layers are substantially placed. Controlled removal of conductive layers 146a and 146b provides controlled flexibility for flex circuit 90 while providing an area of conductive paths formed.

22 is a partial perspective view of a flexible membrane circuit structure in which flexible region 90a is defined in test card structure 94a. 23 illustrates test card structure 94b in which flexible circuit 90b is formed by attachment member 150 (ie, including but not limited to fixture, heat staking, microwelding or adhesive). Is a partial perspective view of an alternative flexible circuit structure attached to a.

Test electronics 94a and 94b disposed in each of test electronic modules 92a-92k provide stimulus and response detection for one or more of the devices 44 under test. The test electronics 94a and 94b are mounted on a high density interconnect (HDI) substrate 142a and 142b or a standard printed wiring board 94a that is connected to the flexible circuit 90. Test electronic cards 94a and 94b are installed together with control and response electronics (such as test electronics 240 in FIG. 35). Each test electronic module 92 (ie, 92a) is connected to the electronics and the computer interface link 96 (typically by a parallel or serial link). Optionally, signal pins in the tester electronic modules 92a-92k are connected in series on a daisy chain to simplify electrical connections such as external test hardware. Test vectors and setup information are sent from the system computer 202 and the control electronics (such as the external pattern generator 246 in FIG. 35) via the link 96 to the pin electronics.

Within each of the test transfer modules 92a-92k, a test electronic card 94 is attached to the flex circuit / membrane 90. The test electronic card 94 is preferably fabricated as an internal structure with a flexible circuit 90, such as an etched thin film substrate, such that a portion of the substrate is etched to make the flexible membrane circuit 90. In alternative embodiments of the test electronic module, the individual test electronic card substrate 94 is typically connected to the flex circuit by solder, wire bond or connector.

24 preferably includes a test electronic module, including a thermally conductive pathway 154 across the flex circuit 90 between the power control module 100 and one or more bus bars 98. 92 is a partial cross-sectional view of one embodiment of flex circuit region 90. Each bus bar 98a-98h, which is typically connected to a plurality of external power sources 234a-234h (FIG. 35), is electrically spaced apart from each other by an insulator 152. Insulator 152 may be a spaced layer from bus bars 98a-98h or may be an electrically insulating layer 152 on bus bars 98a-98h.

25 illustrates a flex circuit of test electronics module 92, in which one or more power control modules 100a-100h are mounted on an inner surface of flex circuit 90 and are arranged to be in thermal contact with a plurality of bus bars 98a-98h. Partial cross-sectional view of an alternate embodiment of region 90.

FIG. 26 is a partial cross-sectional view of a second alternative embodiment of the flex circuit region 90 of the test electronic module 92 with the power module 100 electrically connected to the outer surface of the flex circuit 100. The power control actuation region 158 is preferably defined through the flex circuit region 90 so that the power control module 100 is in thermal contact with the bus bar 98 (such as bus bar 98b).

One or more power and ground bus bars 98a-98h are used to distribute power for all devices 44 under test. The power control module 100, which typically includes a decoupling capacitor, a switching control circuit and a regulator for each device 44 under test, preferably has a flex circuit 90, as shown in FIG. 24, 25 or 26. ) Is mounted on.

Although some preferred embodiments of the test electronic modules 92a-92k include a flex circuit structure 90, the unique interface structure provided by the flex circuit structure 90 can be achieved by other suitable interface designs. FIG. 27 is a perspective view of an alternate embodiment of test electronic module 92 in which an integrated module base 157 provides a pad metric 88 of electrical contact 119 on pad metric flat region 158. . One or more power control modules 100 are electrically connected to electrical contacts 119 placed in the pad matrix or to one or more bus bars 98a-98h through power control module (PCM) traces 149. The power control module 100 is preferably arranged in thermal contact with one or more bus bars 98a-98h. Signal trace 148 is also connected to electrical contact 119 which is placed in pad matrix 88. The signal trace 148 extends over the link and component planar regions 159 and is connected to the test electronics 94 or to the link 96.

In various embodiments of test electronics module 92, one or more bus bars 98 provide a power and heat sink path to power control module 100. Power for the device 44 under test can typically be provided through individual rail bus bars 98 or optionally share the same rail bus bar 98 with the power control module 100. . The power rail bus bar 98 also preferably provides mechanical support for the flex circuit 90 and system board 82 and / or test electronic cards 94a-94k. In some embodiments of the test electronic modules 94a-94k, the power control module circuit 100 is connected to a series scan path to provide individual power and ground control to the device 44 under test.

Alternative bulk parallel test assembly. FIG. 28 shows a partial cut assembly of an alternate mass parallel test assembly 78b with an intermediate system substrate 82 with the flexible spring probe 160 resting on the bottom face 139b (FIG. 17) of the system substrate 82. It is also. The structure and features of the mass parallel test assembly 78b are the same as the mass parallel test assembly 78a shown in FIG. The system substrate spring probe 160, in conjunction with electrically conductive connections 64a-64n on the substrate 16, provides flatness compliance between the system substrate 82 and the substrate 16 and provides high quality electrical over a wide temperature range. Provide a connection.

FIG. 29 is a partial cross-sectional view of an alternate interface assembly 78c with a large grid array (LGA) interposer conenctor 162 placed between the substrate 16 and the system substrate 82. The LGA interposer connector 162 provides a plurality of conductors 164a-164n between the electrical connections 64a-64n on the substrate 16 and the plurality of conductive pads 84a-84n on the bottom surface of the system substrate 82. . In one embodiment, the LGA interposer connector 162 is an AMPIFLEX ^™ connector manufactured by AMP, Harrisburg, PA. In another embodiment, interposer connector 162 is a GOREMATE ^™ connector manufactured by WL Gore and Associates, Eau Clare, WI. In another embodiment, pogo pin interposers 162 are used to connect opposing conductive pads 84a-84n on system substrate 82 to electrical connections 64a-64n on substrate 16. do.

30 is a partial cutaway view of a basic mass parallel test assembly 78d with substrates 16 having spring probes 61a-61n directly connected to test electronic modules 92a-92k. FIG. 31 is a partially enlarged cross-sectional view 166 of a basic mass parallel test assembly 78d showing a test electronic module 92 having a pad matrix 88 of a substrate 16 and an electrical contactor 119.

32 is a partial cross-sectional view 170 of a mass parallel interface assembly 178d illustrating one embodiment of a basic clamping structure 172. The interface assembly 178e is typically for burn-in testing only and therefore the test electronics 94 are packaged in a small module 174. Module 174 is mounted directly on system board 82 and is preferably used for burn-in testing that requires significantly less test electronics (such as shown in FIG. 15) than test electronics modules 92a-92k. . The clamping structure 172 shown in FIG. 32 may also be used for the wafer level bulk parallel interface assemblies 178a-178d.

The interposer substrate 16 is preferably made from a thin substrate 16, such as a 10 mil thick glass plate, such that the substrate 16 is non-flat or bowling between the wafer 134 and the interposer substrate 16. Flexes may be matched to the surface of the wafer under test to accommodate bowing.

Seal 180 around interposer substrate 16 preferably provides a sealing chamber 182. An air pressure is preferably applied between the system substrate 82 and the interposer substrate 16. The applied pressure 184 also thermally isolates the DUT wafer 104 from the test electronics 174, 94. Although the DUT wafer 104 is typically required to operate at elevated temperatures during burn-in testing (such as at 125-160 degrees Celsius), the test electronics 94 are preferably low (such as below 75 degrees Celsius). It must operate at temperature.

Wafer chuck 106 preferably includes a wafer thermal control system 192 that preferably includes a wafer heating system 194 and / or a wafer cooling system 196 to provide temperature control to the wafer 104 under test. It is provided. Wafer thermal control system 192 is preferably controlled by test system temperature controller 188, which is typically linked to system controller 232 (FIG. 35).

The test electronics 174, 94 are preferably located in one or more cooling chambers 176. The cooling chamber 190 is preferably used to cool the operating temperature of the test electronics 174, 94 in the cooling chamber 176 and is preferably controlled by the test system temperature controller 188.

A wafer loading vacuum circuit 186 having a vacuum track 208 (FIG. 33) is preferably installed in the wafer chuck 106 to position the wafer under test (DUT) 104 in place and the substrate connector 16. ) And the flatness between the wafer 104 under test.

Test system architecture. The test system consists of an alignment setup that performs wafer alignment, a cooling unit, and tester electronics. The alignment subsystem and cooling unit can be built according to techniques known in the art.

System alignment . 33 is a first partial enlarged cross-sectional view illustrating a mass parallel test assembly 200 and alignment hardware and procedures. The test assembly 200 includes a carrier ring 202 that preferably includes one or more alignment features, such as the alignment pin 206, such that the carrier ring 202 can be aligned to the system substrate 82. To be. System substrate 82 preferably has a mating alignment feature such as alignment retainer 226 (FIG. 34).

The substrate 16 is mounted to be released to the carrier ring 202 by a flexible tape 204 (such as a ring-type KAPTON ^™ tape), so that the electrical connections 64a-64n (on the connector face 62b of the substrate 16) ( 31, such as shown in FIG. 31, is aligned with the alignment pins 206 so that the electrical connections 64a-64n on the connector face 62b of the substrate 16 have conductive pads 84a on the bottom surface of the system board 82. -84n) (FIG. 17).

The wafer chuck 106 preferably includes a wafer loading vacuum circuit 186 having one or more wafer loading holes 208 on the wafer loading surface 209. Wafer loading vacuum circuit 186 is connectable to vacuum source 210 and may be sealed by wafer loading vacuum circuit 212. The wafer 104 to be tested is placed in the wafer chuck 106 and in place by an applied vacuum applied through the wafer loading hole 208.

The substrate 16 mounted on the carrier ring 202 mounted to the wafer chuck 106 is controllably positioned over the wafer 104 in place by the vacuum applied to the wafer chuck 106. The substrate 16 and the wafer 104 to be tested are precisely aligned by a lookup / lookdown camera 214 within the modified wafer probe system 216, so that the probe face 62a of the substrate 16 is aligned. Probe springs 61a-61n on FIG. 17 are aligned with die pad 47 on DUT wafer 104. Typically alignment is achieved by looking at the spring tip 24 (FIG. 2) or the alignment mark 77 (FIG. 14) on the substrate 16.

Wafer chuck 106 preferably includes a carrier ring vacuum circuit 218 having one or more carrier ring vacuum holes 220. The carrier ring vacuum circuit 218 is also connectable to the vacuum source 220 and may be sealed by the carrier vacuum circuit valve 222. Once the substrate 16 and the wafer 104 to be tested are correctly aligned, the look up / look down camera 214 is removed, and the carrier ring 202 is controllably moved to the wafer chuck 104 so that the substrate 16 The substrate 16 is correctly positioned over the wafer 16 such that the probe springs 61a-61n on the probe face 62a of the NELDA) contact the die pad 47 on the DUT wafer 104. The carrier ring 202 is positioned in place by the vacuum applied through the carrier ring vacuum hole 220.

The wafer loading vacuum circuit valve 212 and the carrier ring vacuum circuit valve 222 are closed to maintain the applied vacuum to the wafer loading vacuum circuit 206 and the carrier ring vacuum circuit 218, while the system substrate 82 is maintained. And for mounting to the test electronic modules 92a-92k, the entire test assembly can be processed integrally. In alternative embodiments of the wafer loading vacuum circuit 206 and the carrier ring vacuum circuit 218, a signal valve is used to apply a sealable vacuum to both the vacuum circuits 206, 218. In order to increase the vacuum holding capability after the vacuum circuit valves 212 and 222 are closed, each circuit 206 and 218 preferably includes a vacuum chamber that serves to maintain the vacuum level over time.

FIG. 34 is a second, partially enlarged cross-sectional view illustrating that the mass parallel test assembly and alignment hardware and procedure 224, thereby allowing the mass parallel interface test assembly 78 to be assembled into a system that can be used for wafer testing. As described above, the system substrate 82 preferably includes means for the tuck 226 in the carrier ring and / or wafer chuck 106, such as the alignment holes 226. The system board 102 mounted to the test electronic modules 92a-92k and the frame 10 is disposed above the carrier ring 202 so that the alignment pins 206 engage the alignment holes 226. An attachment means 228 is then provided between the frame 102 and the wafer chuck 106 or carrier ring 202 to complete the assembly structure.

Although accurate means (such as for optical alignment) can be used to align the fine pitch probe springs 61a-61n to the fine pitch pads 47 on the wafer to be tested, the carrier ring 202 and the system substrate 82 The mechanical alignment provided in (ie, between the alignment pins 206 and the holes 226) is preferably distributed electrical connections 64a-64n and pads 84a, which have larger characteristics and have larger pitches 122,124, respectively. -84n) is sufficient. Of course, the flex circuit 134 on the pad matrix is relatively large (ie, about 1 mm), making the alignment between the test electrical modules 92a-92k and the system card 82 relatively similar using conventional mechanical alignment techniques. .

Tester electronics . 35 is a partial schematic block diagram of test circuit 230 for mass parallel test system 78. Tester electronics 230 include, but are not limited to, control computer 232, power subsystems, test electronics modules 92a-92k, DC parameters and measurement systems 236,238, and control electronics.

As shown in FIG. 35, the test electronic module 92 typically includes one or more devices to be tested (such as, but not limited to, the columns 139 of the device 44 under test) on a set of wafers 104 44).

Each of the test electronic modules 92a-92k provides a stimulus signal 250 to the device (DUT) 44 to be tested and monitors the response 254, or in accordance with the test pass or failure information 258 in the tester memory. Transmit or send the pass or failure information 258 of the device under test to the system controller 232.

For example, in memory testing, test electronics module 92 has all the important functions of a memory tester. It includes a hardware pattern generator 246 that drives the memory device 44 under test that is connected in parallel to the same test electronic module 92. The response detection and fault detection circuitry of the test electronic module 92 records the fault location for the device 44 under test, respectively, as needed.

Since the test electronic module 92 is preferably reconfigurably programmable by software, it is possible to configure the test electronic module 92 for a specific DUT design or test function. In order to provide ancillary test features, a built-in self-test (BIST) engine may also be integrated into the test electronic module 92.

Each test electronics module 92 also includes one or more DC measurement subsystems 238 for performing an analog measurement of the output signal 254 to the digital test electronics in the test electronics module 92 or to the intended DUT pin 47. In order to route it, it provides analog multiplexing.

Sample test sequence . After the wafer 104 to be tested is loaded, aligned, and engaged, the system controller 232 sends control signals to all power control modules 100 to provide all power and ground for the device under test (DUT) 44. Pin 47 is connected to ground except selected pin 47 which is controlably connected to DC parameter unit 236. Power supplies 234a-234h are separated from power buses 98a-98h. The power pin integrity of the selected device 44 is determined via the DC parameter unit 236.

A DC parameter unit 236 connected to the power rails 98a-98h via a relay or solid state switch 235 is programmed to check power for ground shorts. The same sequence is repeated for all power pins on all devices 44 under test.

In order to determine the short and open circuits for the selected device under test 44, similar testing is performed on the DUT input and output pins 47 via the test electronic card 94. Open connections for the device under test 444 are typically detected by the absence of parasitic diodes in the input and output pins 47 of the device 44 under test, as is commonly practiced in the art.

Upon completion of setup testing, the integrity of the connection and state of each device pin 47 is determined for an open or short circuit. Many measured open circuits for one or more of the devices under test 44 on the wafer 104 may be due to system setup or one or more of the detection devices 44 under test.

The test circuit 230 preferably provides diagnostic capabilities for diagnosing failures. The short can be isolated from the power bus 98 and the pin test electronics 94 by scanning the appropriate bit control pattern to the power control module 100 and the pin test electronics module 92.

Power is then applied to the remaining elements 44 to be tested and tested in parallel. The short circuit detection and reporting circuit is preferably installed in each of the power control modules 100 so that if the short circuit is found in the device under test while the device 44 is tested, the particular device under test 44 may be disconnected. have. Other features, such as transient device current testing circuitry, may be included in power control module 100, such as to provide incidental test coverage.

Power pin testing . System controller 232 selectively switches onto the power connections for one or more of the devices under test 44. As the power supplies 234a-234h are turned off (shorted), the device 44 under test can be tested for open and short circuits using the DC parameter unit 236.

I / O pin testing . Similarly, input and output pins 47 on device 44 under test can be tested for leakage, opening, and shorting through system controller 232.

Device functional testing . Using the test results from power pin testing and I / O pin testing, for any device under test 44 that failed (i.e. due to power), the input and output pins 47 for the failed device 44 ) Is isolated from the tester common response. After the power pin testing and I / O pin testing, the remaining device under test 944) can be powered up and tested in parallel.

Functional testing . Stimulus unit 248 and pattern generator 246 generate input pattern 250 on device 44 under test. DUT response 254 is captured in response block 256, which compares the output of device 44 under test with the expected value from pattern generator 246 or stimulation unit 248. Pattern generator 246 is often used for memory testing, while a true table representing device stimulus 250 and expected response 254 may be stored in pattern memory of stimulus unit 248 for logic device testing. A failure map or log 258 is maintained for each die 44. Although Figure 35 illustrates one embodiment of a functional diagram of the pattern generation and stimulus / response system architecture, As is often practiced, other pattern generation and stimulus / response system architectures can be used as appropriate to meet the testing conditions of the device 44 under test.

Alternate interface embodiment . 36 is a partial cutaway view of a mass parallel interface assembly 270a in which a plurality of interface modules 272a-272j are electrically connected to the system interconnect substrate 286a. Each interface module 272 (such as 272a) has a pad matrix 88 of electrical conductors 119 electrically connected to the probe spring interposer 276, respectively.

Each probe spring interposer 276 includes a bottom spring probe 280 electrically connected to the top spring probe 284 by a via 282. As described above, the top spring probe 284 as well as the bottom spring probe 280 may have various tip topologies such as the single point spring 14, interpolation spring 34, or shoulder point spring 50 and In order to achieve low fabrication cost, well controlled uniformity, and extremely fine pad pitch 20, a thin film or MEMS processing method is used to fabricate the substrate 16. In some embodiments, flexible contact bottom spring probe 280 and / or top spring probe 284 are disclosed in US Pat. No. 5,848,685 or US Pat. No. 5,613,861, incorporated herein by reference or incorporated herein by reference. It is compliantly installed in photolithographic springs such as

Probe spring interposer 276 provides an electrical connection between each interface module 272a-272j and the system interconnect substrate 286a. The system interconnect substrate 286a has a top surface electrical contactor 290, a via 291, a top surface interconnect structure 292 and a bottom surface interconnect structure 294, one on each interface module 272. The above pads can typically be connected together. System interconnect substrate 286a may also include substrate electrical components that may be electrically connected to one or more interface modules 272. Each interface module 272 includes a link 96 that provides an electrical connection to the system interconnect board 286a and preferably also includes an interface module circuit 298.

37 illustrates a plurality of interface modules 272a-272j electrically connected to system interconnect boards 286b including flexible probe springs 64a-64n as described above via system board interposer 300. Partial cut assembly view of an alternate mass parallel interface assembly 270b that is connected. System board interposer 300 may preferably include interconnect structure 302 and / or substrate electrical component 304 that may be electrically connected to one or more interface modules 272.

Each of the mass parallel interface assemblies 270a and 270b provides a universal and robust interface between a plurality of interconnected structures. Mass parallel interface assembly 270a may simply be used to provide a robust mass parallel interface (such as providing complex parallel connections between similar components). In a preferred interface embodiment, the mass parallel interface assembly 279a279b may also include module specific cell circuits 298 or shared circuits 296.

38 shows a systematic block diagram 306 of a connection between a plurality of computer systems 308a-308n using the mass parallel interface assembly 270. 39 shows a systematic block diagram 310 of a connection between a plurality of electronic circuits 312a-312n using a mass parallel interface assembly 270.

System advantages . A continuous assembly layer (such as the pad matrix 88 on the substrate 16, the system substrate 82, and the test electronics modules 92a-92k) with the mass parallel interface assembly 78a-78d, the wafer 104. Provides signal and power interconnection between the test set and the plurality of devices 44 overlying the wafer 104 while providing flatness in the liver.

Of course, the mass parallel interface assemblies 78a-78d are vertically packaged test electronic modules that include high pitch spring probe tips 61a-61n, layered substrates 16, 82, and typically flex circuits 90. The combination of 92a-92k provides a short electrical path for power and input and output signals between the test electronic module 92a-92k and the device 44 under test.

Moreover, the bulk parallel interface assemblies 78a-78d provide short electrical paths for power and input and output signals between the test electronic modules 92a-92k and the device 44 under test, while the mass parallel interface assemblies 78a- 78d) provides thermal isolation between the test electronics 94 and the device under test 44 while providing uniform force across all mating spring probes 61 and pads 47 over the entire wafer 104. As such, the test electronic modules 92a-92k provide increased heat transfer away from the heat sensing components (ie, through the bus bars 98a-98h) and preferably provide increased test module temperature control. The device 44 in question can be controlled to operate over a wide temperature range.

Of course, although the device 44 under test operates controllably over a wide temperature range, the mass parallel interface assemblies 78a-78c preferably have a test system, a substrate 16, and a large pitch over the temperature range. By using an appropriate size between the system boards 82, large pitches 122 and 124, which maintain electrical contacts between the interconnects 74a-64n, and fine pitch 20 interconnects 61a- over the temperature range. By using a particular substrate 16 having a similar coefficient of thermal expansion for the wafer 104 under test (which maintains electrical contact between 61n), many devices 44 and tests placed on the wafer 104 maintained over a temperature range Provides power and signal interconnect between systems.

As described above, the mass parallel interface assembly 78 quickly detects power to ground short on any die and separates power from the die with the detected power to ground short before the test electronics are damaged. Can be used. In addition, the mass parallel interface assembly 78 and associated test systems detect whether many, hundreds, or even hundreds of thousands of pads are reliably contacted and each contact is within the contact resistance specification, and the magnetic inductance and magnetic capacitance of each signal line It can be used to be below a value that will adversely affect test signal integrity.

Moreover, mass parallel interface assembly 78 and associated test systems can be used to detect whether mutual inductance and mutual capacitance between signal line pairs and between signal lines and power or ground lines are below a value that would adversely affect test signal integrity.

Of course, the mass parallel interface assembly 78 can reliably and repeatedly establish contact with many, hundreds, or even hundreds of thousands of pads 47 without the need to periodically routinely inspect, inspect, and / or clean the probe interface structure 16. have.

Moreover, the bulk parallel interface assembly 78 inherently configures and manages interconnections between the device under test 44 and the tester electronics 230 while maintaining signal integrity and power and ground stability, and any two or more adjacent pads. (47) also prevents contact by one test probe tip.

Although the disclosed mass parallel interface assembly has been described with reference to integrated circuit testing, computer networking, and circuit connections, the assembly and techniques are integrated circuits within electronic components or devices, burn-in devices and MEMS devices, or any combination thereof as needed. And a wide range of devices and circuits such as interconnects between substrates.

Thus, although the invention has been described in detail with reference to certain preferred embodiments, those skilled in the art will recognize that various modifications and changes can be made without departing from the spirit and scope of the appended claims.

Claims (78)

A system for connecting to at least one integrated circuit device on a wafer, the system comprising: A system substrate having a bottom surface and a top surface, and a plurality of electrical conductors between the bottom surface and the top surface; A substrate having a probe surface and a connector surface, the probe surface comprising a plurality of spring probe contact tips for connecting to the at least one integrated circuit element, and a plurality of spring probe contact tips Having a plurality of electrical connections extending through the substrate between each and the connector face; A plurality of electrically conductive connections between each of the plurality of electrical connections on the connector face of the substrate and each of the electrical connectors on the bottom face of the system substrate; At least one having a plurality of electrically conductive pads on a planar region, at least one of the electrically conductive pads connected to at least one interconnection region, and at least one link connected to at least one of the at least one interconnection region An interface module; And Means for securing and retaining each of the at least one interface module relative to the system substrate And wherein the plurality of electrically conductive pads on the flat area of the at least one interface module contact at least one of the plurality of electrical conductors on the top surface of the system substrate. The system of claim 1, wherein the plurality of spring probe contact tips on the probe face of the substrate are photolithographically patterned springs. The flexible spring of claim 1, wherein the plurality of electrically conductive connections between each of the plurality of electrical connections on the connector face of the substrate and each of the electrical connectors on the bottom face of the system substrate are flexible springs on the connector face of the substrate. System that is a flexible spring probe. 4. The system of claim 3, wherein the flexible spring probe on the connector face of the substrate is a photolithographically patterned spring. 2. The flexible spring of claim 1, wherein a plurality of electrically conductive connections between each of the plurality of electrical connections on the connector face of the substrate and each of the electrical connectors on the bottom of the system board are flexible springs on the bottom of the system board. System that is a flexible spring probe. 6. The system of claim 5, wherein the flexible spring probe on the bottom of the system substrate is a photolithographically patterned spring. The system of claim 1, wherein each of the at least one interface module includes a circuit having a first side and a second side, and the plurality of electrically conductive pads overlie the first side. 8. The system of claim 7, wherein the circuit is a flexible circuit. 8. The system of claim 7, wherein the circuit is a semi-rigid circuit. 8. The system of claim 7, wherein the circuit is a rigid circuit. 2. The apparatus of claim 1, further comprising an interposer substrate lying between the connector face of the substrate and the bottom face of the system substrate, wherein each of the plurality of electrical connections on the connector face of the substrate and the And a plurality of electrically conductive connections between each of the electrical connectors on the bottom of the system substrate lies within the interposer substrate. The system of claim 1, further comprising at least one buss bar electrically connected to at least one of the at least one interconnect area. 13. The apparatus of claim 12, further comprising at least one power control module overlying the at least one interface module, wherein each of the at least one power control module comprises the at least one bus bar and the at least one interconnect area. A system electrically connected between at least one of the two. The system of claim 13, wherein the at least one power control module is in thermal contact with the at least one bus bar. 13. The apparatus of claim 12, further comprising at least one pre-control module overlying the at least one bus bar, wherein each of the at least one power control module comprises at least one bus bar and the at least one interconnect area. A system electrically connected between at least one of the two. The system of claim 15, wherein the at least one power control module is in thermal contact with the at least one bus bar. The system of claim 1, further comprising at least one lower substrate standoff fixedly attached to the probe face of the substrate. The system of claim 1, further comprising a travel limit mechanism for limiting the perpendicular travel of the substrate relative to the system substrate. The substrate of claim 1, wherein the substrate has a plurality of holes defined between the probe surface and the connector surface, wherein each of the plurality of electrical connections between each of the contact tips and the electrically conductive connection is formed of the substrate. And a electrically conductive via in each of the plurality of holes. The system of claim 1, wherein the substrate is electrically insulating. The system of claim 1, wherein the substrate is a dielectric. The system of claim 1, wherein the substrate is electrically conductive. The system of claim 1, wherein the substrate is comprised of a material having a coefficient of thermal expansion similar to that of the wafer. The system of claim 1, further comprising an assembled component lying on the substrate. The system of claim 24, wherein the assembled component is a passive component. 27. The system of claim 25, wherein the manually assembled component is a capacitor. The system of claim 24, wherein the assembled component is an active component. The system of claim 1 further comprising an integrated component as the fabricated structure of the substrate. 29. The system of claim 28, wherein the fabricated structure is a passive component. 30. The system of claim 29, wherein the manually fabricated structure is a capacitor. 29. The system of claim 28, wherein the fabricated structure is an active component. The system of claim 1, wherein the substrate comprises silicon. A system for connecting to at least one integrated circuit device on a wafer, the system comprising: A substrate having a probe surface and a connector surface, the probe surface comprising a plurality of spring probe contact tips for connecting to the at least one integrated circuit element, and the plurality of contacts. Having a plurality of electrical connections extending through the substrate between each of the tips and the connector face; At least one having a plurality of electrically conductive pads on a planar region, at least one of the electrically conductive pads connected to at least one interconnection region, and at least one link connected to at least one of the at least one interconnection region An interface module; A plurality of electrically conductive connections between each of the plurality of electrical connections on the connector face of the substrate and the plurality of electrically conductive pads overlying the flat area of the at least one interface module; And Means for securing and retaining each of the at least one interface module relative to the substrate And the plurality of electrically conductive pads on the flat area of the at least one interface module contact at least one of the plurality of electrical connections on the connector side of the substrate. 34. The system of claim 33, wherein the plurality of spring probe contact tips on the probe face of the substrate are photolithographically patterned springs. 34. The system of claim 33, wherein the plurality of electrical connections on the connector face of the substrate is a flexible spring probe. 36. The system of claim 35, wherein the flexible spring probe on the connector face of the substrate is a photolithographically patterned spring. 34. The system of claim 33, wherein each of the at least one interface module comprises a circuit having a first side and a second side, wherein the plurality of electrically conductive pads lie on the first side. 38. The system of claim 37, wherein the circuit is a flexible circuit. 38. The system of claim 37, wherein the circuit is a semi-rigid circuit. 38. The system of claim 37, wherein the circuit is a rigid circuit. 34. The system of claim 33, further comprising at least one buss bar electrically connected to at least one of the at least one interconnect area. 42. The apparatus of claim 41, further comprising at least one power control module overlying the at least one interface module, wherein each of the at least one power control module comprises the at least one bus bar and the at least one interconnect area. A system electrically connected between at least one of the two. 43. The system of claim 42, wherein the at least one power control module is in thermal contact with the at least one bus bar. 42. The apparatus of claim 41, further comprising at least one pre-control module overlying the at least one bus bar, wherein each of the at least one power control module comprises at least one bus bar and the at least one interconnect area. A system electrically connected between at least one of the two. 45. The system of claim 44, wherein the at least one power control module is in thermal contact with the at least one bus bar. 34. The system of claim 33, further comprising at least one lower substrate standoff fixedly attached to the probe face of the substrate. 34. The system of claim 33, further comprising a travel limit mechanism for limiting perpendicular travel of the substrate for at least one of the at least one interface module. 34. The substrate of claim 33, wherein the substrate has a plurality of holes defined therethrough between the probe face and the connector face, wherein each of the plurality of electrical connections between each of the contact tips and the electrically conductive connection is connected to the substrate. And a electrically conductive via in each of the plurality of holes. The system of claim 33, wherein the substrate is electrically insulating. The system of claim 33, wherein the substrate is a dielectric. The system of claim 33, wherein the substrate is electrically conductive. 34. The system of claim 33, wherein the substrate is comprised of a material having a coefficient of thermal expansion similar to that of the wafer. 34. The system of claim 33, further comprising assembled components lying on the substrate. 54. The system of claim 53, wherein the assembled component is a passive component. 55. The system of claim 54, wherein the manually assembled component is a capacitor. 54. The system of claim 53, wherein the assembled component is an active component. 34. The system of claim 33, further comprising an integrated component as the fabricated structure of the substrate. 59. The system of claim 57, wherein the fabricated structure is a passive component. 59. The system of claim 58, wherein the manually manufactured component is a capacitor. 59. The system of claim 57, wherein the fabricated structure is an active component. The system of claim 33, wherein the substrate comprises silicon. In the interface module, An electrically insulative module base extending from the planar region; A plurality of electrically conductive pads overlying said flat region of said electrically insulating module base; A power control module in contact with the electrically insulating module base and having at least one electrical connection to one of the plurality of electrically conductive pads; And An electrical conductor in electrical and thermal contact with the power control module, a portion of the electrical conductor extending from the electrically insulating module base Interface module having a. 63. The interface module of claim 62 further comprising a plurality of conductive traces connected to the plurality of electrically conductive pads overlying the flat region and extending to a link connection. The method of claim 62, At least one electronic component lying on the electrically insulating module base, and And at least one component trace connected between the at least one electronic component and the link region. The method of claim 62, At least one electronic component overlying the electrically insulating module base, and And at least one component trace connected between the at least one electronic component and at least one of the plurality of electrically conductive pads overlying the flat region. The method of claim 62, At least one electronic component overlying the electrically insulating module base, and And at least one component trace connected between the at least one electronic component and at least one of the plurality of electrically conductive pads overlying the flat region. 63. The interface module of claim 62 further comprising a plurality of spring probes connected to the plurality of electrically conductive pads and extending from the flat region of the electrically insulating module base. 68. The interface module of claim 67 wherein the plurality of spring probes are photolithographically patterned springs. In the process, A substrate having a probe face and a connector face, the probe face having a plurality of spring probe contact tips, and a substrate having a plurality of electrical connections extending through the substrate between each of the plurality of contact tips and the connector face. Providing; Providing a wafer having a top surface and a bottom surface, the wafer having a plurality of pads overlying the top surface; Attaching the wafer to a wafer carrier; Providing a carrier ring having a cavity defined therethrough; Attaching the substrate to the carrier ring such that the substrate lies entirely within the cavity of the carrier; Aligning the attached substrate with the attached wafer such that the plurality of spring probe contact chips on the probe face of the attached substrate are aligned with the plurality of pads placed on the upper surface of the wafer; And Moving the carrier ring and the wafer carrier in contact with the aligned plurality of spring probe contact chips on the probe face of the attached substrate to contact the plurality of aligned pads placed on the top surface of the wafer. step Process comprising. 70. The process of claim 69, wherein attaching the wafer to the wafer carrier ring comprises aligning the substrate to the carrier ring. 70. The process of claim 69, wherein attaching the wafer to the carrier ring comprises aligning the substrate to the carrier ring. The process of claim 69, wherein the alignment between the attached substrate and the attached wafer is optical alignment. 70. The process of claim 69 wherein the plurality of spring probe contact chips on the probe face of the substrate are photolithographically patterned springs. 70. The process of claim 69, wherein the plurality of electrical connections extending to the connector face on the substrate comprises a flexible spring probe on the connector face of the substrate. 75. The process of claim 74, wherein the flexible spring probe on the connector face of the substrate is a photolithographically patterned spring. 70. The process of claim 69 further comprising attaching the carrier ring to the wafer carrier. The method of claim 69, wherein Providing a test structure having a bottom, and a plurality of electrical conductors overlying the bottom; Aligning the test structure with the carrier ring such that the plurality of electrical conductors lying on the top surface of the test structure are aligned with the plurality of electrical connections on the connector side of the substrate; And Moving the aligned test structure and the carrier ring such that the aligned plurality of electrical conductors lying on the bottom of the test structure contact the aligned plurality of electrical connections on the connector face of the substrate. Process comprising more. 78. The process of claim 77, wherein said alignment between said test structure and said carrier ring is a mechanical alignment.