KR20020025558A - Multi-layer PCB manufacturing process - Google Patents
Multi-layer PCB manufacturing process Download PDFInfo
- Publication number
- KR20020025558A KR20020025558A KR1020000057467A KR20000057467A KR20020025558A KR 20020025558 A KR20020025558 A KR 20020025558A KR 1020000057467 A KR1020000057467 A KR 1020000057467A KR 20000057467 A KR20000057467 A KR 20000057467A KR 20020025558 A KR20020025558 A KR 20020025558A
- Authority
- KR
- South Korea
- Prior art keywords
- printed circuit
- circuit board
- multilayer printed
- copper foil
- layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09136—Means for correcting warpage
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
본 발명은 다층 인쇄회로기판의 제조방법에 관한 것으로, 좀더 상세하게는 다층 인쇄회로기판 제조시 발생되는 다층 인쇄회로기판의 휨현상을 방지할 수 있는 다층 인쇄회로기판의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a multilayer printed circuit board, and more particularly, to a method for manufacturing a multilayer printed circuit board which can prevent warpage of a multilayer printed circuit board generated when the multilayer printed circuit board is manufactured.
일반적으로, 다층 인쇄회로기판은 에폭시계의 절연기판상에 동박을 입힌 것으로, 단면 다층 인쇄회로기판, 양면 다층 인쇄회로기판 및, 다층 다층 인쇄회로기판등으로 그 종류를 구분할 수 있다.In general, a multilayer printed circuit board is coated with copper foil on an epoxy-based insulated substrate, and may be classified into a single-sided multilayer printed circuit board, a double-sided multilayer printed circuit board, and a multilayered multilayer printed circuit board.
상기 단면 다층 인쇄회로기판은 절연기판의 한쪽면에만 배선패턴의 동박이 입혀진 구조로 되어 있고, 상기 양면 다층 인쇄회로기판은 절연기판의 양쪽면에 배선패턴의 동박이 입혀진 구조로 되어 있으며, 상기 다층 다층 인쇄회로기판은 상기 단면 다층 인쇄회로기판 또는 양면 다층 인쇄회로기판이 다수개 적층된 구조로 되어 있다.The single-sided multilayer printed circuit board has a structure in which copper foil of a wiring pattern is coated on only one side of the insulated substrate, and the double-sided multilayer printed circuit board has a structure in which copper foil of a wiring pattern is coated on both sides of the insulated substrate. The multilayer printed circuit board has a structure in which a plurality of single-sided multilayer printed circuit boards or double-sided multilayer printed circuit boards are stacked.
이때, 상기와 같은 다층 인쇄회로기판 어레이는 도 1에 도시된 바와 같이, 다수의 다층 인쇄회로기판(1-1∼1-N)이 다층 인쇄회로기판(1-1∼1-N)과 일체로 형성된, 즉 다층 인쇄회로기판(1-1∼1-N)의 절연층과 동일한 재질의 가이드바(2)에 지지된 채로 제조되며, 상기 다층 인쇄회로기판 어레이가 하나의 워크패널상에서 다수개 형성된 채로 제조되고 있다.In this case, as shown in FIG. 1, the multilayer printed circuit board array includes a plurality of multilayer printed circuit boards 1-1 to 1 -N integrated with the multilayer printed circuit boards 1-1 to 1 -N. It is manufactured while being supported on the guide bar (2) of the same material as the insulating layer of the multilayer printed circuit board (1-1 to 1-N), the plurality of multilayer printed circuit board array on one work panel It is being produced.
그러나, 상기와 같은 다층 인쇄회로기판은 다층 인쇄회로기판의 각 절연층에 부착되는 동박의 잔존률이 다름에 따라 다층 인쇄회로기판 제조시 다층 인쇄회로기판의 휨현상이 발생되는 문제점이 있었다.However, the multilayer printed circuit board as described above has a problem in that bending of the multilayer printed circuit board occurs when the multilayer printed circuit board is manufactured due to different residual rates of the copper foils attached to the insulating layers of the multilayer printed circuit board.
이에, 본 발명은 상기한 바와 같이 종래의 제 문제점을 해소하기 위해 안출된 것으로, 다층 인쇄회로기판 제조시 발생되는 다층 인쇄회로기판의 휨현상을 방지할 수 있을 뿐만 아니라 다층 인쇄회로기판의 절연층 두께를 균일하게 하는 다층 인쇄회로기판의 제조방법을 제공하는데 그 목적이 있다.Accordingly, the present invention has been made to solve the problems of the prior art as described above, it is possible to prevent the bending phenomenon of the multilayer printed circuit board generated during the manufacturing of the multilayer printed circuit board as well as the insulation layer thickness of the multilayer printed circuit board. It is an object of the present invention to provide a method for manufacturing a multilayer printed circuit board having a uniform thickness.
이와 같은 목적을 달성하기 위한 본 발명에 따른 다층 인쇄회로기판의 제조방법은, 다층 인쇄회로기판의 중앙층을 기준으로 서로 대응하는 양측의 층별 동박잔존율이 균일해지도록 다층 인쇄회로기판을 제외한 워크패널 영역에 동박을 형성하는 것을 특징으로 한다.In order to achieve the above object, a method of manufacturing a multilayer printed circuit board according to the present invention includes a workpiece except a multilayer printed circuit board such that copper foil residual ratios of both layers corresponding to each other are uniform based on the center layer of the multilayer printed circuit board. Copper foil is formed in a panel area | region.
또한, 바람직하게는 상기 다층 인쇄회로기판의 중앙층을 기준으로 서로 대응하는 양측의 층별 동박 잔존율이 균일해지도록 가이드바에 동박을 형성하는 것을 특징으로 한다.In addition, preferably, the copper foil is formed on the guide bar so that the remaining copper foil rate of each layer corresponding to each other on the basis of the center layer of the multilayer printed circuit board is uniform.
도 1은 종래 기술에 따른 다층 인쇄회로기판 어레이의 개략도,1 is a schematic diagram of a multilayer printed circuit board array according to the prior art;
도 2는 본 발명에 따른 다층 인쇄회로기판 어레이의 개략도이다.2 is a schematic diagram of a multilayer printed circuit board array in accordance with the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for main parts of the drawings>
10 : 인쇄회로기판 어레이 10-1∼10-N : 다층 인쇄회로기판10: printed circuit board array 10-1 to 10-N: multilayer printed circuit board
12 : 가이드바 14 : 동박12: guide bar 14: copper foil
20 : 워크패널20: Work Panel
도 2는 본 발명에 따른 다층 인쇄회로기판 어레이의 개략도로서, 다수의 다층 인쇄회로기판 어레이(10)가 하나의 워크패널(20)상에서 제조되고 있고, 상기 각 다층 인쇄회로기판 어레이(10)는 다층 인쇄회로기판(10-1∼10-N)과 일체로 형성된, 즉 다층 인쇄회로기판(10-1∼10-N)의 절연층과 동일한 재질의 가이드바(12)에 의해 지지된 채로 제조되고 있다.2 is a schematic diagram of a multilayer printed circuit board array according to the present invention, in which a plurality of multilayer printed circuit board arrays 10 are manufactured on one work panel 20, and each of the multilayer printed circuit board arrays 10 is Manufactured integrally with the multilayer printed circuit boards 10-1 to 10-N, that is, manufactured while being supported by a guide bar 12 of the same material as the insulating layer of the multilayer printed circuit boards 10-1 to 10-N. It is becoming.
그리고, 상기 가이드바(12)에는 다층 인쇄회로기판(10-1∼10-N)의 중앙층을 기준으로 양측의 동박 잔존율이 균일해지도록 동박(14)이 형성되어 있다.The guide bars 12 are formed with copper foils 14 so that the residual ratio of copper foils on both sides becomes uniform with respect to the center layer of the multilayer printed circuit boards 10-1 to 10 -N.
즉, 다층 인쇄회로기판(10-1∼10-N)의 디자인을 분석하여 다층 인쇄회로기판(10-1∼10-N)의 여러층을 중앙을 중심으로 분류하고, 서로 대응하는 양측의 동박의 잔존률을 파악한 다음 양측의 동박 잔존률이 균형을 이루도록 워크패널(20) 및/또는 가이드바(12) 부분에 동박(14)을 추가 또는 삭제함으로서, 다층 인쇄회로기판의 휨현상을 방지할 수 있을 뿐만 아니라 절연층을 균일하게 할 수 있는 것이다.That is, by analyzing the design of the multilayer printed circuit boards 10-1 to 10-N, the layers of the multilayer printed circuit boards 10-1 to 10-N are classified around the center, and copper foils on both sides corresponding to each other are classified. After determining the residual ratio of the copper foil, the copper foil 14 is added to or removed from the part of the work panel 20 and / or the guide bar 12 to balance the copper foil remaining ratios of both sides, thereby preventing warpage of the multilayer printed circuit board. In addition, the insulating layer can be made uniform.
이상에서 설명한 바와 같이 본 발명에 따르면, 다층 인쇄회로기판 제조시 발생되는 다층 인쇄회로기판의 휨현상을 방지할 수 있을 뿐만 아니라 다층 인쇄회로기판의 절연층 두께를 균일하게 하는 효과가 있다.As described above, according to the present invention, it is possible to prevent warpage of the multilayer printed circuit board generated when the multilayer printed circuit board is manufactured, and to have an uniform thickness of the insulating layer of the multilayer printed circuit board.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000057467A KR20020025558A (en) | 2000-09-29 | 2000-09-29 | Multi-layer PCB manufacturing process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000057467A KR20020025558A (en) | 2000-09-29 | 2000-09-29 | Multi-layer PCB manufacturing process |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20020025558A true KR20020025558A (en) | 2002-04-04 |
Family
ID=19691165
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020000057467A KR20020025558A (en) | 2000-09-29 | 2000-09-29 | Multi-layer PCB manufacturing process |
Country Status (1)
| Country | Link |
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| KR (1) | KR20020025558A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109121302A (en) * | 2018-09-28 | 2019-01-01 | 广州兴森快捷电路科技有限公司 | Edges of boards design method, the design method of wiring board and the wiring board of wiring board |
| KR20190015901A (en) * | 2017-08-07 | 2019-02-15 | (주) 진성전자 | Manufacturing Method of Printed Circuit Board to Improve Flatness |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR960026283U (en) * | 1994-12-31 | 1996-07-22 | Printed circuit board | |
| JPH1022633A (en) * | 1996-07-01 | 1998-01-23 | Ibiden Co Ltd | Manufacture of multilyaer printed wiring board |
| KR19980010292U (en) * | 1996-08-05 | 1998-05-15 | 배순훈 | PCB with deflection improvement structure |
| KR19980060521U (en) * | 1997-03-12 | 1998-11-05 | 김연혁 | Deflection prevention structure of push back PCB |
| JPH11177191A (en) * | 1997-12-12 | 1999-07-02 | Mitsubishi Electric Corp | Printed circuit board and multi-layer printed circuit board |
| JP2000216543A (en) * | 1999-01-27 | 2000-08-04 | Shin Kobe Electric Mach Co Ltd | Manufacture of multilayered printed wiring board |
-
2000
- 2000-09-29 KR KR1020000057467A patent/KR20020025558A/en not_active Application Discontinuation
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR960026283U (en) * | 1994-12-31 | 1996-07-22 | Printed circuit board | |
| JPH1022633A (en) * | 1996-07-01 | 1998-01-23 | Ibiden Co Ltd | Manufacture of multilyaer printed wiring board |
| KR19980010292U (en) * | 1996-08-05 | 1998-05-15 | 배순훈 | PCB with deflection improvement structure |
| KR19980060521U (en) * | 1997-03-12 | 1998-11-05 | 김연혁 | Deflection prevention structure of push back PCB |
| JPH11177191A (en) * | 1997-12-12 | 1999-07-02 | Mitsubishi Electric Corp | Printed circuit board and multi-layer printed circuit board |
| JP2000216543A (en) * | 1999-01-27 | 2000-08-04 | Shin Kobe Electric Mach Co Ltd | Manufacture of multilayered printed wiring board |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20190015901A (en) * | 2017-08-07 | 2019-02-15 | (주) 진성전자 | Manufacturing Method of Printed Circuit Board to Improve Flatness |
| CN109121302A (en) * | 2018-09-28 | 2019-01-01 | 广州兴森快捷电路科技有限公司 | Edges of boards design method, the design method of wiring board and the wiring board of wiring board |
| CN109121302B (en) * | 2018-09-28 | 2020-03-06 | 广州兴森快捷电路科技有限公司 | Circuit board edge design method and circuit board design method |
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| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E601 | Decision to refuse application |