KR20020020862A - Method and apparatus for manipulating address information in a memory tester - Google Patents

Abstract

PURPOSE: A device for managing address information in a memory tester is provided to use any section of a z-address register as a substitute for up to eight most significant bits in x-address lines. CONSTITUTION: A majority of z-selection multiplexers select one of sixteen z-address lines for transfer to a majority of z-bit activation multiplexers. Each z-bit activation multiplexer chooses between a selected z-bit or a matching x-address bit. An Independent claim is also included for a method for manipulating address information in a memory tester.

Description

MEMHOD AND APPARATUS FOR MANIPULATING ADDRESS INFORMATION IN A MEMORY TESTER}

Electronics devices and capabilities are becoming very common in everyday life. In addition to personal computers in the home, many individuals have more than one productivity tools for a variety of different purposes. Most personally produced electronic devices include some form of nonvolatile memory. Cell phones utilize nonvolatile memory to store and maintain phone numbers and configurations programmed by the user when power is turned off. PCMCIA cards utilize nonvolatile memory to store and retain information even when the card is removed from a computer slot. Many other common electronic devices also benefit from the long term storage capability of nonvolatile memory in up-powered assemblies.

Non-volatile memory manufacturers selling to electronic equipment manufacturers need testers to test and verify the proper operation of the memory they produce. Due to the capacity of nonvolatile memory that is constantly being manufactured and sold at a low price, it is very important to minimize the time taken to test a single component. Buyers of non-volatile memory can save money by combining the memory device into a more costly assembly with minimal or no testing, which will allow memory manufacturers to provide high shipment yields. Requires. Thus, the memory test process should be efficient enough to identify a large proportion of nonconforming parts and preferably the entire nonconforming part by a single test process.

As nonvolatile memory grows larger, denser and more complex, testers must be able to process the increased size and complexity without significantly increasing the time it takes to test. As memory evolves and improves, testers must be able to easily accept changes made to the device. Another specific problem with testing nonvolatile memory is that repeated writing to the memory cell degrades performance for the entire lifetime of the part. Nonvolatile memory manufacturers address many test problems by forming special test modes for memory devices. This test mode is not used at all by the purchaser of the memory and can be accessed by the memory manufacturer to test all or a significant portion of the memory as efficiently as possible for as little time as possible. Some nonvolatile memory can also be repaired during the test process. The tester must therefore be able to identify the repair request, the location of the repair, the type of repair required, and be able to perform the appropriate repair. Such repair processes require testers that can detect and isolate specific noncompliant parts of the memory. In order to take full advantage of the special test modes and repair functions, it is desirable for the tester to be able to run a test program that supports conditional branching based on the expected response from the device.

Conceptually, the memory test procedure is an algorithmic process. By way of example, a typical test involves writing zero or one for a memory cell while sequentially incrementing or decreasing the memory address. The term "vector" refers to a collection of ones and zeros that are written or read during a memory cycle, while the term "pattern" typically refers to a sequence of vectors. Testing includes writing patterns such as checkerboards, walking 1's and butterfly patterns over memory space. Test developers, with the help of algorithmic constructs, can more easily and efficiently create programs that form these patterns. Algorithmically coherent test patterns are also easier to debug and use a logical method of separating parts of the pattern that do not perform as expected. Test patterns that are algorithmically generated using instructions and commands repeated in programming loops consume less space in tester memory. Therefore, it is desirable to have a test pattern generation capability by an algorithm in a memory tester.

Accurate signal edge placement and detection should also be considered in the efficiency of the nonvolatile tester. In order to capture a portion that does not conform within the specified margin but generally matches the median, the nonvolatile memory tester must be able to accurately place each signal edge in time relative to another signal edge. . It is also important to be able to accurately measure the time point at which the edge is received. Thus, the nonvolatile memory tester must have sufficient control and flexibility over the timing and placement of the stimulus and the response from the device under test (DUT) (memory) thereto.

The memory tester is said to generate a transmit vector (stimulus) applied to the DUT and receive a vector (response) that is expected to be returned. Algorithmic logic for generating these vectors can generally do so without having to worry about how a particular bit in the vector is obtained from or reached for a particular signal pad in the DUT. At this level it is assumed that it is a given fact that adjacent bits in the vector will end up as physically adjacent signals on the DUT. Unfortunately this is not the case.

In practice, the correspondence between the bits in the vector at the "conceptual level" and the actual signal at the DUT tends to be arbitrary. If no action is taken to avoid this, it will be necessary to cross one or more probe wires from the peripheral device in contact with the DUT. Since such crossings are mostly undesirable, we incorporate a mapping mechanism in the path of the transmit vector to relocate its transmit bit position before the bit in the transmit vector is applied to the DUT, so that physical contact operations support the burden of the cross. It is common to not let. Correspondingly, the reverse mapping mechanism is applied to vector reception, and these vectors are then considered. As a result, algorithmic vector generation and comparison mechanisms can ignore this entire problem. As another example that such a mapper and reverse mapper can perform, consider the case where other DUTs of the same type are being placed on the same wafer, but with rotation or some mirror reflective symmetry to avoid wasting space on the wafer. Please see. This method also affects the correspondence between the vector bit position and the physical signal position, but it can be hidden by proper mapping or demapping. It will be appreciated that the mapping and demapping required in this situation, once identified for a particular DUT, is static and therefore does not require a change in the testing process for that particular DUT.

For certain types of memory, efficient testing requires that each address line bit group be manipulated separately from other address line bit groups. In prior art testers without algorithmic pattern generation, the task is relatively simple and the address lines are defined in two separate groups and managed on a bit for bit basis. One example of a type of memory using such address alignment is the number of memory cells in the page addressing format, where page addressing uses some of the most significant bits of the address lines and memory word addressing uses some of the least significant bits of the address lines. Memory that maintains the block structure. However, in order to take full advantage of algorithmic pattern generation for testing these types of memory, it is necessary for the tester to provide a simple solution to selectively group bits in the address line for independent algorithmic pattern generation.

According to one aspect of the invention, an apparatus for managing an address channel in a memory tester includes one or more addresses storing a plurality of logical address bits and a plurality of replacement bits (each replacement bit corresponding to one logical address bit). Contains registers The apparatus also has a bit selector for each logical address bit and replacement bit combination and each bit selector independently selects a logical address bit or a replacement bit. The output set of the bit selector is a valid address used for memory testing. The vector processor applies a valid address at the tester.

According to another aspect of the invention, a method for managing an address channel in a memory tester comprises a plurality of logical addresses for each of the plurality of bit selectors having one logical address bit per bit selector and one replacement bit per bit selector. Delivering the bits. The method selects a logical address bit or a replacement bit, and the output set of that bit selector becomes a valid address. The effective address is used to address the DUT memory.

Preferably, testers in accordance with the principles of the present invention provide additional flexibility and efficiency in developing test patterns over prior art testers.

1 is a schematic block diagram illustrating an extended reconfigurable nonvolatile memory tester according to the present invention;

2 is an enlarged schematic block diagram of the DUT tester of FIG. 1;

3 is a block diagram showing the address mapper 29 shown in FIG.

4 is a block diagram showing an X scrambled portion 302 of the address mapper 29 shown in FIG.

FIG. 5 is a block diagram showing a Z scrambled portion 306 of the address mapper 29 shown in FIG.

Explanation of symbols for the main parts of the drawings

2: test system controller 4: test site controller

5: test site bus 6: DUT tester

9 pin electronic device 14 DUT

1, there is shown a schematic block diagram 1 of a nonvolatile memory test system constructed in accordance with the principles of the present invention. In particular, the illustrated system can test simultaneously on each of 64 large number of test points, up to 36 individual DUTs, and an element of a set of test resources to test a DUT having more than 64 test points. Provide a reconstruction that allows them to be bonded together. These test points may have some locations on the integrated circuit wafer that are not yet diced and packaged, or may be pins of packaged components. The term "test point" refers to an electrical location where a signal (eg, power supply, clock, data input) can be applied or a signal (eg, data output) can be measured. We will follow industry practice to refer to test points as "channels." The aforementioned "collection of test resources to be bonded together" can be understood to be as many as 36 test sites, each of which is a test site controller (4), (64 channels) DUT tester (6). ) And a collection of (64 channels) pin electronics that make actual electrical connections to the DUT 14. If a DUT test requires 64 or fewer channels, one single test site is sufficient to perform a test on that DUT, that is, for example, test site # 1 (shown in FIG. 1). Is formed and operates as a single site test station. On the other hand, if any of the forms of reconfiguration described above are valid, two (or more) test sites are bonded to one another and have one larger channel having 128 channels. It functions as an equivalent test site, therefore, referring again to the example shown in Fig. 1, the so-called test sites # 35 and # 36 form a "two-site test station".

In simple terms, don't assume that the entire test site should test a single DUT, or that a single test site can only test one single DUT. Assume that a wafer has two (possibly, but not necessarily, a die) and the sum of its test channel requests is 64 channels or less. Both DUTs can be tested by a single test site. What makes this possible is the general purpose programmability of each test site. A test program executed by a test site may be written such that another portion is used to test another DUT while a portion of the test site resource is used to test one of the DUTs. After all, if you have a third DUT, which is the first two logical unions, you can test that third DUT with a single test site, thus testing similarly the so-called "component DUTs". You should be able to. The only difference is that, for the "third" DUT, the two "component DUTs" are tracked separately (ie, the third DUT) as opposed to the integrated answer. There is a question as to which part of the code is rejected). While this "single-site multi-test station" capability is close to the prior art, it is discussed here for clarity and to avoid potential confusion and misunderstandings that may arise when comparing the concept of bonding two or more test sites together. It is.

Without this concept of reconfiguration, there would be no difference between the test site and the test station, and one of the terms would not be necessary. In fact, however, it will be readily appreciated that the number of test stations need not be the same as the number of test sites. In the past, because the test sites were split to create more test stations (the DUT was not complex enough to use the entire test site), their numbers may have been different. However, the difference can now also be attributed to the test site, where the test sites are bonded to each other to form a multi-site test station (the DUT is too complex to process into a single test site).

Then, the test system controller 2 is followed by the system bus 3 to as many as 36 test site controllers (names ending in suffixes # 1 to suffixes # 36) 4a-4z. Connected. (It's true that there are only 26 subscripts up to az and not 36. However, despite these discrepancies, using numeric reference characters rather than appending numeric subscripts (which can potentially be very complex) It appears desirable.) The test system controller 2 is a computer (e.g., a PC running NT) that runs a suitable test system control program that includes the task of testing the nonvolatile memory. Test system control programs represent the abstraction or abstraction that exists at the highest level when hierarchically dividing tasks (and complexity) to achieve desirable tests. The test system controller determines not only which programs are running at different test sites, but which programs also examine robotic systems (not shown) that change the DUT and test probes as needed. The test system controller 2 can function in a way that supports the concept that some test sites are programmed to perform as single-site test stations, while others are bonded to one another to form a multi-site test station. Clearly, in such an environment, there are different parts to be tested, and it is most desirable that different tests be performed on different parts. Similarly, not all single-site test stations require testing of the same type of components, and none of them require multiple-site test stations. Thus, the test system controller 2 is programmed to issue a command to achieve the required test site bonding and then call the appropriate test program to be used at the various test stations. The test system controller 2 can also receive information about the results obtained from the test and take appropriate action to discard the wrong parts and perform various analyzes that can be used to control the production process in the so-called factory setup. A log can be maintained.

The test system itself is a fairly large and complex system, and the robot is used to load wafers in a stage where one or more future dies (wafers are not yet diced) are sequentially placed under a probe connected to Pin Electronics 9. It is common to use a subsystem where the future die (wafer is not yet diced) is tested. The test system may also be used to test package components loaded on a suitable carrier. Regardless of how many test sites are used to form the test station, or how many test stations are on the test site, there is at least one test site controller used in connection with each test station (as described below). There will be. The test site controller may be an Intel i960 processor with 36 to 64 MB of program and data-coupled memory running a dedicated operating system called VersaTest O / S (VOS) as an embedded system, to test nonvolatile memory. It has also been used in previous products (eg, Agilent V1300 or V3300). At first, only the situation of a single-site test station is considered. For clarity, assume that test site # 1 functions as test station # 1 to test WHIZCO component no.0013. The test pattern changes hundreds of different types of tests (voltage level, pulse width, edge position, delay, and large scale simple storage and detection of selected information patterns). Each type of test involves millions of individual memory cycles per DUT. At the highest level, the operator of the test system instructs the test system controller 2 to start testing WHIZCO 0013 using the test station # 1. In turn, the test system controller 2 instructs the test site controller # 1 (4a) (which is a built-in [computer] system) to execute a related program, that is, TEST_WHIZ_13. If the program is already available in the test site controller (# 1) environment, simply run it. If not, the program is supplied by the test system controller 2.

In principle, the program TEST_WHIZ_13 may be self-contained. If so, however, it will most likely be quite large, allowing the processor of the embedded system in the test site controller 4a to run at a constant speed, from one DUT memory cycle to the next, sufficiently fast to run the test at the desired speed. It can be very difficult. The low level subroutine type operation of generating the address sequence and associated data to be expected from the write sequence or read operation is generated by a programmable algorithmic mechanism located within the DUT test 6 as needed, but this is a test site controller. It operates in synchrony with the program executed by the embedded system in (4). Think of this as exporting certain low-level subroutine-like activity and initiating DUT memory cycles to a mechanism closer to the hardware environment of the DUT 14 (DUT tester). . Generally speaking, whenever test system controller 2 has a test program for a test site controller, the appropriate low-level implementation routines needed to achieve the overall operation required for programming or test site controller programming. Supply the relevant DUT tester (perhaps a memory-specific routine to be tested). Low-level implementation routines are termed "patterns" and are generally named (as in functions and variables in high-level programming languages).

Each test site controller (#n) 4 is connected to its associated DUT tester (#n) 6 by a site test bus (#n) 5. The tester site controller uses the site test bus to control the operation of the DUT tester and to receive information about the test results therefrom. The DUT tester can generate various DUT memory cycles related to the test type at high speed, and determine whether the result of the "read" memory cycle is as expected. In fact, it responds to (ie executes a corresponding pattern) an instruction or an operation instruction (called a pattern) sent from the test site controller by initiating a corresponding useful sequence of read and write DUT memory cycles. Conceptually, the output of the DUT tester 6 is the stimulus information to be applied to the DUT, and also receives response information therefrom. This stimulus / response information 7a passes between the DUT tester 6a and the pin electronic device # 1 assembly 9a. The pin electronics assembly 9a supports up to 64 probes that can be applied to the DUT 14.

The foregoing stimulus information is a sequence of parallel bit patterns (ie, a sequence of "transmit vector" and expected "receive vector") expressed in accordance with the voltage level of a given group of logic devices used in the DUT tester. There is a configurable mapping between the bit position in the stimulus / response and the probe on the die, which mapping is understood by the DUT tester 6. Individual bits are correct with respect to their timing and edge position, but may require voltage level shifting until they can be applied to the DUT in addition to the mapping. Similarly, the response that occurs at the DUT following the stimulus may need to be buffered and (inverted) level shifted before being input back to the DUT tester. This level shifting operation is the responsibility of the pin electronics 9a. The pin electronics configuration required to test WHIZCO 0013 will not be valid for testing components from ACMIE, perhaps even for other WHIZ components. Therefore, it will be appreciated that the pin electronics assembly requires that it also be configurable (such configurability being a function of the PE Config line 8a).

This concludes the brief structural overview of how a single test site is configured for DUT testing. Now let's discuss the problems that can arise if there are many test sites that will work. As a preparation step, a preferred embodiment of constructing a test system having a plurality of test sites will be described. In many respects, some of the information now being described is a matter of choice based on market research of customer preference and cost benefit analysis. In any case, certain choices must be made to make up one of these, and once a selection is made, specific results are evident throughout the entire system. At least in general, it would be useful to provide a more overview of the hardware characteristics of the test system. Although some of these features are by chance, knowing these features will nevertheless help to understand the various examples used to illustrate the invention.

Start by considering four rather large card cages. Each card cage, in addition to power supplies and water cooling (in a clean room environment, fans can be a source of contamination), the motherboard, the front plane and the back It has a back plane. Up to nine assemblies can be placed for each card cage. Each assembly includes a test site controller, a DUT tester and a pin electronic device. A general overview of how test site controllers are bonded to each other will be described, which will involve several buses used to create daisy chains.

We will briefly explain the term "daisy chain" from the main text. Consider the system elements A, B, C and D. Assume that they must be daisy chained in that order. There is an information and control path from A to B, then B can selectively forward traffic from B to C, then C can selectively forward traffic from C to D have. This same kind of device may also exist with respect to traffic in the opposite direction. Daisy chains are often used to create priority schemes. We will use them to create a master / slave relationship between the various test site controllers. These daisy chain type communication devices will be denoted by the suffix "DSY" instead of "BUS". Therefore, we will say instruction / data DSY instead of instruction / data bus. The concept of "input to B and optionally delivered" may imply that traffic must be replicated onto a separate set of conductors before it can be delivered. Such a method may be more similar to a regular bus with an addressable entity if not for performance reasons. By virtue of the programmable address mapping device and the ability of some of the downstream test site controllers to be in a "to sleep" state, a single bus can be logically configured to look (i.e. function so) as multiple daisy chains. have. After all, daisy chains are high-performance paths for command and control information, and if not, you cannot expect the master / slave combination (multi-site test station) to run as fast as a single test site. For the benefit of daisy chain performance, the various DSYs do not leave their respective card cages. The effect of this decision allows you to set limits on what test sites can be bonded to each other (and how many test sites can be bonded to each other). In principle, these limitations are not necessarily required, nor are related (in such cases) technically impractical. However, since there are already nine test sites in the card cage, expanding the DSY seems to add too much additional cost for its relatively small advantage.

Resuming the discussion of FIG. 1, consider various test site controllers 4a-4z in four card cages (each card cage has nine test site controllers). These are denoted by reference numbers 4a-4f, 4g-4m, 4n-4t, and 4u-4z. (As mentioned earlier, these are only nominal 26 subscripts-the reader should think that there will be another 10 subscript symbols somewhere-no need to be careful.) CMD / DAT DSY (17a) And data daisy chain) interconnect test site controllers 4a-4f in one card cage, while another CMD / DAT DSY 17b interconnects test site controllers 4g-4m in another card cage. Connect. The same device, test site controller 4n-4t and test site controller 4u-4z also exist for the remaining card cages, respectively. It has been described earlier that the DSY does not leave the card cage, and the "tail end" of the bus that actually forms the DSY is the head of the next segment in another card cage without leaving the card cage. Instead, the system bus 3 from the test system controller 2 is connected to the entire test site controller, each of which can be a master at the head of the DSY segment without leaving the card cage.

The CMD / DAT DSYs 17a-17d discussed so far exist between the various test site controllers 4a-4z. Similar devices exist for the SYNC / ERR DSY 18a-18d and the DYT tester 6a-6z. The synchronization and error information carried by the SYNC / ERR DSY 18 allows the DUT testers to operate in unison. These two daisy chains 17 and 18 carry slightly different types of information, but each exists as part of the same general mechanism for bonding one or more test sites together to one test station.

Referring now to FIG. 2, a simplified extended block diagram of the DUT tester of FIG. 1 is shown (there may be up to 36). It is enough to explain only that one case. At first glance, you will feel quite dense. Some shown in the block diagram in the DUT tester 6 are quite functionally complex and not available in an "off the shelf" form. It is important to point out two points here. First, the main purpose of including FIG. 2 in the figures is to describe the basic characteristics of the critical operating environment within the overall nonvolatile memory test system 1. The invention, which is fully described by FIG. 3 and the subsequent figures, may be an extension of the mechanism beginning in the following description of FIG. 2 or a new mechanism to which motivation is provided from FIG. Either way, it is not known exactly which of these is in front of the reader in writing this specification. The present goal is to provide a simplified and informative starting point for the extensive details of the various preferred embodiments which follow, so that each of the following descriptions will be appropriately concise (one describing everything with respect to each of the different inventions). So that it does not become a "jumbo" statement). Second, an enlarged or expanded element may generally include information that is generally consistent with FIG. 2 but not exactly “match-up” to the simplified version of FIG. 2. This does not mean that there are errors or that they are fatally inconsistent, which sometimes occurs because it is difficult or impossible to simplify something and present its exact image in miniature. This situation is similar to a map. The full-size Colorado map will show that if you head east on I-70, you can head north along Denver I-25. This looks like a left turn. And this was actually a left turn in the past but not now, and a detailed map of the intersection will show the range between the series of turns. But no one can say that the standard size map is wrong, and it is correct at the level of abstraction or reduction. Similarly, and despite its fairly complex appearance, FIG. 2 is a simple operation that actually works with a medium level of abstraction or attenuation, although some apparent left turns are not simply left turns at all.

As shown in FIG. 1, the main input to the DUT tester 6 is an example of a test site bus 5, which is a test site controller 4 associated with an example of the DUT tester 6 of interest. From). The test site bus 5 couples with a micro-controller sequencer 19 which may be similar to a special purpose microprocessor. The test site bus 5 may be from a program stored in a program memory, which may be either inside the micro-controller sequencer 19 (PGM SRAM 20) or outside the micro-controller sequencer 19 (EXT. DRAM 21). Fetch the command of These two memories are addressed by being essentially a logical common address 63 (or instruction fetch address) that serves as a program counter and either of the two memories can be the source of programming to be performed, but (1) It should be noted that only one performs an instruction fetch memory cycle for any period of time and (2) the two memories are actually addressed by electrically different signals. SRAMs are fast and allow true random access, but they consume valuable space in the micro-sequence controller 19 (which is a large IC), so that the size of the SRAMs is limited. External DRAMs can be provided in large, adjustable amounts, but are only fast when accessed in sequential chunks with linear performance and without any branching. Programming SRAM 20, the intensive algorithm, is the most common, but EXT. DRAM 21 is most suitable for elements that are not easily generated by algorithmic processes, such as initialization routines and random or irregular data.

The instruction word carried by the micro-controller sequencer 19 is quite long, ie 208 bits. The instruction word consists of 13 16-bit fields. These fields often indicate fetch command information about mechanisms outside the normal micro-controller sequencer. This field is dedicated to the mechanism associated with it. One set of ALU instructions 22 is provided for a collection of eight 16-bit ALUs 24, and another set of ALU instructions is distributed to various other mechanisms distributed throughout the DUT tester. "Various Control Values & Commands" 42 Legends and lines indicate this latter case.

Each of the eight 16-bit ALUs 24 has a typical repertoire of arithmetic instructions built around its associated 16-bit result register (each ALU also has several different registers). Three of these result registers and the ALUs associated with the three registers are for generating the X, Y, and Z address components 27 which are variously combined into a complete address to be provided to the DUT. The algorithm of the 32-bit data pattern 28 in which two of the eight ALU / registers (DH & DL) or more are divided between the most significant portion (DH) and the least significant portion (DL). It is provided to support creation. The last three ALUs / Registers (A, B, C) are used as counters and contribute to the creation of various program control flags 25 that support program control and branching to complete in some program specified number of iterations or other conditions. . This program control flag 25 is sent back to the micro-controller sequencer 19, in which the flag 25 affects the value of the instruction fetch address as in the microprocessor. There are also various other flags 55 that can be used to affect program branching. This flag 55 is associated with various other mechanisms in the DUT tester 6 controlled by different fields of the fetch instruction word. One particular additional flag is explicitly shown as a separate item, VEC_FIFO_FULL 26. In other figures with less detail, this one particular additional flag may be combined with the other flags 55. It is intended herein to facilitate the description of one aspect of the micro-controller sequencer 19 operation by separating one particular additional flag.

What VEC_FIFO_FULL does is to pause (pause) further program execution by the micro-controller sequencer 19. There are many stages of pipeline between the instruction fetched by the micro-controller sequencer 19 and the mechanism for finally handing off the test vectors to be applied to the DUT. In addition, as some of the baggage to be provided to the DUT proceeds forward, some of the baggage accompanying the vector is information about the speed or the respective vector duration of the ultimate vector application. Thus, the speed of the vector application to the DUT need not be constant, and in particular some groups of vectors may take longer to provide than to generate. The micro-controller sequencer only performs programming at its maximum speed. Obviously, however, on average, the speed of "vector consumption" should be equal to the speed of "vector generation" so that the pipeline almost does not have to be jagged like an elastomer. The vector FIFO 45 exists at the output of the address mapper 29 to be described later, and the vector FIFO 45 performs an elastic function in the pipeline. The VEC_FIFO_FULL signal is used to pause the generation of a new vector at the head end of the pipe to avoid exceeding a limited number of steps in the pipeline.

Subsequently, the X, Y, and Z address components 27 (of 48 bits, three times 16 bits) are provided to the address mapper 29, with the output of the address mapper 29 almost random in the ordered 48 bit address space. It is preselected with the reconstructed address value. As a starting point for recognizing this, first assume that the address mapper 29 is a memory that is a full 48-bit address space and holds 48-bit values at each address (don't consider for a moment that this memory will be the size of a large refrigerator today). ). Given this memory, the lookup table can be implemented to map any given address to any other selected 48 bit value that can be used as an alternate address. The reason why such address mapping is desirable is that the X, Y and Z address components have a useful meaning in terms of the particular DUT internal architecture that is most likely not to be implemented with one large linear decoder. The concept of layers, blocks, or pages can be very useful to test engineers, and errors that occur in physically close locations can include corresponding similarities in their X, Y, and Z addresses. Can be useful for correcting these errors at this or design level at the production level, recognizing what is an error, and reprogramming some to avoid the error section behavior as a preliminary section behavior. The first is to reduce the 48 bits to the actual number of bits (32 or 16 bits) to be provided to the DUT. We will briefly mention how to reduce, which is usually a matter of taking some bits from X, some bits from Y, and the rest from Z. Not all, but this is the second problem, which This is because a given address may lie in the circuit with a left-for-right (or left-right and up-down) mirror image of another section of the circuit, because some sequential address value may be placed in the circuit. This has the effect of reconstructing what one bit means in physical order, and this chip layout characteristic can occur many times, and the way in which a group of bits, ie, Y, is interpreted, depends on the accompanying value of some other, ie, Z bits. Naturally, the address mapper 29 is originally provided such that the X, Y and Z addresses are "repackaged" so that the memory has this internal architecture configuration. Let the person to test reflect this type of work To actually do this, the address mapper 29 includes a large number of interconnect multiplexers The address mapper 29 is assumed to be temporary for the sake of explanation. As one can't achieve a completely arbitrary look-up table behavior of a fully populated memory decode scheme. However, the address mapper 29 can reconstruct the sub-fields of the X, Y and Z address components as needed because there is still another mechanism that will reduce the 48 bits to the actual number required. The address mapper 29 also includes three 16-bit (address) lookup tables to perform limited random mapping within the local range.

The mapping address output 30 of the address mapper 29 is provided as an address to the Aux RAM 31 and the error catch RAM 32. The Aux RAM 31 and the error catch RAM 32 perform separate functions but It can be implemented as a selectable part of the whole RAM that is large of. The mapping address output 30 is also provided as an input to an address bit select circuit 37 which will be described later.

Consider Aux RAM 31. The function of the Aux RAM 31 is to hold a data pattern 33 and an address 34 that can be provided to the DUT. Data pattern 33 and address 34 are logically separate outputs from Aux RAM 31, because data pattern 33 and address 34 are processed somewhat differently and used in different places ( The Aux RAM 31 is not a dual "port memory," but preferably it is several banks whose output is provided to the multiplexer). In such an implementation, the store data 33 may be stored in one bank or range of Aux RAM 31 addresses, and the store address 34 may be stored in another bank or range of Aux Ram 31. Furthermore, we do not show an explicit mechanism for writing to the Aux RAM 31. This is accomplished by the addressing bus operation initiated by the test site controller 4 in the executing program instruction (the "utility service" bus, referred to as "under the floorboards", ie "ring buses," going to almost all parts in FIG. 2). (Not shown because of the complexity of the drawings).

The error catch RAM 32 is addressed to the same address provided to the Aux RAM 31, and the error catch RAM 32 stores or retrieves information about the error, which operation is combined with a post decode circuit described below. Is performed. As with paths 33 and 34 from Aux RAM 31, path 61 (to error catch RAM) and path 62 (from error catch RAM) are distributed by a ring bus (not shown). The multiplexed output from the multi-bank memory (error catch RAM 32) is preferred in accordance with the configuration information.

The data multiplexer 35 has as inputs the stored data output 33 from the Aux RAM 31 as well as the data 28 from the registers DH and DL in the collection 24 of the ALU. The data multiplexer 35 selects which of these inputs 28, 32 to provide to its output 38, which output 38 transmits to the transmit vector mapper / serial converter / receive vector comparison data circuit 40. It is provided as one of two vector components (the other component is the output 39 of the address bit select circuit 37). The circuit 40 assembles three functions, the ordered logical representation of the entire vector to be provided (transmitted) to the DUT, and the ordered bits of the transmitted vector logic representation and this signal (i.e., Apply a random dynamic correspondence (mapping) between the actual physical channel numbers of the pin electronics (i.e., any probe tip) to contact the DUT instead of the bits in this vector, and work with the compiler to Splitting into pieces that will be provided separately and in order). Which of these functions is performed is determined by the control signal from the SRAM 41 that is also addressed according to the field in the 208-bit instruction fetched by the micro-controller sequencer 19. The output of the circuit 40 amounts to a 64-bit vector 44 to be provided to the vector FIFO 45 which completely generates the VEC_FIFO_FULL signal 26, the meaning and use of the VEC_FIFO_FULL signal 26 described above. The upper vector of the vector FIFO 45 is removed from the vector FIFO 45 upon receipt of the VEC_FIFO_UNLOAD signal 47 occurring in the period generator 49 (to be described briefly). This removal vector 46 is provided to the timing / formatting and comparing circuit 52 that is connected to the DUT via the associated operation of the pin electronics 9. That is, each operation of the pin electronic device 9 receives the transmit & receive vector 7 and the pin electronic device configuration information 8 from the timing / formatting and comparing circuit 52 associated with the pin electronic device 9. .

The timing / formatting and comparing circuit 52 has an internal SRAM 54 addressed by the same command address (“A inside the circle”) as in the program SRAM 20 of the micro-controller sequencer 19 (external DRAM 53 may be used in place of internal SRAM 54. Internal SRAM 54 (or external DRAM 53) supports the generation of drive and compare cycles. The drive cycle provides the transmission vector to the DUT. The comparison cycle receives the vector provided by the DUT and examines it to determine if it matches the previously provided comparison data. Both drive cycles and comparison cycles can be adjusted as to their duration, whether a load is applied and when the data is latched or strobe. The above-described comparison produces a 64-bit value 56 provided to the receive vector demapper / serial converter 57, which can be thought of as a logical inversion of circuit 40 (circuit 40). The operation of 57 is controlled by the SRAM 58 in response to the control of the circuit 40 by the SRAM 41). The output 59 of the circuit 57 is then provided to the post decode circuit 60. The post decode circuit 60 checks both the input error information 59 and the (previous) stored error information 60 (stored in the error catch RAM) via the program standard and later via the path 61 the error catch RAM ( It is possible to generate compressed and easily interpretable error information to be stored back. As one example, information may be generated about how many times an error exists within a particular range of addresses, which may be useful in determining when to attempt an on-chip repair by driving an alternate circuit.

The period generator 49 and its associated timing SRAM 51 will now be described. The period generator 49 and the timing SRAM 51 have 8 bits that determine the duration for the associated operation of the timing / formatting and comparing circuit 52 for each 208 bit instruction fetched by the micro-controller sequencer 19. In response to the signal T_SEL 43. T_SEL 43 is a member of the command 42 and the various control values represented by the different fields in the fetch command. The T_SEL 43 may indicate or encode 256 different cases with 8-bit values. In this case, these "cases" are 28-bit values stored in timing SRAM 51 and addressed by T_SEL. Each addressed 28-bit value 23 specifies the desired duration with 19.5 picosecond resolution. The sequence of accessed 28-bit duration values 23 is stored in the periodic FIFO 50 so that individual members of the sequence can be retrieved and provided concurrently with the retrieval of the destination corresponding vector stored in the vector FIFO 45.

The coarse timing value field in the first entry in FIFO 50 carries duration information with a resolution of 5 nsec and from this information to the timing / formatting and comparison circuit 52 for subsequent transmission vectors from vector FIFO 45. Generate a VEC_FIFO_UNLOAD signal 47 to transmit. A comparison signal timing reminder 48 is also provided to the circuit 52 in which the final 19.5 picosecond resolution is achieved.

Some memory consists of multiple blocks of memory that are duplicated on a single die to make up the entire memory space in the memory device. In such cases often, the duplicated block is a mirror image across the longitudinal or horizontal axis, or both, and the duplicated block can also be further replicated. Often it is effective to construct a single test for one memory block and iterate over the duplicated block. While the test pattern is related to each block, it is not possible to simply reuse a single test for the entire memory block because the memory blocks are images of each other. Thus, the duplicated block affects testing for devices whose address bits follow a different sequence for each block. However, different sequences are related to each other. The scramble feature only allows the test developer to reuse test patterns for different memory blocks by programming only the scramble feature. The test pattern itself is reused, and a scramble function that is algorithmically distinct from the test pattern program instructions performs the administrative responsibility for adapting the test pattern for each replicated memory block. Some memory is also organized in pages. The page is addressed using a predetermined subset of address bits. The scramble function is enhanced by performing algorithmic control of certain bits separately from other address lines and allows replacement of those bits for regular address bits that are input into the scramble function. Referring specifically to FIG. 3, each of the X scramble 302, Y scramble 304, and Z scramble 306 blocks each receive a 16-bit address from the address X, address Y, and address Z ALU registers 24, respectively. A mid-level detail of the address mapper 29 shown in FIG. 2 is shown. Thus, the 48 address lines, shown at 27 in FIG. 2, are divided into three groups of 16-bit logical address lines in FIG. X scrambled, Y scrambled, and Z scrambled blocks 302, 304, 306 also receive information initiated in the APG register. Programmability of the APG registers provides a programmable feature of the tester function. The value of each APG register is stored and downloaded to the test pattern as part of the compiled object code, providing an initial value before executing the test pattern. It is also possible, although not common, to change the value in some of the APG registers during test pattern execution. There are a large number of AGP registers in the tester and only some of the registers related to the present invention are described herein. The APG register associated with the X scramble block 302 includes the APG_XSCR_JAM_MASK [0:15] register 308, the APG_XSCR_JAM_ADDR [0:15] register 310, bit 2 of the APG_XYZ_SCR_EN register 312, and APG_XSCR_Z_EN [0: 7] register 314, and APG_XSCR_Z_BITS_L [0:15] and APG_XSCR_Z_BITS_U [0:15] register 316. The APG register associated with the Y scramble block 304 includes the APG_YSCR_JAM_MASK [0:15] register 318, the APG_YSCR_JAM_ADDR [0:15] register 320, bit 1 of the APG_XYZ_SCR_EN register 312, and APG_YSCR_Z_EN [0: 7]. Register 322 and the APG_YSCR_Z_BITS_L [0:15] and APG_YSCR_Z_BITS_U [0:15] registers 324. The APG register associated with the Z scramble block 306 includes the APG_ZSCR_JAM_MASK [0:15] register 326, the APG_ZSCR_JAM_ADDR [0:15] register 328, and bit 0 of the APG_XYZ_SCR_EN register 312. The X scrambled, Y scrambled, and Z scrambled blocks 302, 304, and 306 perform mapping functions and three sets of outputs output 16 bits of real address information 330 to the programmable delay logic 332. Programmable delay logic 332 functions to enable a test developer to program a latency between address information about the DUT and DUT transmission or response data information. Programmable latency logic 332 outputs 48 cycle delay adjusted address lines 334 that are input to auxiliary RAM 31.

Referring specifically to FIG. 4 of the drawing, a Z-bit replacement and jamming logic stage, a look-up table, and a disable (between the input and output of the X scramble block 302). A detailed block diagram of an X scramble block 302 with stages is shown. The X scrambled and Y scrambled blocks 302 and 304 are actually the same in terms of structure. Thus, to avoid unnecessary duplication, only the X scramble block 302 is shown and described for the purpose of describing the X scramble and Y scramble blocks 302 and 304. For simplicity of explanation, start with the device on the left of FIG. 4 and proceed to the right.

For the purposes of nominal, the X-address line 27 received from the Address X ALU register 24 is referred to as a logical X-address line 404. The z-bit replacement stage allows the test developer to replace up to eight of the top logical X-address lines 404 with any eight of the sixteen Z-address lines 402. The X, Y, and Z address ALUs 24 are operated separately from each other. Allowing a bit replacement of a portion of the X or Y address line with up to eight Z address lines preferably provides independent operation for two subsets of tester channels dedicated to the x-address and y-address lines. Tester developers may want this feature to use the Z-address ALU register 24 for page addressing in the DUT 14. The lowest eight logical X-address bits 404b are not processed through the Z-bit replacement logic stage. Each of the top eight logical X-address bits 404a, 404c are processed through a z-bit swap logic stage. If using the ninth actual x-address bit 404a as shown in the example shown, all 16 (16) of logical Z-address bits 402 are available for selection and input to a 16x1 z-select multiplexer 406. . Four bits disposed in the APG_XSCR_ZBITS_L register 316, specifically APG_XSCR_Z_BITS_L [0: 3] bits, are allocated in association with the ninth actual X-address bits 404a. The four APG_XSCR_Z_BITS_L [0: 3] bits select one of the 16 available Z-address bits 402 to replace the replacement bits for the ninth actual X-address bits 404a at the output of the z-select multiplexer 406. Provided as 408. The ninth actual X-address bit 404a and the selected z-bit replacement 408 are input to the 2x1 z-bit enable multiplexer 410. Bit 2 of the APG_XYZ_SCR_EN register 312 enables or disables the scramble function for the X scramble block 302 independently of the Y scramble and Z scramble blocks 304 and 306. Each of the Y scrambled and Z scrambled blocks 304, 306 has a unique bit, APG_XYZ_SCR_EN [1] and APG_XYZ_SCR_EN [0] bits, respectively, which enable or disable the scramble function independently of other scrambled blocks. The APG_XSCR_Z_EN register 314 contains one bit for each of the top eight x-address lines 404a and 404c that enable or disable the z-bit swap function for each line and the upper x-address line 404a. , 404c) may be set independently for each. In the disclosed embodiment, the APG_XSCR_Z_EN [8] bits are allocated to enable or disable z-bit replacement for the ninth actual x-address line 404a. The conjugation of the 9th bit (i.e., APG_XSCR_Z_EN [8] bit) and APG_XYZ_SCR_EN [2] bit 312 starting at the APG_XSCR_Z_EN register 314 is passed to 9 as the output of the z-bit enable multiplexer 410. Select the first actual X-address bit 404a or z-bit swap 408. The combining operation disables the z-bit swap function when the scramble function bypasses block 302. Thus, bit 2 of the APG_XYZ_SCR_EN register 312 and the 8th bit of the APG_XSCR_Z_EN register 314 must both be set to true for the z-bit swap function to work. If any of the enable bits from registers 314 and 312 are set to false, the logical x-address bits 404a appear at the output of the z-bit enable multiplexer 410. Each different z-bit replacement stage is associated with each unique bit of the APG_XSCR_Z_EN register 314 as well as four unique bits from the APG_XSCR_Z_BITS_L and APG_XSCR_Z_BITS_U registers 316. Thus, the z-bit swap function can be programmed separately for each of the top eight bits of the logical X-address lines 404a and 404c. The output set of the z-bit replacement logic stage is referred to as z-selective X-address line 412.

The X scrambled, Y scrambled, and Z scrambled blocks 302, 304, and 306 all comprise jamming logic stages. Thus, this discussion relates to the entirety of the scrambled block, only the X scrambled block 302 is described in detail herein. The jamming logic stage includes a 2x1 jamming multiplexer 414 for each bit of the least significant 8 bits of the logic X-address line 404b and each bit of the most significant z-selective X-address line 412. The jamming stage allows for overlapping of bit values represented as logical X-address 404b or z-selective X-address 412 by the definite programmed value. The corresponding bit positions in the APG_XSCR_JAM_MASK 308 and APG_XSCR_JAM_ADDR 310 registers correspond to respective bit positions in the logical and z-selective X-address lines 404 and 412. The APG_XSCR_JAM_ADDR register 310 is passed as input to the jamming multiplexer 414. The other input is one of the bits from the logic or z-selective X-address lines 404b and 412. One bit in the APG_XSCR_JAM_MASK register 308 corresponding to each bit in the X-address line is passed through the logic / z-selective X-address lines 404b, 412 or the APG_XSCR_JAM_MASK register (such as the output of the jamming multiplexer 414). Program bit value 310 is selected. Each jamming stage is associated with only one of the bits in the APG_XSCR_JAM_ADDR 310 and the APG_XSCR_JAM_MASK registers 308, 310. Thus, the jamming function can be programmed separately for each of the sixteen Z-address lines 404. The output set of the jamming logic stage is referred to as a valid X-address line 416.

The valid X-address line 416 addresses the X scrambled RAM 418. X scrambled RAM 418 is 64 kiloword x 16 bit memory that provides a lookup table for a typical mapping function. The effective X-address line 416 addresses one word of the 64 kilowords and the addressed word is represented as a mapped X-address line 420. The X scrambled RAM 418 is programmed with the appropriate mapping values prior to execution of the test pattern and programmed at the same time as the APG registers 308-328.

The disable stage is implemented by proper programming of the APG_XYZ_SCR_EN register 312 bits 0-2. The test developer can programmatically disable the entire mapping function for any or all of the X scrambled, Y scrambled, and Z scrambled blocks 302, 304, 306. Each of the three bits corresponds to X scrambled, Y scrambled and Z scrambled blocks 302, 304 and 306, respectively. The valid X-address line 416 provides two separate paths within the X scramble block 302. One path of the effective X-address line 416 addresses the X-scrambled RAM 418. Another path of the valid X-address line 416 enters the scramble enable stage 422 by bypassing the X scramble RAM 418.

The scramble enable 422 includes 16 channels, a 2x1 multiplexer that receives an X-address line 420 mapped from the X scrambled RAM 418 and a valid X-address line 416 from the jamming multiplexer 414. do. Bit 2 of the APG_XYZ_SCR_EN register 312 allows the scramble enable 422 to select a mapped X-address line 420 or a valid X-address line 404 to pass as the output of the X scramble block 302. Bit 1 of the APG_XYZ_SCR_EN register 312 controls Y scramble enable and bit 0 of the APG_XYZ_SCR_EN register 312 controls Z scramble enable in a similar manner.

With particular reference to FIG. 5, a block diagram of a Z scrambled block 306 in accordance with the principles of the present invention is shown. As mentioned above, Z scramble block 306 does not include a z-bit replacement logic stage, but a jamming logic stage. The contents of the logic-Z address line 402 and the APG_ZSCR_JAM_ADDR register 328 are input to sixteen 2x1 jamming multiplexers 502. The APG_ZSCR_JAM_MASK register 326 selects between two values for each bit to produce a valid Z-address line 504. The effective z-address line 504 addresses the Z scrambled RAM 506 to access a memory location in the Z scrambled RAM 506 that becomes the mapped z-address line 508. The mapped z-address line 508 is input to sixteen channel 2 × 1 scramble enable 510. A valid z-address line 508 is also input to sixteen channel 2 × 1 scramble enable 510. The bit associated with the Z scramble block 306 in the APG_XYZ_SCR_EN register 312, that is, the APG_XYZ_SCR_EN [0] bit, selects a valid Z-address line 504 or a mapped Z-address line 508 to allow the Z scramble block 306 to be selected. Is passed as actual address information 330 at the output of.

This specification illustrates the features of the invention by way of example. Those skilled in the art will appreciate that the present invention may be modified without departing from the scope of the claims. This specification is intended to explain the invention, but is not intended to limit the invention, the scope of the invention is defined only by the appended claims.

Testers in accordance with the principles of the present invention provide additional flexibility and efficiency in developing test patterns over prior art testers.

Claims (10)

A device for managing address channels in a memory tester, One or more address registers 24 for storing a plurality of logical address bits; A plurality of replacement bits 408, each replacement bit corresponding to one of the logical address bits; A bit selector 410 for each logical address bit and replacement bit combination-each bit selector independently selects either the logical address bit or the replacement bit, and an output set of the bit selectors Becomes an effective address 416 -and A vector processor for applying the valid address in the tester; Memory tester address channel management device. The method of claim 1, And further includes a memory 418 accessed using the valid address 416. Memory tester address channel management device. The method of claim 1, A replacement register 24 which stores a number of available bits 402 passed to a number of replacement bit selectors 406-each said replacement bit selector 406 is adapted for each of said plurality of said replacements Corresponding to each one of the bits 408, each said replacement bit selector 406 selecting one of said plurality of available bits 406 to generate one of each of said replacement bits. More containing Memory tester address channel management device. The method of claim 1, One or more second address registers 24 store the plurality of available bits 402. Memory tester address channel management device. The method according to claim 1, wherein Contents of the one or more address registers are generated algorithmically Memory tester address channel management device. The method of claim 3, wherein Each of the replacement bit selectors 406 is addressed to a value specifying which of the available bits 420 will be selected. Memory tester address channel management device. The method of claim 6, Wherein each value specifying which of the available bits is to be selected is stored in one or more select control registers 316. Memory tester address channel management device. The method of claim 7, wherein The one or more select control registers 316 are programmable Memory tester address channel management device. The method of claim 7, wherein The select control registers are programmable independently of one another. Memory tester address channel management device. The method of claim 1, The bit selector may be disabled Memory tester address channel management device.