DE10144645A1 - Device for manipulating address information in a memory tester controls address channels in the memory tester with address registers storing logical address bits, replacement bits, a bit selector and a vector processor. - Google Patents

Abstract

A memory tester has a feature for using any section of a z address register as a substitute for up to eight most significant bits in x address lines. A majority of z selection multiplexers select one of sixteen z address lines for transfer to a majority of z-bit activation multiplexers. Each z-bit activation multiplexer chooses between a selected z-bit or a matching x address bit. An Independent claim is also included for a method for manipulating address information in a memory tester.

Description

In everyday life there are electronic devices and their lei capabilities are now widely used. Moreover Many people wear personal computers at home more than a productivity device for all kinds of purposes yourself. Most personal electronic produktivi Process devices include a form of non-volatile memory cher. Mobile phones use non-volatile memory to user-programmed phone numbers and configurations to save and maintain when the performance is shut down is. PCMCIA cards use non-volatile memory, to store and receive information even if the card is removed from its slot in the computer. Many other widely used electronic devices professional also benefit from the long-term storage capacity of non-volatile memory in non-powered devices.

The manufacturers of non-volatile memories that are attached to the Electronic equipment manufacturers sell, develop testers to ensure the correct operation of the memory that they manufacture, execute and verify. Due to the Amount of non-volatile memories that are manufactured and are sold at continuously low prices it is very important to minimize the time it takes to test a single part. Due to the cost savings in connection with the practice of installing the Storage elements in more expensive arrangements with minimal or Without testing, buyers demand non-volatile food from memory manufacturers that the same high ver achieve sand yields. Accordingly, the memory test process be sufficiently efficient by a large percentage set of defective parts and preferably all defects  are liable to identify parts in a single test process ren.

While non-volatile memories are larger, denser and com To be more complex, the testers must be able to use it increased size and complexity to edit without the time significantly increase that is needed to do the same testing. As memories evolve and improve, the tester must be able to easily adapt to the changes adjustments that have been made to the element. Another specific topic when testing non- volatile memory is that repeated writes on cells the memory the total life performance ability of the part to deteriorate. The manufacturers of non-volatile memories have on many of the test tasks by installing special test modes in the memory elements responding. These test modes are used by the buyer of the Spei chers not used at all, but the manufacturer can access them to all or essential section storage in the shortest possible time and as efficiently as possible to test as efficiently as possible. Some non-volatile food They can also be repaired during the test process. The tester should therefore be able to: identify: a repair needed, a location of the Repair, the type of repair needed, and then must be able to carry out the appropriate repair. Such a repair process requires a tester to is able to identify a specific faulty section of the Capture and separate storage. To the entire front parts of the special test modes as well as the repair radio it is beneficial for a tester to to be able to run a test program that conditional branching based on an expected response che supported by the element.

The process is from a conceptual perspective of memory testing is an algorithmic process. As Typical tests include sequential increments  animals or decrement memory addresses while Zeros and ones are written into the memory cells. It is common to have a collection of ones and zeros, those written or read during a memory cycle are referred to as a "vector" while the The term "structure" refers to a sequence of vectors. It is common in tests to write structures such as. B. Chess boards, running ones and butterfly structures to record in the storage space. A test developer can with the help of algorithmic elements Program to create these structures easier and more effi generate more efficiently. A test structure that algorithmic ko is also easier to troubleshoot, and Logical procedures are used to isolate sections of the Structure that doesn't work as expected is easier to get use. A test structure created using An Instructions and commands that are in programming loops again fetched, generated algorithmically, consumed in the Tester memory less space. Accordingly, it is fine worth an algorithmic in a memory tester To have test structure generation capability.

The exact signal edge placement and detection is flat if a consideration to the effectiveness of a non- volatile tester. To capture parts that generally a median while not within half of the specified range, a non- volatile memory tester to be able to any signal edge in terms of time to another signal edge to be placed precisely. It is also important that the same is able to measure exactly at what time a Signal edge is received. Accordingly, a non-volatile memory tester sufficient flexibility and control the timing and placement of Stimuli and responses from the person to be tested Device (memory).  

The memory testers are intended to generate transmit vectors that are the DUT (device under test = device to be tested) is created are received (stimulus) and vectors that respond expected (answer). The algorithmic logic that generated these vectors can generally do this without dealing with it like a special bit in a vector from or to a special one Signal connection point in the DUT. At that level it almost seems as if there is a certainty that adjacent bits in the vector are also considered physical neighboring signals arrive at the DUT. If only so would be easy!

In reality, the correspondence between the bits tends in a vector on the "conceptual level" and the actual signals in the DUT to be more arbitrary his. If nothing is done to avoid this, you can it may be necessary to add one or more probe wires cross because they hang from a periphery, to get in touch with the DUT. Such a crossing is not desirable at all and it's convention a mapping mechanism in the path of the transmit vector to reinstall the bit positions in the transmit vector assign before they are applied to the DUT, so that the task of making physical contact is not burdened by crossings. Receive vectors who corresponding to an inverted imaging mechanism created before they are processed. In this way It will be the algorithmic vector generation and ver equal mechanisms enables this entire area to to ignore. As another example of what such fig who can perform and reverse images, consider that Case where another example of the same type of DUT spread on the same wafer, but with a ro tation or a mirrored symmetry to prevent that space on the wafer is wasted. These practices also have an effect on correspondence between Vector bit position and physical signal position that but through the appropriate illustrations and reverse images  can be covered. It can be seen that the fig and reversal images that are appropriate for these situations are required to be static once they are for a special DUT are identified, and during the course of testing for this particular DUT need not be changed.

For certain types of storage, one requires efficiency ter test manipulating a group of bits of the address lines separate from another group of bits of the address lines. For testers of the prior art without generating algorithmic patterns Task relatively easy in that the address lines were defined as two separate groups and bit by bit were managed. An example of a type of storage that supports This type of addressing is a memory that has a Organization of several blocks of memory cells in one Maintains page addressing format where the pages addressing determined the most significant bits of the address lines used and the memory word addressing be agreed the minimum address lines used. Around the generation of algorithmic patterns for testing these ares However, it is necessary to take full advantage of memory Lich that a tester is a simple solution to selective Grouping bits in the address lines for an independent current generation of algorithmic patterns.

It is the object of the present invention to provide a front Direction for managing address channels in a memory tester, a method of managing address channels in an egg nem memory tester and a device for managing To create addresses in a memory tester, which have permanent properties.

This object is achieved by a device according to claim 1, a method according to claim 12 or an apparatus according to Claim 16 solved.

According to one aspect of the invention, a device for Manage address channels in a memory tester  more address registers that have a plurality of logical Have address bits and a plurality of spare bits, where each spare bit corresponds to one of the logical address bits. The device also has a bit selector for each logical address bits and each replacement bit combination, and each bit selector independently selects either the logical one Address bit or the replacement bit. A collective outcome The bit selector is an effective address that is for the purpose testing memory. A vector pro processor applies the effective address in the tester.

According to a further aspect of the invention, a method to manage address channels in a memory tester the steps of passing a plurality of logical ones Address bits to a respective plurality of bit selectors one logical address bit per bit selector and one replacement bit per bit selector. The procedure then selects neither the logical address bit or the replacement bit, where a collective output of the bit selectors an effective address se is. The effective address is for the purpose of addressing a DUT memory is used.

Advantageously, a tester according to the teachings of present invention additional flexibility and Efficiency in developing test patterns in comparison to testers of the prior art.

Preferred embodiments of the present invention are referred to below with reference to the enclosed Drawings explained in more detail. Show it:

Figure 1 is a simplified block diagram of a largely reconfigurable non-volatile memory tester constructed in accordance with the invention.

FIG. 2 is an expanded simplified block diagram of the DUT tester 6 of FIG. 1;

Fig. 3 is a block diagram of the address mapper 29 shown in Fig. 2;

FIG. 4 is a block diagram of the XScramble section (or the X-scrambling or scrambling section) 302 of the address mapper 29 shown in FIG. 3; and

FIG. 5 is a block diagram of the ZScramble section 306 of the address mapper shown in FIG. 3.

With reference to Fig. 1 is a simplified Blockdia program is shown a non-volatile memory test system 1, the principles of the invention constructed in accordance with. In particular, the system shown can simultaneously test up to 36 individual DUTs (Devices Under Test = test devices), each with up to 64 test points at a time, with provisions for reconfiguration to enable elements of a collection of test resources to test DUTs with more than 64 test points. These test points can be positions on a portion of an integrated circuit wafer that has not yet been singulated and packaged, or they can be the pins of the packaged part. The term "test point" refers to an electrical position at which a signal can be applied (e.g. power supply, clocks, data inputs) or at which a signal can be measured (e.g. a data output). In this description, those who follow the customs of the industry refer to the test points as "channels". The "collection of test resources to be linked" referred to above can be viewed as up to 36 test sites, each test site having a test site controller ( 4 ), a (64 channel) DUT tester ( 6 ) and a (64 channel) collection of pin electronics ( 9 ) that actually connects to a DUT ( 14 ). In the event that testing of the DUT requires 64 or fewer channels, a single test site is sufficient to perform tests on this DUT, and here, for example, it is assumed that test site # 1 (as shown in Fig. 1 appears) forms or acts as a "single site test station". Conversely, if one form of the aforementioned reconfiguration is effective, two (or more) test sites are "connected" to act as a larger equivalent test site with 128 channels. Accordingly, and again referring to an example shown in FIG. 1, it is assumed that test sites # 35 and # 36 form a "two-site test station".

To briefly consider the opposite case, shouldn't be assumed that an entire test site is required, to test a single DUT or that a single Te can only test a single DUT. Suppose a wa fer would two (but may not necessarily be neighboring) chips, the sum of the Testka would be 64 channels or less. Both DUTs can be tested by a single test site become. This is due to the universal programmability of the test site. A test program by the Test site is executed, can be written as that part of the test site's resources is used to test one of the DUTs while using a part to test the other DUT. When you finally assume that if there is a third DUT, this is the logical one Unit of the first two would be able to to test this third DUT with a single test site, therefore one should be able to use the "Compos ten-DUTs "of the same. The only difference is to track individually whether the two "component DUTs" exist or fail as opposed to a uniform Answer for the "third" DUT (i.e. there is a problem regarding which section of the "third" DUT has failed). This "single-site multiple test station" - Ability is mostly conventional and becomes here Purpose of completeness mentioned and possible confusion and misunderstandings to avoid if the same with  the idea of connecting two or more test sites is compared.

Apart from this thought of reconfiguration, there would be no difference between a test site and a test station, and one of these terms could be omitted the. As it is, however, it becomes apparent that the An number of test stations does not equal the number of testors must be. In the past, the numbers could not be different because the test locations have been divided to generate more test stations (DUTs that are not complex are enough to consume an entire test site). Now the difference can also be due to the fact that the Te were linked together to multi-site Form test stations (DUTs that are too complex for one are the only test site).

A test system controller 2 is then connected by a system bus 3 to up to 36 test site controllers, the names of which end with the suffix 1 to 36 ( 4 a to 42 ). (It is true that the indices a to z only go from 1 to 26, and not to 36. But this small deviation is preferable to numerical indices after numerical reference signs, which would probably be very confusing.) The test system controller 2 is a computer (e.g. a PC running NT) that executes an appropriate test system control program related to the task of testing non-volatile memory. The test system control program represents the highest level of abstraction in a hierarchical division of labor (and complexity) for performing the desired testing. The test system control determines which programs are run by the different test sites and also monitors a robot system (not shown) that the test probes and DUTs moved as needed. The test system controller 2 can act in certain ways that support the idea that some test sites are programmed to operate as single-site test stations while others are connected to form multi-site test stations. Of course, under such circumstances, the different parts are tested, and it is very desirable that different tests are used for the different parts. Similarly, there is no requirement that all single-site test stations test the same type of parts, nor is there a requirement for multiple-site test stations. Accordingly, the test system controller 2 is programmed to issue the commands, to perform the required test site connection and then to call up the appropriate test programs for the various test stations used. The test system controller 2 also receives information about results obtained from the tests so that it can take the appropriate actions to dispose of the bad part and obtain the same logs for the various analyzes that can be used to for example to control production processes in a factory environment.

The test system itself is a relatively large and complex system, and it is common for the same to use a robot subsystem to load wafers onto a stage, which then successively positions one or more future chips under probes connected to pin electronics 9 are, after which these future chips (the wafer has not yet been isolated) are tested. The test system can also be used to test packaged parts that have been loaded on a suitable carrier. Depending on the test station that is in operation, at least one test site controller will be assigned (as will be explained below), regardless of how many test sites are used to form this test station or how many test stations are at a test site. A test site controller is an embedded system, which can be an i960 processor from Intel with 36 to 64 MB of combined program and data memory, which runs on its own operating system called VOS (VersaTest operating system), which is also used in earlier products Testing non-volatile memory (e.g. Agilent V1300 or V3300) was used. For the moment, only the situation for single-site test stations is considered. For the purpose of a specific example, it is assumed that test site # 1 acts as test station # 1 and that it should test WHIZCO part # 0013. The test determinations include about 100 different types of tests (varying and monitoring voltage levels, pulse widths, edge positions, delays, as well as a large amount of simple storage and then retrieval of selected information structures), and each type of test involves many millions of individuals Storage cycles for the DUT. At the highest level, the operators of the test system instruct the test system controller 2 to use the test station No. 1 to start testing the WHIZCO 0013. In due course, the test system controller 2 notifies the test site controller No. 1 ( 4 a) (which is an embedded [computer] system) to let the assigned test program, such as TEST_WHIZ_13, run. If the program is already available within the Test Site Control # 1 environment, it will simply run. If not, it is supplied by the test system controller 2 .

In principle, the TEST_WHIZ_13 program could now be completely independent. But if it were so, it would be very large with ziem Licher security and it can for the processor of the embedded system within the Test Site Controller 4a be difficult, fast enough to run, to produce the tests at the desired speed, or even with a Rate that is uniform from one DUT memory cycle to the next. Accordingly, low level subroutine type activities are generated, the sequences of addresses and associated data to be written or expected from a read operation are generated as needed by a programmable algorithmic mechanism that is positioned in the DUT tester 6 is niert, but works synchronously with the program that is executed by the embedded system in the test site control 4 . This can be seen as exporting certain low-level subroutine-like activities and the task of triggering DUT memory cycles to a mechanism (the DUT tester) that is closer to the hardware environment of the DUT 14 . Generally speaking, each time the test system controller 2 equips a test site controller with a test program, it then also provides the associated DUT tester with appropriate low level implementation routines (perhaps specific to the memory under test) that are needed to determine overall activity to be carried out, which is described or required by the programming for the test site control. The low level implementation routines are called "structures" and are generally named (just as functions and variables in high level program languages have names).

Each test site controller n (4) is coupled to its associated DUT tester n (6) by a site test bus n (5). The test location controller uses the location test bus 5 , both to control the operation of the DUT tester and to receive information from it about test results. The DUT tester is able to control the various DUT memory cycles as specified in the test regulations are included, generate at high speed, and decide whether the results of a read memory cycle are as expected. In essence, it responds to commands or opcodes ("named structures") sent by the test site controller by triggering appropriate useful sequences of read and write DUT memory cycles (ie, it executes the appropriate structures) ). Conceptually, the output signal of the DUT tester 6 is stimulus information to be applied to the DUT, and the same also accepts response information from the same. This stimulus / response information 7 a runs between the DUT tester 6 a and a pin electronics no. 1 arrangement 9 a. The pin electronics arrangement 9 a supports up to 64 probes that can be applied to the DUT 14 .

The stimulus information mentioned above is only a sequence of parallel bit structures (ie, a sequence of "transmit vectors" and expected "receive vectors") that is expressed according to the voltage levels of a family of logic elements used in the DUT tester. There is configurable mapping between bit positions in a stimulus / response and the probes on the chip, and this mapping is understood by the DUT tester 6 . The individual bits are correct in timing and edge placement, but in addition to mapping, they may also require voltage level switching before they can be applied to the DUT. Likewise, a response that occurs subsequent to a stimulus in the DUT may require buffering and "reverse" level switching before it can be considered appropriate to be returned to the DUT tester. This level switching task are the area of pin electronics 9 a. The pin electronics configuration needed to test a WHIZCO 0013 is unlikely to work on testing a part from ACME Co., and maybe not even on another WHIZCO part. Since it is obvious that the pin electronics arrangement must also be configurable, such a configurability is the function of the PE configuration lines 8 a.

The above explanations end with a brief architectural overview of how a single test site for te most of a DUT is structured. Subjects that follow now arise when there are many test sites that operate Need to become. As an introduction, a preferred version Example for setting up a test system with several Test sites described. In many ways, there are some the information that is described is a question of Preferences based on market studies on customer preference ben and cost-benefit analyzes. Anyway, one thing  To create these things you have to make a certain choice meet, and once this is done, certain arise Consequences that are visible through the entire system. It is believed to be useful, at least in general the larger outline of the hardware egg to describe properties of the test system. Even if egg some of these properties are random; becomes the knowledge the same nevertheless an acknowledgment of the different be Support games that are used to complete the invention display.

To begin with, consider four rather large card cages. Except Power supplies and water cooling (fans can be in a clean room environment is a source of pollution each card cage includes a motherboard, one Front surface and a rear surface. Can be in any card cage up to 9 arrangements can be placed. Any arrangement includes a test site controller, a DUT tester and a pin electronics. The following is a rough outline of how test site controls are connected, what some buses which will be used to make concatenations (Dai sy-chains).

A brief digression on the term "chaining" is perhaps appropriate at this point. Look at that System elements A, B, C and D. Suppose the same should be chained in this order. You could say, that there is an information or control route that ver lets and goes in D that B selectively forward traffic which then leaves B and goes into C, and that C is selective Can forward traffic that then goes to D. This same che type of arrangements can also be used for traffic in the whose direction exist. Chains are often used det to create priority schemes, the same used here to establish master / slave relationships between ver to generate different test site controls. This chain th communication arrangements are with the additional word "DSY" instead of "BUS". So instead of one  Command / data bus referred to a command / data DSY become. Now the thought that information "in B. penetrate and be forwarded selectively ", hindeu that traffic on a separate set of ladders is reproduced before being forwarded. It could be like that, but for performance reasons it's more of a regular rer bus with addressable units. Through a program mable address mapping arrangement and the ability to stro Downstream test site controls can be achieved that the single bus is as logical as a plurality of chains appears (that is, how it works). Finally, it is obvious that the concatenations are high power paths for command and control information are, and that if they weren't, you couldn't expect that a master / slave combination (multi-site test station) works as fast as a single test site. In favor of Concatenation efficiency must be said that the different DSY their respective card cages leave. The effect of this decision is that some Restrictions are imposed on which test locations (and thus also how many) can be connected. In principle there is no basic need for this restriction, yet there is a general lack of technical internship lity (it could be done), it will only assumed that expanding the DSYs was essential Cost for a relatively small additional benefit would work, since there are already 9 test locations in a card cage consist.

To accommodate the discussion of Fig. 1 again, the various Test Site Controllers 4 are a- 4 z regarded that can occupy the 4 card cages, each gene having 9 Testortsteuerun. The same will be f 4 a- 4, 4 g 4 m, 4 n- 4 t and 4 u- 4 z. (It doesn't matter that these are nominally only 26 additions, as previously explained - the reader is invited to imagine that there are another 10 addition symbols somewhere out there.) A CMD / DAT DSY 17 a (command and data -Daisy chain = command and data chaining) connects the test site controls 4 a- 4 f, which are located in a card cage, while another CMD / DAT DSY 17 b connects the test site controls 4 g- 4 m in another card cage. The same arrangement exists for the remaining card cages and the test site controls 4 n- 4 t or 4 u- 4 z. It has previously been noted that the DSY does not leave the card cages because the "tail end" of a bus that actually forms the DSY does not leave a card cage and the head of the next segment becomes another card cage. Instead, the system bus 3 goes from the test system controller 2 to all test site controllers, and everyone is able to become a master at the head of a DSY segment that does not leave the card cage.

The CMD / DAT DSY 17 a-d that were discussed exist between the various test site controls 4 a- 4 z. There is a similar arrangement for the SYNC / ERR DSY 18 a- 18 d and the DUT testers 6 a- 6 z. The synchronization and error information transmitted by the SYNC / ERR DSY 18 enables the DUT testers to function in unison. These two chains ( 17 and 18 ) carry slightly different types of information, but each exists as part of the same general mechanism for connecting one or more test sites to a test station.

A discussion of FIG. 2 follows, which is a simplified block diagram extension of the DUT tester 6 of FIG. 1, of which up to 36 may be present. It is sufficient here to describe only one example. A look at Figure 2 shows that it is quite crammed, especially for a "simplified" block diagram. Some of what is in the DUT tester 6 and shown in the block diagram is functionally quite complicated and is not directly available in this form. It is appropriate to make two points here. First, the primary purpose of the inclusion of FIG. 2 is to describe the basic properties of an important operating environment within the entire non-volatile memory test system 1 . The invention (s) fully described in connection with FIG. 3 and subsequent figures are either extensions of the mechanisms set out in the following description of FIG. 2, or they are new mechanisms whose motivation requirement in FIG. 2 can be found. In any case, while this is being written, it is not known exactly what the reader has. The current goal is to provide a simplified, yet informative, starting point for numerous different detailed descriptions of different preferred embodiments, so that each of them can be as accurate as appropriate (as opposed to a "giant" specification that reveals everything about each different invention). The second point is that the expanded or expanded material, although generally in general agreement with FIG. 2, may contain information that does not exactly match the simplified version. This does not mean that there is a mistake or that things are crucially contradictory, but it occurs because it is sometimes difficult or impossible to simplify something so that it is the exact miniature image. The situation is more like that of maps. A standard size road map of Colorado shows that if you drive east on I-70, you can drive north on I-25 at Denver. This looks like a left turn. And although it was actually a left-hand bend, it isn't now, and a detailed map of this intersection will show a sequence of sub-bends and road sections in between. But nobody would say that the standard size road map is wrong, it is correct for its level of abstraction. Similar to and despite the rather crowded appearance, Fig. 2 is actually a simplification that works with a medium level of abstraction, but some apparent left turns are simply not left turns in reality.

As shown in Fig. 1, the main input to the DUT Tester 6 is an example of the Test Site Bus 5, the sen origin lies in the Test Site Controller 4 that is associated with the case of play of the DUT Tester 6. The test site bus 5 is coupled to a microcontroller sequencer 19 , which can be compared with a special microprocessor. The same retrieves instructions from a program that is stored in a program memory, which can either be contained in the microcontroller sequencer 6 (PGM SRAM 20 ) or can be outside the same (EXT. DRAM 21 ). Although these two memories appear to be addressed by an essentially logical common address 63 that serves as a program counter (or instruction fetch address) and both can be a programming source to be executed, the following should be noted: (1) only one of the memories performs instruction fetch memory cycles during each period of time, and (2) in fact they are addressed by electrically different signals. The SRAM is fast and enables real direct access, but takes up valuable space within the microcontroller sequencer 19 (which is a large IC), so its size is limited. The external DRAM can be supplied in adjustable amounts of a considerable amount, but is only fast if it is accessed in successive blocks that include the linear design and no branching. Programming in the SRAM 20 is mostly most algorithmic, while the EXT. DRAM 21 is best suited for material that cannot be easily generated by algorithmic processes, such as. B. Initialization routines and random or irregular data.

The instruction word executed by the microcontroller sequencer 19 is relatively wide: 208 bits. It consists of 13 16-bit fields. These fields often represent instruction information retrieved for mechanisms that lie outside the proper microcontroller sequencer. Such fields are reserved for their assigned mechanisms. A set of ALU instructions 22 is applied to a collection of 8 16-bit ALUs 24 , while others are distributed to various other mechanisms distributed by the DUT tester. This latter situation is represented by the lines and the designation "Various control values &instructions" 42 .

The 8 16-bit ALUs ( 24 ) each have a conventional repertoire of arithmetic instructions, which are structured around assigned 16-bit result registers (each ALU also includes several other registers). Three of these result registers and their associated ALUs are for generating X, Y and Z address components 27 which are combined differently into a complete address which is provided to the DUT. Two more of the 8 ALU / registers (DH and DL) are provided to contribute to the algorithmic generation of 32 bit data structures 28 which are divided between a most significant section (DH) and a least significant section (DL). The last three ALU / registers (A, B, C) are used as counters and contribute to the creation of various program control flags 25 , which are used for program control and branching upon completion of a programmatically specified number of iterations or other numerical conditions contribute. These program control flags 25 are sent back to the microcontroller sequencer 19 where they affect the value of the instruction fetch address in ways that are familiar to those who understand microprocessors. There are also various other flags 55 that can also be used to affect a program branch. These originate together with various other mechanisms in the DUT tester 6 , which are controlled by the different fields of the instruction word retrieved. A specific additional flag is explicitly shown as a separate element: VEC_FIFO_FULL 26 . In another, less detailed drawing, the same can be summarized with the other flags 55 . Here, it has been separated to help explain an aspect of the operation of the microcontroller sequencer 19 .

The VEC_FIFO_FULL (temporarily) stops the further program execution by the microcontroller sequencer 19 . There are many pipeline stages between the instructions that are fetched by the microcontroller sequencer 19 and the mechanism that ultimately outputs test vectors to be applied to the DUT. Also, part of the baggage accompanying a vector as it moves in the direction to apply the DUT is information related to the rate of eventual application of the vector or the duration of each vector. Thus, the rate of vector application to the DUT need not be constant and, in particular, a group of vectors may take longer to apply than to generate. The microcontroller sequencer simply does the programming at its maximum rate. But of course the rate of "vector consumption" must on average be the same as the rate of "vector production", otherwise the pipe line would have to be infinitely elastic. There is a vector FIFO 45 at the output of address mapper 29 , discussed below, and it serves as an elastic capacity in the pipeline. The VEC FIFO FULL signal is used to prevent the limited number of stages in the pipeline from being exceeded by causing a temporary stop in the production of new vectors at the head end of the pipeline.

Subsequently, the (3 × 16 = 84 bits of) X, Y and Z address components 27 are applied to an address mapper 29 , the output signal of which is a preselected almost arbitrary rearrangement of the address values in the sorted 48-bit address space. As a starting point for recognizing the same, assume that the address mapper 29 is a memory that completely occupies a 48-bit address space and that it holds a 48-bit value at each address. (It is temporarily not to be taken into account that such a memory - at least nowadays - would be the size of a large refrigerator.) If one starts from such a memory, a lookup table could be implemented which arbitrarily outplaces each address created could map the selected 48-bit value, which could then be used as an exchange address. The reason that such address mapping is desirable is that the X, Y and Z address components generally have a useful meaning in the context of the internal architecture of a particular DUT, which is unlikely to be implemented with a large linear decoder , The thoughts of rows, columns, and layers, blocks, or pages can be very useful to the test engineer, and errors that occur in positions that are physically close to each other can be close to their X, Y, and Z addresses exhibit. Such structures in the test results can be valuable in recognizing what is wrong and trying to fix it, whether it is at the development level or a manufacturing level to reprogram a part, to operate a defective section with the to bridge an additional section. Two points arise from this thinking. The first is to limit the 48 bits to the actual number of bits (approximately 32 or maybe 16) to be applied to the DUT. The following briefly mentions how the constraint is performed, and is generally done by taking out so many bits of X, so many of Y, and the rest of Z. But not exclusively, and this is the second point, because certain addresses can reside within a circuit arrangement that is a left-for-right (or left-for-right and up-for-down) mirror image of another section of the circuitry , This has the effect of rearranging what the bits mean, depending on which consecutive address values are in physical order within this circuitry. This chip layout property can occur often, and it may well be the case that how a group of bits, e.g. y, is interpreted may depend on the accompanying value of others, e.g. Z bits. The address map of Figure 29 is provided to allow the raw X, Y and Z addresses to be "repackaged" to reflect this to the benefit of those who would test memories with such internal architectural arrangements. As it is actually carried out, the address mapper 29 is constructed from a relatively large number of multiplexers which are connected to one another. The same can implement the completely arbitrary lookup table behavior of a fully occupied memory decoding scheme, as was temporarily assumed above for explanatory purposes. However, it can rearrange subfields of the X, Y, and Z address components as needed, especially since there is now another mechanism that restricts 48 bits to the number actually needed. The address images 29 also contains three 16-bit (address) look-up tables which enable the same to perform any limited mapping within local areas.

The mapped address output signal 30 of the address mapper 29 is applied as an address to an auxiliary RAM 31 (AUX RAM) 31 and an error detection RAM 32 which, although having separate functions, can nevertheless be implemented selectable parts in a larger total RAM , The mapped address output signal 30 is also applied as an input signal to an address bit selection circuit 37 , which will be described below.

The auxiliary RAM 31 is considered below. Its function is to maintain data structures 33 and addresses 34 that can be applied to the DUT. These are logically separate output signals from the auxiliary RAM 31 , since they are treated somewhat differently and are used in different places. (The auxiliary RAM 31 is not a "dual port memory", but preferably consists of several banks, the output signals of which are applied to multiplexers.) To match this, stored data 33 may be in a bank or area of addresses of the auxiliary RAM 31 are stored, while stored addresses 34 are stored in another. In addition, no explicit mechanism for writing to the auxiliary RAM 31 has been shown. This is carried out by an addressed bus operation, which is triggered by a test location controller 4 at the command of the program, which executes the same. There is an underlying "utility service" bus, referred to as the "ring bus" (which is not shown since it would overwhelm the drawing enormously) which leads to almost everything in Figure 2).

The error detection RAM 32 is addressed by the same address that is applied to the auxiliary RAM 31 and stores or retrieves information about errors where these operations are performed in conjunction with a post-decode circuit, which will be discussed below. As with paths 33 and 34 from the auxiliary RAM 31 , the paths 61 (in the fault detection RAM) and 62 (from the fault detection RAM) are preferably multiplexed outputs from multi-bank memory (the fault detection RAM 32 ) according to configuration information distributed through the ring bus (not shown).

It should be noted that the data MUX 35 includes, as input signals, the stored data output signals 33 from the auxiliary RAM 31 , and also data 28 from the registers DH and DL in the collection 24 of ALUs. The data MUX 35 selects which of these input signals ( 28 , 32 ) is presented as its output signal 38 , which is then applied as one of the two vector components to a transmit vector map of the / serial converter / receive vector comparison data circuit 40 (the other component is the output si Signal 39 of the address bit selection circuit 37. ) The circuit 40 can perform three functions: assembling vector components ( 38 , 39 ) into a sorted logical representation of an entire vector which is to be applied to the DUT, applying any dynamic Correspondence (mapping) between the sorted bits of the logical representation of the transmit vector and the actual physical number of channels of the pin electronics (ie which probe tip) the DUT will contact for this signal (ie the bit in the vector) and cooperating with the compiler in the division of an entire logical vector into pieces that are separated and in rows sequence (serial conversion) should be created for DUTs that allow such a thing. Which of these functions is performed is determined by control signals from an SRAM 41 , which is also addressed according to a field in the 208-bit instruction that is fetched by the microcontroller sequences 19 . The output of circuit 40 is an up to 64-bit vector 44 which is applied to a vector FIFO 45 which, when full, generates signal VEC_FIFO_FULL 26 , the meaning and use of which has been discussed above. The vector at the top of the FIFO 45 vector is removed therefrom upon receipt of a VEC_FIFO_UNLOAD 47 signal generated at a period generator 49 (discussed below). Such remote vectors ( 46 ) are applied to a timing / formatting and comparison circuit 52 which is connected to the DUT via the associated example of pin electronics 9 .

That is, each example of pin electronics 9 receives transmitted and received vectors 7 and pin electronics configuration information 8 from its associated timing / formatting and comparison circuit 52 .

The timing / formatting and comparison circuit 52 includes an internal SRAM 54 which is addressed by the same instruction address ("A" in the small circle) as the program RAM 20 of the microcontroller sequencer 19th (An external DRAM 53 can be used instead of the internal SRAM 54. ) The internal SRAM 54 (or external DRAM 53 ) supports the production of driver and comparison cycles. The driver cycles apply a send vector to the DUT. The comparison cycles receive a vector represented by the DUT and examine it to determine if it matches previously sent comparison data. Both the driver cycle and the comparison cycle can be set with regard to their duration, with regard to whether a load is applied or not, when it is applied and when data is temporarily stored or sampled. The comparison produces a 64-bit value 56 that is sent to a receive vector inverse / serializer 57 , the function of which can be viewed as the logic inverse of circuit 40 . (The operation of the circuit 57 is controlled by an SRAM 58 , which corresponds to the control of the circuit 40 by the SRAM 41. ) Thereafter, the output signal 59 of the circuit 57 is applied to the post-decoding circuit 60 . It is currently sufficient to say that the post-decoder circuit 60 can examine, via programmatic criteria, both incoming error information 59 and (previously) stored error information 60 (which is stored in the error detection RAM) in order to generate compressed and easier to interpret error information, which can then be saved back to error detection RAM 32 via path 61 . An example would be to generate a number of times an error occurred in a particular range of addresses, which information would be useful in deciding when to attempt to repair on-chip by activating spare circuits.

The period generator 49 and its associated timing SRAM 51 will now be described. These respond to an eight bit signal T_SEL 43 on which for each 208-bit instruction that is call 19 abge by the microcontroller sequencer, a duration for the associated operation of the Timing / Formatting & Comparison circuit 52 agrees be. T_SEL 43 is an element of the various control values and instructions 42 , which are represented by the different fields in the called instruction. As an 8-bit value, it can represent or encode 265 different things. In this case, these "things" are 28-bit values stored in the timing SRAM 51 and addressed by T_SEL. Each addressed 28-bit value (23) specifies a desired duration NIIT ÄI ner 19, 5 picosecond resolution. The sequence of 28-bit duration values ( 23 ) to be accessed is stored in a period FIFO 50 , so that the individual elements of this sequence are recovered and synchronized when the intended corresponding vector stored in the vector FIFO 45 is retrieved be created.

A coarse timing value field in the oldest entry in the FIFO 50 transmits duration information with a resolution of 5 nanoseconds and generates a signal VEC_FIFO_UNLOAD 47 which transfers the next transmit vector from the vector FIFO 45 to the timing / formatting and comparison circuit 52 . An accompanying signal Zeitge bungsrest 48 is also applied to the circuit 52 . There the final resolution is carried out to 19.5 picoseconds.

Some memories consist of multiple memory blocks that are reproduced on a single chip to form the total memory space in a memory device. As is often the case, the reproduced blocks are over either a vertical or a horizontal axis or the mirror image of each other, and these reproduced blocks can be reproduced further. It is often efficient to create a single test for one of the memory blocks and to repeat it for the reproduced blocks. While the test pattern is relevant to each block, it is not possible to reuse a single test for all of the memory blocks because the memory blocks are images of each other. Accordingly, the reproduced blocks affect a test for the device in that the address bits follow a different sequence for each block. However, the different sequences are related to each other. The scrambling feature enables a test developer to reuse test patterns for the various memory blocks by programming only one scrambling function. The test pattern itself is reused, and the scrambling function, which is algorithmically separate from the test pattern program instructions, performs management tasks related to adjusting the test pattern for each block of memory being reproduced. Some memories are also organized in pages. Pages are addressed using certain subsets of address bits. The scrambling function is enhanced by allowing algorithmic control of certain bits separately from the other address lines, and then allows regular address bits to be substituted for those bits entered into the scrambling function. Referring specifically to Figure 3 of the drawings, a mid-level detail view of address mapper 29 shown in Figure 2 of the drawings is shown, in which XScramble- 302 , YScramble- 304 and ZScramble- 306 blocks each have 16 address bits from address-X- , Address-Y and Address-Z ALU registers 24 received. Accordingly, the forty-eight ( 48 ) address lines shown in FIG. 2 as reference number 27 are divided into three ( 3 ) groupings of 16-bit logic address lines in FIG. 3. The XScramble, YScramble and ZScramble blocks 302 , 304 , 306 also receive information that has their origin in APG registers. The programmability of the APG registers provides the programmability features of the tester functions. Values for each of the APG registers are stored and downloaded as part of the compiled object code in a test pattern to provide initial values prior to executing a test pattern. It is also possible, but not as common, to change values in certain of the APG registers while executing a test pattern. A large number of APG registers exist in the tester and only those registers relevant to the present invention are disclosed herein. The APG registers relevant to XScramble block 302 include an APG_XSCR_JAM_MASK [0:15] register 308 , an APG_XSCR_JAM_ADDR [0:15] register 310 , bit 2 of an APG_XYZ_SCR_EN register 312 , an APG_XSCR_Z] - Register 314 and APG_XSCR_Z_BITS_L [0:15] & APG_XSCR_Z_BITS_U [0:15] register 316 . The APG registers relevant for the YScramble block 304 comprise an APG_YSCR_JAM_MASK [0:15] register 318 , an APG_YSCR_JAM_ADDR [0:15] register 320 , bit 1 of the APG_XYZ_SCR_EN register 312 , an APG_YSCR_Z_EN [0 - Register 322 and an APG_YSCR_Z_BITS_L [0:15] - & - APG_YSCR_Z_BITS_U [0:15] register 324 . The APG registers relevant to the ZScramble block 306 include an APG_ZSCR_JAM_MASK [0:15] register 326 and APG_ZSCR_JAM_ADDR [0:15] register 328 and bit 0 of the APG_XYZ_SCR_EN register 312 . The XScramble, YScramble, and ZScramble blocks 302 , 304 , 306 perform the mapping function and output three ( 3 ) sets of actual 16-bit address information 330 into programmable latency logic 332 . Programmable latency logic 332 performs the function that enables the test developer to program a latency between address information passed to the DUT and DUT transmit or response data information. Programmable latency logic 332 outputs forty eight ( 48 ) cycle latency address lines 334 that are input to auxiliary RAM 31 .

With specific reference to FIG. 4 of the drawings, there is shown a detailed block diagram of the XScramble block 302 , in which there are z-bit replacement and fault logic stages, a look-up table and a deactivation stage between the input and output of the XScramble block 302 . The XScramble and YScramble blocks 302 , 304 are practically identical in structure. In order to avoid the unnecessary, only the XScramble block 302 is shown for the purposes of the disclosure of the XScramble and YScramble blocks 302 , 304 . For simplicity of implementation, the discussion begins with components on the left side of FIG. 4 and then continues to the right.

For nomenclature purposes, the X address lines 27 obtained from the address X ALU register 24 are referred to as the logic X address lines 404 . The z-bit replacement stage enables a test developer to replace up to eight ( 8 ) of the most significant logic X address lines 404 with up to eight ( 8 ) of any of sixteen ( 16 ) Z address lines 402 . The X, Y and Z address ALU 24 are handled separately. Enabling bit replacement of some of the X or Y address lines by up to eight ( 8 ) of the Z address lines advantageously provides independent treatment of the two ( 2 ) subsets of the tester channels associated with the x address and y address lines , The test developer may want this feature to use the Z address ALU register 24 for page addressing in a DUT 14 . The mindestwertigen eight (8) logic X-address bits 404 are not processed by the z Bitersatzlogikstufe b. Each of the eight ( 8 ) most significant logic X address bits 404 a, 404 c is processed by respective z-bit replacement logic stages. Under USAGE 404 dung of the ninth actual X-address bits A as veran illustrative example, all sixteen (16) of the Lo-Z gik address bits 402 available for selection and are input to a 16x1-z Auswählmultiplexer 406th Four ( 4 ) bits arranged in the APG_XSCR_Z_BITS_L register 316 , in particular APG_XSCR_Z_BITS_L [0: 3] bits, are assigned as relevant for the ninth actual X address bit 404 a. The four APG_XSCR_Z_BITS_L [0: 3] bits select one of the six ten ( 16 ) available Z address bits 402 , which are to be transferred as a replacement bit 408 for the ninth actual X address bit 404 a at the output of the z-select multiplexer 406 , The ninth actual X address bit 404 a and the selected z bit set 408 are input to a 2x1 z bit activation multiplexer 410 . Bit 2 of the APG_XYZ_SCR_EN register 312 activates or deactivates the scrambling function of the XScramble block 302 independently of the YScramble and ZScramble blocks 304 , 306 . The YScramble and ZScramble blocks 304 , 306 each have a unique bit, APG_XYZ_SCR_EN [1] and APG_XYZ_SCR_EN [0] bits, respectively, which activate or deactivate the scrambling function independently of the other scrambling blocks. The APG_XSCR_Z_EN register 314 contains one bit for each of the eight ( 8 ) upper x-address lines 404 a (404c, which activates or deactivates the z-bit replacement function for each line, and can for each of the upper x-address lines 404 a, 404 c In the disclosed exemplary embodiment, the APG_XSCR_Z_EN [8] bit is assigned to activate or deactivate a z-bit replacement for the ninth actual X address line 404 a, a combination of the ninth bit that is in the APG_XSCR_Z_EN - Register 314 has its origin (ie the APG_XSCR_Z_EN [8] bit) and the APG_XYZ_SCR_EN [2] bit 312 selects either the ninth actual X address bit 404 a or the z bit set 408 to be used as the output 408 of the z Bit enable multiplexer 410. The join operation disables the z-bit replacement function if the scrambling function for block 302 is bypassed. Accordingly, bit 2 of the APG_XYZ_SCR_EN register 312 and the eighth bit of the APG_XSCR_Z_EN register 314 is set true so that the z-bit replacement function can operate. If one of the two activation bits is incorrectly set by the registers 314 and 312 , the logic x address bits 404 a are transferred to the output of the z-bit activation multiplexer 410 . Each different z-bit replacement level is assigned unique four ( 4 ) bits from the APG_XSCR_Z_BITS L and APG_XSCR_Z_BITS_U registers 316 and a unique and respective bit in the APG_XSCR_Z_EN register 314 . Accordingly, the z-bit replacement function can be programmed for each of the eight ( 8 ) most significant bits of the logic X address lines 404 a, 404 c. The collective output of the z-bit replacement logic stage is referred to as the z-selected-X address lines 412 .

The XScramble, YScramble and ZScramble blocks 302 , 304 , 306 all contain the fault logic level. Accordingly, the present discussion is relevant to all scrambling blocks, with only XScramble block 302 being described in detail herein. The interference logic stage has a 2x1 interference multiplexer 414 for each bit of the least significant eight ( 8 ) bits of logic X address lines 404 b and for each bit of the most significant z selected X address lines 412 . The interference level allows the bit values, which are transferred as the logic X address 404 b or the z-selected X address 412, to be canceled by a defined programmed value. Corresponding bit positions in the APG_XSCR_JAM_MASK- 308 and the APG_XSCR_JAM_ADDR register 310 correspond to a respective bit position in the logic and z-selected-X address lines 404 , 412 . The bits in the APG_XSCR_JAM_ADDR register 310 are passed to the fault multiplexer 414 as input. The other input is one of the bits of the logic or z-selected X address lines 404-b, 412th A bit in the APG_XSCR_JAM_MASK- register 308 corresponding to the respective bit in the X-address line selects either the logic / z-selected X address line 404-b, 412, or the bit value of the program in the register 310 APG_XSCR_JAN_MASK to be passed as the output of the noise multiplexer 414 . Each fault level is assigned a unique one of the bits in the APG_XSCR_JAN_ADDR and APG_XSCR_JAN_MASK registers 308 , 310 . Accordingly, the spurious function may be programmed separately for each of the sixteen X address lines 404 . The collective output of the spurious logic stage is referred to as the effective X address lines 416 .

The effective X address lines 416 address an XScramble RAM 418 . The XScramble RAM 418 is a 64K word by 16 bit memory that provides a lookup table for the mapping function according to the convention. Effective X address lines 416 address one of the 64K words, and the word being addressed is passed as the mapped X address lines 420 . The XScramble RAM 418 is programmed with appropriate mapping values prior to executing the test pattern and is programmed at the same time as the APG registers 308-328 .

The deactivation stage is implemented by suitably programming bits 0-2 of the APG_XYZ_SCR_EN register 312 . The test developer can programmatically disable the entire mapping function for one or all of the XScramble, YScramble and ZScramble blocks 302 , 304 , 306 . Each of the three ( 3 ) bits corresponds to the XScramble, YScram ble, and ZScramble blocks 302 , 304, and 306 , respectively. The effective X address lines 406 serve as a feed line for two separate paths in the XScramble block 302 . A path of the effective X address lines 416 addresses the XScramble RAN 418 . The other path of the effective X address lines 416 bypasses the XScramble RAM 418 and is input to a scramble activation stage 422 .

The scrambling activator 422 is a 16 channel 2x1 multiplexer that takes the mapped X address lines 420 from the XScramble RAM 418 and the effective X address lines 416 from the noise multiplexers 414 . Bit 2 of the APG_XYZ_SCR_EN register 312 causes the scramble activator 422 to select either the mapped X address lines 420 or the effective X address lines 404 to be passed as the output 326 of the XScramble block 302 . Bit 1 of the APG_XYZ_SCR_EN register 312 controls the YScramble activator, and bit 0 of the APG_XYZ_SCR_EN register 312 controls the ZScramble activator in a similar manner.

Referring specifically to FIG. 5 of the drawings, a block diagram of ZScramble block 306 in accordance with the teachings of the present invention is shown. As previously mentioned, the ZScramble block 306 does not include the z-bit replacement logic level, but includes the noise logic level. The logic Z address lines 402 and the contents of the APG_ZSCR_JAM_ADDR register 328 are input to sixteen ( 16 ) 2x1 interference multiplexers 502 . The APG_ZSCR_JAM_MASK register 326 selects between the two values for each bit to create effective Z address lines 504 . The effective z address lines 504 address a ZScramble RAM 506 to access memory locations in the ZScramble RAM 506 which become the mapped z address lines 508 . The mapped z address lines 508 are input to a 2x1 ( six ) ( 16 ) channel scramble activator 510 . The effective z address lines 508 are also input to the 2x1 scramble activator 510 with sixteen ( 16 ) channels. The bit associated with the ZScramble block 306 in the APG_XYZ_SCR_EN register 312, that is, the APG_XYZ_SCR_EN [0] bit, selects the effective Z address lines 504 or the mapped Z address lines 508 to be the actual address information 330 to be passed to the output of ZScramble block 306 .

Claims (20)

1. Device for managing address channels in a memory tester, which has the following features:
one or more address registers ( 24 ) storing a plurality of logical address bits ( 27 );
a plurality of spare bits ( 408 ), each spare bit corresponding to one of the logical address bits;
a bit selector ( 410 ) for each combination of a logical address bit and a spare bit, each bit selector independently selecting either the logical address bit or the spare bit, and wherein a collective output of the bit selectors is an effective address ( 416 ); and
a vector processor ( 40 ) for applying the effective address in the tester. 2. The apparatus of claim 1, further comprising a memory ( 418 ) accessed using the effective address ( 416 ). 3. Apparatus according to claim 1 or 2, further comprising the fol lowing feature:
a spare register ( 24 ), the spare register storing a plurality of available bits ( 402 ) that are passed to a plurality of spare bit selectors ( 406 ), each of the spare bit selectors corresponding to each of the respective plurality of spare bits ( 408 ), and wherein each replacement selector selects one of the plurality of available bits to generate each of the replacement bits. 4. The device according to one of claims 1 to 3, wherein one or more second address registers ( 24 ) store the plurality of available bits ( 402 ). 5. Device according to one of claims 1 to 4, in which the content of the one or more address registers is generated algorithmically. 6. The device according to claim 4, wherein the content of the one or more second address register ( 24 ) is generated algo rithmisch. 7. The device according to one of claims 3 to 6, wherein each substitute selector is addressed with a value for specifying which of the available bits ( 402 ) is selected. 8. The apparatus of claim 7, wherein each value for specifying which of the available bits ( 402 ) is selected is stored in one or more selection control registers ( 316 ). 9. The apparatus of claim 8, wherein the one or more selection control registers ( 316 ) are programmable. 10. The apparatus of claim 8 or 9, wherein the selection control register ( 316 ) are independently programmable. 11. The device according to one of claims 1 to 10, wherein the bit selector ( 410 ) can be deactivated. 12. A method for managing address channels in a memory tester, comprising the following steps:
Passing a plurality of logical address bits ( 27 ) to a corresponding plurality of bit selectors ( 410 ) with one logical address bit per bit selector;
Passing a spare bit ( 408 ) per bit selector;
Selecting either the logical address bit or the spare bit, wherein a collective output of the bit selectors is an effective address ( 416 ); and
Addressing a memory ( 418 ) with the effective address. 13. The method of claim 12, further comprising the steps of:
Providing an arbitrary plurality of available bits ( 402 ); and
Selecting each of the spare bits ( 408 ) from the arbitrary plurality of spare bits. The method of claim 13, wherein the step of selecting each of the spare bits ( 408 ) comprises programming a selection control register ( 316 ) with a value corresponding to the spare bit. The method of claim 14, wherein the step of programming the selection control register ( 316 ) further includes a step of assigning one or more unique bits in one or more selection controls to each of the spare bits ( 408 ) from the plurality of available bits ( 402 ) to be selected independently. 16. Device for managing addresses in a memory tester, which has the following features:
a first address source having a plurality of first address bits;
a spare address source having a plurality of spare bits ( 408 );
a selector that independently selects one or more of the spare bits to replace one or more of the first address bits to generate a mapped address word; and
a vector processor for applying signals to a DUT according to the mapped address word. 17. The apparatus of claim 16, further comprising a second address source having a plurality of second address bits, and wherein the selector independently selects one or more of the spare bits ( 408 ) to set the one or more of the second address bits , 18. The apparatus of claim 16 or 17, further comprising a memory ( 418 ) that is addressed using a combination of the first address bits and the spare bits ( 408 ) to generate a mapped address word. 19. The apparatus of one of claims 16 to 18, further comprising a deactivation stage to prevent selection of the one or more replacement bits ( 408 ) to replace one or more of the first address bits. 20. Device according to one of claims 16 to 19, further comprising an interference stage in order to cancel the selection of the one or more replacement bits ( 408 ) with an interference address.