ITRM20010549A1 - METHOD AND APPARATUS FOR HANDLING THE ADDRESS INFORMATION IN A MEMORY TESTING DEVICE. - Google Patents

Description

Description of the industrial invention entitled "METHOD AND APPARATUS FOR HANDLING THE ADDRESS INFORMATION IN A MEMORY TESTING DEVICE"

DESCRIPTION

Foundation

Electronic devices and their capabilities have grown enormously in common in today's life. Along with personal computers in the home field, many individuals carry more than one productivity tool for various and different purposes. Most personal electronic productivity devices include some form of non-volatile memory. Cell phones use non-volatile memory for the purpose of storing and maintaining telephone numbers and configurations programmed by the user when the power is turned off. PCMCIA cards use non-volatile memory to store and maintain information even when the card is removed from its slot in the computer. Many other common electronic devices also benefit from the long-term storage capability of non-volatile memory in unpowered assemblies.

Manufacturers of non-volatile memories who sell to manufacturers of electronic devices require testing devices to exercise and verify the operation of the memories they produce. Due to the volume of non-volatile memories that are built and sold at very low prices it is very important to minimize the time it takes to test a single part. Non-volatile memory acquirers require memory manufacturers to provide high shipping yields due to the cost savings associated with the practice of incorporating memory devices into more expensive assemblies with minimal or even no testing. Consequently, the memory testing process must be effective enough to identify a large percentage of non-conforming parts and preferably all non-conforming parts in a single testing process.

As non-volatile memories become increasingly large, denser and more complex, test devices must be able to handle the increased size and complexity without significantly increasing the time they require for testing. As memories evolve and improve, the testing device may be able to easily acknowledge the changes made on the device. Another element specific to non-volatile test memories is that repeated writes to the memory cells can degrade the performance of the entire life of the part. Non-volatile memory manufacturers have responded to many testing requests by building special test modes for memory devices. These test modes are not used at all by the memory purchaser but can be accessed by the manufacturer to test all significant parts of the memories in the shortest possible time and as effectively as possible. Some non-volatile memories are also capable of being repaired during the testing process. The testing device should therefore be able to identify: a need for repair; a place of repair; the tripod needed repair; and must therefore be able to perform the appropriate repair. This repair process requires that a test device be able to detect and isolate a non-specific non-conforming part of the memory. In order to take full advantage of special test modes as well as repair functions it is useful for a test device to be able to run a test program that supports conditional branching based on an expected response from the device.

From a conceptual perspective, the procedure for testing memories is an algorithm procedure. As an example, typical tests include sequential incrementing or decrementing memory addresses by writing 0s and 1s to memory cells. It is customary to refer to a collection of 1s and 0s that are written or read during a memory cycle as a "reader" while the term "pattern" refers to a sequence of vectors. It is conventional for tests to include writing configurations in the memory space such as "checkboards", "walking 1" and butterfly configurations. The test developer can more easily and effectively enter a program to generate these configurations with the help of algorithm constructs. A test configuration that is algorithm consistent is also easier to "debug" and use logical methods to isolate parts of the configuration that are not as compliant as expected. A test configuration that is generated by an algorithm that uses instructions and commands that are repeated in programming cycles consumes less space in the memory of the test device. Accordingly, it is desirable to have an algorithm test pattern generation capability in a memory test device.

Accurate placement and detection of a signal edge is also a consideration in the effectiveness of a non-volatile test device. In order to capture parts that generally conform to a median while not conforming to the specified margins, a non-volatile memory tester must be able to accurately place each time-relative signal edge on another edge. signal. It is also important to be able to accurately measure at what point in time a signal edge is received. Consequently, a test device of a non-volatile memory should have sufficient flexibility and control of the timing and arrangement of the stimuli and responses from the device under test (memory).

Memory testing devices are said to generate transmission vectors which are applied (stimuli) to the DUT and receive vectors which are expected to return (response). The algorithm logic that generates these vectors can generally do this without worrying about how a particular bit in a vector is to be placed or taken from a particular signal pad in the DUT. At this level it is almost as if there is a certainty that the adjacent bits in the vector should end as physically adjacent signals on the DUT. Life should be like this!

In reality the correspondence between the bits in a vector at the "conceptual level" and the actual signals in the DUT are suitable to be quite arbitrary. If nothing is done to prevent this, it may be necessary to traverse one or more probe cables as they descend from a periphery to make contact with the DUT. positions of the bits in the transmission vector before they are applied to the DUT, so that the task of making physical contact is not burdened by the crossings. Receive readers are applied correspondingly in a reverse mapping mechanism before being considered. In this way the generation of an algorithm vector and the comparison mechanisms can be enabled to ignore this whole detail. As another example of what such mappers and reverse mappers can do, consider the case where a different event of the same type as the DUT is placed on the same wafer, but with some mirror symmetry rotation, in order to avoid wasting space on the wafer. . These practices also have an effect on the correspondence between the position of the bits of the vectors and the physical position of the signals, but which can be overridden by appropriate mappings and inverse mappings. It will be noted that the mappings and reverse mappings required for these situations are, once a particular DUT is identified, static and do not need to change during the course of testing for this particular DUT.

For some types of memories, effective testing requires the manipulation of one set of address line bits separated by another set of address line bits. In the test devices of the prior art the generation of algorithm configuration the task was relatively simple since the address lines were defined as two separate groups and were managed on a bit by bit basis. An example of a type of memory that uses this kind of addressing is a memory that maintains the organization of multiple blocks of memory cells in a page addressing format where the page addressing uses some of the most significant bits of the address and memory word addressing uses some of the more significant address lines. In order to take full advantage of the algorithm configuration generation for testing these types of memory, however, there is a need, for a test device that provides a simple solution to selectively group bits in the address lines for independent configuration generation. of algorithm.

Summary

According to an aspect of the invention, an apparatus for managing address channels in a memory test device has one or more address registers which store a plurality of logical address bits and a plurality of substitution bits, each substitution bit corresponding to one of the logical address bits. The apparatus also has a bit selector for each logical address bit and a replacement bit combination and each bit selector independently selects either the logical address bit or the replacement bit. A collective output of the bit selectors and an effective address for memory testing purposes. A vector processor applies the effective address in the test device.

According to another aspect of the invention, a method for managing the address channels in a memory testing device comprises the steps of presenting a plurality of logical address bits to a respective plurality of bit selectors with one logical address bit per selector of bits and a replacement bit for bit selector. The method then selects either the logical address bit or the replacement bit, a collective output of the bit selectors being an actual address. The actual address is used for DUT memory addressing purposes.

Advantageously, a test device according to the teachings of the present invention offers additional flexibility and efficiency in the development of test configurations as compared to prior art test devices. Brief description of the drawings

Figure 1 is a simplified block diagram of an extensively reconfigurable non-volatile memory test device constructed in accordance with the invention.

Figure 2 is an expansion of the simplified block diagram of the test device of DUT 6 of Figure 1.

Figure 3 is a block diagram of the address mapper 29 shown in Figure 2.

Figure 4 is a block diagram of the XScramble 302 portion of the address mapper 29 shown in Figure 3.

Figure 5 is a block diagram of the ZScramble 306 portion of the address mapper 29 shown in Figure 3.

Detailed description

We now refer to figure 1 in which a simplified block diagram 1 of a non-volatile memory test system built according to the principles of the invention is shown. In particular, the system shown can test simultaneously with up to sixty-four test points each, up to thirty-six individual DUTs (devices under test) at once, with supplies for reconfiguration to allow elements of a collection of test assets to be kept together. to check DUTs with more than sixty-four test points. These test points can be locations on a part of an integrated circuit wafer that has not yet been cut and packaged, or they can be the pins on a packaged part. The term "test point" refers to an electrical location where the signal can be applied (eg power supplies, clocks, data inputs) or where a signal can be measured (eg a data output). We will follow the industrial practice of referring to test points as "channels". The "collection of test assets to be joined together" referred to above can be understood as up to thirty-six test sites, where each test site includes a test site controller (4), a test site DUT (sixty-four channels) and a collection (sixty-four channels) of pin electronics (9) that make a real electrical connection with a DUT (14). In the event that the execution of the DT test requires sixty-four or less channels, a single test site is sufficient to perform the tests on this DUT, and let's say, for example, that the test site # 1 (as shown in the figure 1) forms or functions as a "single site testing station". On the other hand, when some form of so-called reconfiguration is performed, two (or more) test sites are "joined" together to function as a larger equivalent test site that has one hundred twenty-eight channels. Consequently, again referring to an example shown in Figure 1, we can say that test sites # 35 and # 36 form a "two site test station".

To briefly consider the opposite case, it could be assumed that an entire test site is required to test a single DUT or that a single test site can test all but a single DUT. Suppose a wafer has two (probably, but not necessarily) adjacent matrices, of which the sum of the test channel requirements is sixty-four channels or less. Both DUTs can be tested using a single test site. What makes this possible is the general purpose programmability of each test site. A test program run by the test site can be written so that part of the test site resources tests one of the DUTs while another part is used to test the other DUT. After all, we assume that if we had a third DUT that was the logical union of the first two, then we would be able to test the third DUT with a single test site, so we should be able to similarly test its "DUT components. "as it is. The only difference is to individually keep track of whether the two "component DUTs" pass or fail testing, as opposed to a unified response for the "third DUT" (ie there is an output concerning which part of the "third DUT" "did not pass the test). This "single site test station" capability is largely conventional and we remember it here for completeness and to warn of potential confusion and misunderstanding when comparing with the notion of joining two or more test sites. between them.

Were it not for this notion of reconfiguration there would be no gap between a test site and a test station and we could do without one of the terms. In fact, however, it will be appreciated that the number of test stations does not have to equal the number of test sites. In the past, the numbers could have been different as test sites were split to create multiple test stations (DUTs not complex enough to consume an entire test site). Now, however, the difference could also be due to the test sites that have been joined together to form multiple site test stations (DUTs too complex for a single test site).

To continue then, a test system controller 2 is connected via a system bus 3 to thirty-six test site controllers whose names end in suffixes # 1 to # 36 (4a-4z). (It is true that the a-z indices range from one to twenty-six and not to thirty-six but this minor deficiency seems preferable for numerical indexes over numerical reference characters which could potentially be confusing.) The test system controller 2 is a computer (e.g. a PC running as an NT) which executes a suitable test system control program, during the non-volatile memory test task. The test system control program represents the highest level of abstraction in a hierarchical division of labor (and complexity) to accomplish the desired test. The test system controller determines which programs are to be managed by the different test sites as well as monitoring a robot system (not shown) that moves the test probes and DUTs as needed. Test System Controller 2 can function in a way that supports the notion that some test sites are programmed to function as single site test stations, while others are joined together to form multiple site test stations. Clearly, in such circumstances there are different parts that are tested and it is highly desirable that different tests be used for the different parts. Similarly, there is no requirement that all single site testing stations should test the same part style, nor is there such exquisite for multiple site testing stations. Consequently, the test system controller 2 is programmed to issue the commands to accomplish the required test site union and then call the appropriate command programs for the various test stations in use. The test system controller 2 also receives the information about the results obtained from the tests, so that it can take the appropriate action to unload the defective part and so that it keeps the "logs" for the various analyzes that can be used to control, for example, production processes in a factory plant.

The test system itself is a fairly large and complex system and it is common for it to use a robot subsystem to load the wafers onto a platform which then sequentially places one or more future matrices under the probes connected to the electronics at pin 9, after which these future dies (the wafer has not been cut yet) are tested. The testing system can also be used to test packaged parts that have been loaded onto a suitable stand. There is (as will be shown below) at least one test site controller associated with each test station, regardless of how many test sites are used to form this test station or how many test stations exist on a test site. A test site controller is an embedded system that may be an Intel i960 processor with thirty-six to sixty-four MB of combined program and data memory running on a proprietary operating system called VOS (VersaTest O / S), which has also been used in earlier products for testing non-volatile memories (eg Agilent V1300 or V3300). For now, we will only consider the situation for single site test stations. By way of a defined example suppose that the test site # 1 is functioning as test station # 1 and that it has to test the particular WHIZCO n.

0013. The test regime involves roughly a hundred different types of tests (variable voltage and detection levels, pulse widths, edge positions, delays, as well as a large amount of simple storage and then retrieval of selected configurations of information), and each type of testing involves many millions of individual memory cycles for the DUT. At the highest level, test system operators instruct Test System Controller 2 to use Test Station # 1 to initiate testing of WHIZCO 0013. In due course Test System Controller 2 tells site controller to test # 1 (4a) (which is an embedded [computer] system) of running the associated test program, ie, TEST_WHIZ_13. If this program is already available within the Test Site Controller # 1 environment then it is simply run. If not, it is supplied by the testing system controller 2.

Now in principle, the TEST_WHIZ_13 program should be entirely self-contained. But if so, it should at least certainly be quite large and it may be difficult for the system processor embedded within the test site controller 4a to run fast enough to produce the tests at the desired speed or even at a speed that is uniform. from one DUT memory cycle to the next. Consequently, the low-level subroutine type activities that generate the address sequences and associated data to be written or expected by a read operation are generated as required by a programmable algorithm mechanism located in the test device. DUT 6, but which works in synchronism with the program that is executed by the embedded system as a test site controller 4. This can be thought of as exporting some activity similar to a low-level subroutine and the task of initiating memory cycles of DUT from a mechanism (DUT's test device) that is closer to the hardware environment than DUT 14. Generally speaking, so whenever test system controller 2 equips a test site controller with a test program testing also provides the DUT testing device associated with the appropriate low-level implementation routines (specific for ese mpio for the memory being tested) necessary to carry out the complete activity described or necessary for programming by the test site controller. Low-level implementation routines are referred to as "configurations" and they are generally named (just as functions and variables in high-level programming languages have their own names).

Each test site controller #n (4) is coupled to the associated DUT test device #n (6) via a site test bus #n (5). The test site controller uses the site test bus 5 to control both the operation of the test device of DUT and to receive information from it about the test results. The test device of DUT is capable of generating at high speed the various memory cycles of DUT which are involved in the testing regime and it decides whether the results of a reading memory cycle are as expected. It actually responds to commands or operational codes ("named configurations") sent by the test site controller by initiating the corresponding useful sequences of the read and write DUT memory cycles (i.e., it performs the corresponding configurations). Conceptually, the output of the testing device of DUT 6 is the stimulus information to be applied to the DUT, and also accepts the response information from it. This stimulus / response information 7a passes between the DUT test device 6a and an electronics assembly at pin # 19a. The 9a pin electronics assembly supports up to sixty-four probes which can be applied to the DUT 14.

The stimulus information mentioned above is just a sequence of bit configurations in parallel (ie a sequence of "transmission vectors" and "reception vectors" expected) expressed according to the voltage levels of some family of logic devices used in the testing device of DUT. There is a configurable mapping between the bit positions within the stimulus / response and the probes on the matrix, and this mapping is understood by the DUT 6 test device. The individual bits are corrected in their timing and edge arrangement but in addition at mapping they may also need voltage level scaling before they are applied to the DUT. Similarly, a response originating in the DUT following a stimulus may require buffering and libellus (inverse) scaling before it can be considered suitable for feedback on the DUT testing device. These level scaling tasks are the responsibility of pin 9a electronics. The pin electronics configuration needed to test a WHIZCO 0013 does not work similarly to test a part of ACME Co., and perhaps not even with another WHIZ Co. part.So you will notice that the pin electronics assembly must also be configurable; this configurability is the function of the PE Config 8a lines.

The above concludes a brief architectural overview of how a single test site is structured to test a DUT. Let us now return to the details that arise when there are many test sites to operate with. We will preliminarily describe a preferred embodiment for building a test system having multiple test sites. In many respects some of the information we need to describe is the details of choice based on user preference market studies and cost-benefit analyzes. Be that as it may, to build one of these things you need to make definite choices and once that is done there are particular consequences that are visible throughout the entire system. It is believed that it is useful to describe at least in an overview the major profiles and hardware properties of the test system. While some of these properties are contingent a knowledge of them will nevertheless assist in the appreciation of the various examples used to illustrate the invention.

So let's start by considering four rather large board cages. Each board cage has, in addition to the power supplies and water cooling (fans which can be a source of contamination in a clean room environment), a motherboard, a front and a rear shelf. Up to nine assemblies can be arranged in each card cage. Each assembly includes a test site controller, a DUT test device and a pin electronics. We will describe general profiles of how test site controllers are joined together, which implies some buses used to create daisy chains.

A brief description concerning the term "daisy chain" is perhaps appropriate. Let us consider the system elements A, B, C and D and suppose that they must be daisy-chained together in this order. We can say that there is information or a control path that leaves A and goes to B, that B can selectively pass in traffic which then leaves B and goes to C and that C can selectively pass through traffic and therefore goes to D This same type of arrangement may exist for traffic in the other direction as well. Daisy chains are often used to create priority schemes; we will use them to create "master / slave" relationships between the various test site controllers. We will refer to these daisy chained style communication arrangements with the suffix name "DSY", instead of "BUS". So we will refer to a DSY command / data instead of a data / BUS command. Now the notion that the "enter B is selectively passed forward" information may suggest that the traffic is repeated on a separate set of connectors before being passed forward. This could be the case but for performance reasons a regular bus is more likely to have addressable entities. By means of a programmable address mapping arrangement and the ability to arrange the parts of the test site controllers downstream in the "dormant" state, the single bus can be made to appear logically (this is functional) with a plurality of daisy chains. Finally it will be noted that daisy chains are high performance paths for control command information and that if they were not there, we could not wait for a master / slave combination (multi-site test station) to work that fast. as indeed a single test site does. For the benefit of daisy chain performance the various DSYs do not release their respective card cages. The effect of this decision is to place some limits on which test sites (and also on how many) can be linked together. In principle there is no fundamental need for this limit nor is there a genuine lack of technical practicality involved (it could be); it is simply thought that since nine test sites already exist in a board cage, the extension of the DSY adds a significant cost for a relatively small additional benefit.

To summarize our description of Figure 1, we then consider the various test site controllers 4a-4z that can populate the four board cages, each with nine test site controllers. Let's denote them as 4a-4f, 4g-4m, 4n-4t and 4u-4z. (It does not matter, as illustrated above, that these are nominally only twenty-six indices, the reader is encouraged to imagine that there are ten other index symbols somewhere else.) A DSY CMD / DAT 17a (Commando and daisy chain of data) interconnects 4a-4f test site controllers located in a board cage while a CMD / DAT DSY 17b interconnects 4g-4m test site controllers in another card cage. The same arrangement exists for the remaining board cages and test site controllers 4n-4t and 4u-4z respectively. We mentioned earlier that the DSY does not leave the card cages as the tail end of a bus that actually forms the DSY does not leave a card cage and becomes the head of the next segment in another card cage. otherwise System Bus 3 from Testing System Controller 2 goes to all Test Site Controllers and each is able to become a Master and the head of a DSY segment does not leave the board cage.

The CMD / DAT DSY 17a-d we are describing exists among the various 4a-4z test site controllers. There is a similar arrangement for the SYNC / ERR DSY 18a-18d and DUT 6a-6z test devices. The error synchronism information conveyed by the SYN / ERR DSY 18 allows the DUT test devices to operate in unison. These two daisy chains (17 and 18) carry slightly different types of information, but each exists as a part of the same general mechanism for joining one or more test sites together at a test station.

We now return to a description of Figure 2, which is an expansion of the simplified block diagram in the test device DUT 6 of Figure 1, of which up to thirty-six can exist. It is sufficient at the moment to describe only one case of them. A look at Figure 2 will show that it is fairly populated with material; especially so far a "simplified" block diagram. Something of what is in the DUT 6 test device is represented in the block diagram is functionally quite complicated and not available in the "off the shelf" form. Here it is appropriate to make two points. First, the fundamental purpose of including Figure 2 is to describe the fundamental properties of an important operating environment within the non-volatile memory test system 1. The invention (s) which are fully described in connection in figure 3 and in the following figures are either expansions of mechanisms predisposed in the following description of figure 2 or are new mechanisms whose motivation premise is found in figure 2. In any case, since this is written it is not exactly known which of this comes before the reader. The current goal is to provide a simplified yet informative starting point for numerous different detailed descriptions of various preferred embodiments, so that each of these can be as concise as appropriate (as opposed to a specific "jumbo" describing everything. concerning each different invention). The second point is that the expanded or expanded material, while in general total agreement with Figure 2, may contain information that does not exactly "coincide" with the simplified version. This does not mean that there has been a mistake or that things are fatally inconsistent; the problem arises from the fact that it is sometimes difficult or impossible to simplify something that is the exact miniature image. The situation is rather like the maps. A standard-sized street map of Colorado shows that when you go east on 1-70 you can go north on 1-25 in Denver. It looks like a left turn. And while it is used to be a real curve to the left, it is in fact not a detailed map of this intersection showing a sequence of component curves and intervening road sections. But no one would say that the standard-size road map is wrong; it is correct for its level of abstraction. Similarly and despite its fairly busy aspect Figure 2 is indeed an operational simplification at a medium level of abstraction but some that look like left curves are not simple left curves at all.

As shown in figure 1 the main input of the test device of DUT 6 is a case of the test site bus 5 which originates from a test site controller 4 which is associated with the case of the test device of DUT 6 which is of interest. The Test Site Bus 5 is coupled to a micro controller sequencer 19 which can be like a special purpose micro processor. It takes the instructions from a stored program of program memory, which can be internal to the sequencer of micro controller 6 8PGM SRAM 2 =) or external to it (EXT. DRAM 21). Although these two memories appear to be addressed by what is essentially a logically common address 63 which serves as a program counter (or instruction fetch address), and also may be a programming source to execute, note that: (1 ) only one of the memories executes the instruction picking memory cycles during any time picking; and (2) in effect they are addressed by electrically different signals. SRAM is fast and allows genuine random access but consumes appreciable space within the micro sequence controller 19 (which is a large IC) so it is limited in size. External DRAM can be provided in sizable amounts of adjustable values but is fast only when subjected to access to sequential blocks that involve linear execution and no branching. The programming in the SRAM 20 which is mostly heavily formed by algorithms, while the EXT. DRAM 21 is best suited for material not easily generated by algorithmic processes, such as initialization routines and random or regular data.

The instruction word executed by the micro controller sequencer 19 is quite large: two hundred and eight bits. It consists of thirteen fields of sixteen bits. These fields often represent instruction information taken for mechanisms that are outside the appropriate microcontroller sequencer. These fields are dedicated to their associated mechanisms. One set of ALU INSTRUCTIONS 22 instructions are applied to a collection of eight sixteen-bit 24 ALUs, while the others are distributed into various other mechanisms distributed through the DUT test device. This latter situation is represented by the lines and the legend "VARIOUS CONTROL VALUES AND INSTRUCTIONS" 42.

The eight sixteen-bit ALUs (24) each have a conventional repertoire of arithmetic instructions embedded around the sixteen-bit associated result registers (each ALU has several other registers) these result registers and their associated ALUs serve to generate the address components XY and Z 27 which are combined in various ways into a complete address to be provided to the DUT. Two more of the eight ALU registers (DH and DL) are provided to assist in the creation of the algorithms of the thirty-two bit patterns 28 which are split between a more significant part (DH) and a less significant part (DL). The three ALU registers (A, B, C) are used as counters and contribute to the production of the various 25 program control FLAGs which assist with program control and branching in completing some programmatically specified number of iteration or other numerical conditions . These program control FLAGs 25 are sent back to the micro controller sequencer 19 where they influence the value of the instruction pickup address in a manner familiar to those of micro processors. There are also various other 55 FLAGs that can be used to carry out program branching. These originate with various other mechanisms within the test device of DUT 6 which are controlled by the different fields of the picked instruction word. A specific add-on FLAG is explicitly shown as a separate detail: VEC_FIFO_FULL 26. In another drawing that has a less detailed appearance it may be incorporated along with other FLAGs 55. We have separated it to assist in illustrating one aspect of an operation of the micro controller sequencer 19.

What VEC_FIFO_FULL does is (temporarily) stop further program execution via the micro controller sequencer 19. There are many stages of "pipeline" between the instructions taken from the micro controller sequencer 19 and the mechanism that ultimately handles the test vectors so that they are applied to the DUT. In addition, a part of the baggage accompanying a carrier when it moves to be applied to the DUT and information concerning the speed of a possible vector application or the duration of each carrier. Thus the vector application rate to the DUT must be constant and in particular a group of vectors may take longer to apply than they require for generation. The micro controller sequencer simply performs programming at its maximum speed. But clearly on average, the "vector consumption" rate as it is must be equal to the "vector production" rate, unless the pipeline needs to be almost boundlessly elastic. There is a FIFO vector 45 at the output of the address counter 29 described below, and it serves as an elastic capacity of the pipeline. The VEC_FIFO_FULL signal is used to prevent the limited number of stages in the pipeline from being exceeded, causing a temporary cessation in the production of new vectors at the end of the pipe head.

To continue the (three times sixteen and equal to forty-eight bits) X, Y and Z components of address 27 are applied to an address mapper 29, whose output is an almost arbitrary pre-selected arrangement of each address in the address space a forty-eight bit sorted. As a starting point for evaluating this, let's assume for a moment that address mapper 29 is a memory that has fully populated a forty-eight-bit address space and that contains a forty-eight-bit value in each address, (temporarily it doesn't matter that a such memory would currently be the size of a large chiller). Given such a memory, a lookup table could be created which could map any address applied to another, arbitrarily selected, a 48-bit value which could then be used as a replacement address. The reason such an address mapper is desirable is that the X, Y, and Z address components generally have a use of meaning in context and a particular internal architecture of the DTU that is most likely not augmented with a large linear decoder. The notions of row, column and layer, block or page can be very useful for the test engineer, and failures that occur in locations that are physically close to each other can result in corresponding proximity in the X, Y and Z addresses. configurations in the test results can be valid in appreciating what is wrong and attempting to fix, if a design level or production level of reproduction of a part to short circuit a faulty section operation with that of a spare section. Two details arise from this supposition. The first is to equalize the forty-eight bits up to the real number of bits (i.e. thirty-two or perhaps sixteen) to be applied to the DUT. We will briefly mention how equalization is done and this is strongly a matter of taking many bits from X, many bits from Y and the rest from Z. But not entirely and this is the second hypothesis, since some addresses could be located within a circuit which is a ' mirror image left for right (or left for right and top for bottom) of another circuit section. This has the effect of constituting what the bits mean, as long as the sequential address values are in physical order within this circuit. This chip arrangement property can occur many times and it can be the case where as a group of bits for example Y are interpreted, it can depend on the accompanying value of some others, i.e., the Z bits. The address mapper 29 is provided to allow X, Y, and Z addresses to be "repacked" as they were, to reflect this kind of thing for the benefit of those who would like to test memories having such internal architecture arrangements. As regards what is currently being done, the address mapper 29 is constructed with a fairly large number of interconnected multiplexers. It cannot implement the completely arbitrary lookup table behavior of a fully populated memory decoding scheme as was temporarily assumed before for illustration purposes. However, it can reconstitute the sub fields of the components of the X, Y, and Z addresses as needed, particularly since there is yet another mechanism that will do the equalization down from forty-eight bits to the required real number. The address mapper 29 also contains three sixteen-bit lookup tables (addresses) which allow to realize an arbitrarily limited mapping within local fields.

The mapped address output 30 of the address mapper 29 is applied as an address to an Aux RAM 31 and an error pickup RAM 32, which while they have separate functions, may nevertheless be selectable parts implemented in a larger global RAM. The mapping address output 30 will also be applied to an input on an Addr circuit. Bis Select 37 which is described below.

Let us consider Aux RAM 31. Its function is to hold data configurations 33 and addresses 34 that can be applied to the DUT. These are logically separate outputs from Aux RAM 31, as they are treated somewhat differently and used in different places, (Aux RAM 31 is not a dual "port memory", but is preferably made up of some banks whose outputs are applied to MUX). In dealing with this it may be that the stored data 33 is held in one bank or range of addresses by the Aux RAM 31 while the stored addresses 34 are held in another. Also we have not shown an explicit mechanism for writing to Aux RAM 31. This is accomplished by a routed bus operation initiated by a test site controller 4 on the order of the program that is running, (there is an "under the flooboards "as if it were, a bus of" utility services "called a" ring bus "[not shown, as if it immensely groups the drawing] which goes just for everything in figure 2).

The error retrieval RAM 32 is addressed with the same address that is applied to the Aux RAM 31 and stores or retrieves the information about the errors, which operations are performed in conjunction with a post decoding circuit which will be described later. As with the paths 33 and 34 from Aux RAM 31, paths 61 (in the error sampling RAM) and 62 (from the error sampling RAM) are preferably MUX-submitted outputs from a multiple-bank memory (the sampling RAM). error 32) according to the configuration information distributed by the ring bus (not shown).

Note that the data MUX 35 has as inputs the stored data output 33 to the Aux RAM 31 as well as the data 38 from the DH and DL registers in the ALU collection 24. Data MUX 35 selects which of these inputs (28, 32) to present as its output 38, which is then applied as one of two vector components to a transmit reader / serializer / receive vector comparison data circuit. 40 (another component is output 39 of the Addr.Bit Select circuit 37). The circuit 40 can perform three functions: assembling the vector components (38, 39) in an ordered logical representation of an entire vector to be applied (transmitted) to the DUT; apply an arbitrary dynamic correspondence (mapper) between the ordered bits of the logical representation of the transmission vector and the real number of physical channels of the electronics to Pin (i.e. which probe point) that will be in contact with the DUT instead of this signal ( i.e. this bit in the vector); and cooperating with the compiler in dividing an integer logical vector into elements to be applied separately and in order (serialization) for DUTs that admit such a thing. Which of these functions is performed is determined by the control signals from a SRAM 41 which is also addressed according to a field in the 208-bit instruction taken from the sequencer of micro controller 19. The output of the circuit 40 is a vector of up to sixty-four bits 44 which is applied to a FIFO vector 45 which when full generates the signal VEC_FIFO_FULL 26 whose meaning and use have been described above. The vector on top of the FIFO vector 45 is removed therefrom upon receipt of a VEC_FIFO_UNLOAD signal 47 originating in a period vector 49 (which will be briefly described). Such removed vectors (46) are applied to a timing / formatting and comparison circuit 52 which is connected to the DUT through the associated case of the Pin 9 electronics. That is, each case of the Pin 9 electronics receives the transmitted and received 7 vectors. and the electronics configuration information at Pin 8 from its associated timing / formatting and comparison circuit 52.

The timing / formatting and comparison circuit 52 has an internal SRAM 54 addressed by the same instruction address ("A" in the small circle) since it is the program SRAM 20 of the micro controller sequencer 19. (An external DRAM 53 can be used instead of the internal SRAM 54). Internal SRAM 54 (or external DRAM 53) assists in producing the driving and comparison cycles. Drive cycles apply a transmission vector to the DUT. The comparison cycles receive a vector presented by DUT and examine it to determine if it matches the comparison data provided previously. Both drive and compare cycles are adjustable for their duration, if and when a load is applied, and when data is latched or strobed. The comparison produces a sixty-four bit value 56 which is applied to the mapper towards the receive / deserializer vector 57, whose function can be considered to be the logical inverse of the circuit 40. (the operation of the circuit 57 is controlled by a SRAM 58 which corresponds to the control of the circuit 40 by the SRAM 41). In turn, the output 59 of the circuit 57 is applied to the post decoding circuit 60. It is generally sufficient to say that the post decoding circuit 60 can inspect both the incoming error information 59 and the error information by programmatic criteria. stored (previously) 60 (stored in the error sampling RAM) to produce a condensed and more easily interpretable error information which can then be stored again in the error sampling RAM 32 via path 61. An example would serve to create a counting how many times an error has occurred within a particular address range, which information can be useful in deciding when to attempt to engage in a chip repair by enabling replacement circuits.

Let us now return to the period generator 49 and its associated timing SRAM 51. These respond to an eight-bit signal T_SEL 43 which, for each 208-bit instruction taken from the microcontroller sequencer 19, determines a duration for the associated operation of the timing / formatting and comparison circuit 52. T_SEL 43 is the element of the various and control values and instructions 42 which are represented by the different fields within the picked instruction. Because an eight-bit value can represent or encode two hundred and fifty-six different things. In this case these "things" are twenty-eight bit values stored in the timing SRAM 51 and which are addressed by T_SEL. Each addressed twenty-eight bit value (23) specifies a desired duration with a resolution of 19.5 picoseconds. The sequence of the addressed twenty-eight bit duration values (23) is stored in a FIFO of period 50 so that the individual elements of this sequence are retrieved and applied in synchronism with the retrieval of their intended corresponding vector, which is stored in the FIFO of vector 45.

A coarse timing value field in the oldest input in FIFO 50 conveys the duration information with a resolution of 5 nsec, and produces from it a signal VEC_FIFO_UNLOAD 47 which transfers the next transmission vector from the vector FIFO 45 to the circuit Formatting and Comparison 52. An accompanying TIMING REMAINDER 48 signal is also applied to circuit 52. This is where the last resolution down to 19.5 picoseconds is realized.

Some memories consist of multiple blocks of memory that are replicated on a single matrix to realize the total memory space in a memory device. As is often the case, replicated blocks are mirror images of each other on a vertical or horizontal axis or both, and these replicated blocks can be replicated further.

It is often effective to dial a single tester for one of the memory blocks and repeat it for the replicated blocks. While the test configuration is relevant for each block, it is not possible to simply reuse a single test device and all memory blocks since the memory blocks are images of each other. Consequently, the replicated blocks have an impact with a test for the device as the address bits can follow a different sequence for each block. The different sequences, however, are related to each other. The "scramble" feature allows a test developer to reuse test configurations for different memory blocks by programming only one scramble function. The test configuration itself is reused, and the scramble function, which is separated by algorithms from the test configuration program instructions, performs the administrative tasks related to adapting the test configuration for each replicated memory block. Some memories are also organized into pages. Pages are addressed using some subsets of address bits. The d scramble function is improved by allowing algorithmic control of some bits separately from other address lines and thus allows the substitution of these bits for the regular address bits that are input into the scramble function. With specific reference to Figure 3 of the drawings, a mid-level detailed view of the address mapper 29 shown in Figure 2 of the drawings is shown in which the blocks of XScramble 302, YScramble 304 and ZScramble 306 each receive 16 bits of address from the registers of ALU of address X, address Y and address Z respectively 24. Consequently, the forty-eight (48) address lines shown as reference number 27 in Figure 2 are separated into three (3) groupings of 16-bit logical address lines in Figure 3. The XScramble, YScramble and ZScramble 302, 304, 306 blocks also receive the information originating in the APG registers. The programmability of the APG registers provides the programmability features of the test device functions. The values for each of the APG registers are stored as part of the compiled object code in a test configuration and are downloaded to provide initial values before a test configuration is run. It is also possible, although not common, to change the values in some of the APG registers while running the test configuration. There are a large number of APG registers in the test device and only those registers which are relevant to the present invention are described here. The APG registers relevant to the XScramble block 302 include a register 308 APG_XSCR_JAM_MASK [0:15], a register 310 APG_XSCR_JAM_ADDR [0:15], the bit 2 of an APG_XYZ_SCR_EN register 312, a register APG_XSCR_Z_EN [0: 7 registers] APG XSCR Z BITS L [0:15] and APG XCR Z BITS U [0:15] 316. The APG registers relevant to block YScramble 304 include one register APG_YSCR_JAM_MASK [0:15] 318, one register APG_YSCR_JAM_ADDR [0:15 ] 320, bit 1 of a register APG_XYZ_SCR_EN 312, a register APG_YSCR_Z_EN [0: 7] 322 and the registers APG_YSCR_Z_BITS_L [0:15] and APG_YSCR_Z_BITS_U [0:15] 324. The APG registers relevant to the block ZScramble 306 APG_ZSCR_JAM_MASK [0:15] 326 and the register APG_ZSCR_JAM_ADDR [0:15] 328, and bit 0 of the APG_XYZ_SCR_EN 312 register. The XScramble, YScramble and ZScramble blocks 302, 304, 306 perform the output mapping function ( 3) 16-bit real address information sets 330 in programmable latency logic 332 The programmable latency logic 332 performs the function which allows the test developer to program a latency between the address information presented to the DUT and the DUT transmits or responds to the data information. The programmable latency logic 332 outputs forty-eight (48) cycle latency regulated address lines 334 which are input into the auxiliary RAM 31.

With specific reference to Figure 4 of the drawings, a detailed block diagram of the XScramble block 302 is shown in which there are the z-bit substitution and jamming logic stages, a search table and a disabling stage between the input and the output of the XScramble 302 block. The XScramble and YScramble 302, 304 blocks are virtually identical in structure, therefore, to avoid unnecessary redundancy, only the XScramble 302 block is shown and described for the purpose of describing the XScramble and YScramble 302, 304. For simplicity of illustration the description begins with the components on the left of figure 4 and proceeds on the right.

For nomenclature purposes the X address lines 27 that are received by the X address ALU register 24 are referred to as the X address logic lines 404. The Z bit substitution stage allows a test developer to substitute up to eight (8 ) of the most significant logical X address lines 404 with up to eight (8) of any of sixteen (16) Z address lines 402. The X, Y and Z address ALUs 24 are handled separately from each other. Allowing bit substitution of some of the X or Y address lines up to eight (8) of the Z address lines advantageously provides independent manipulation of two (2) subsets of the test device channels which are dedicated to the X address lines and of address Y. The test developer may want this feature in order to use the ALU register of address z 24 for page addressing in a DUT 14. The eight (8) bits of least significant logical X address 404b are not processed through the bit substitution logic stage z. Each of the eight (8) most significant logical X address bits 404a, 404c is processed through the respective logical bit substitution stages z. Using the ninth real X address bit 404a as an illustrative example, all sixteen (16) of the logical Z address bits 402 are available for selection and are input into a 16x1 406 z selection multiplexer. Four (4) bits placed in the register APG_XSCR_Z_BITS_L 316, specifically the bits APG_XCR_Z_BITS_L [0: 3] are assigned as relevant to the ninth bit of the real X address 404a. The four bits APG_XSCR_Z_BITS_L [0: 3] select one of the sixteen (16) available Z address 402 to be presented as a replacement bit 408 for the ninth bit of real X address 404a at the output of the selection multiplexer z 406. The ninth bit of real C address 404a and the substitution of the selected bit z 408 are input into a 2x1 bit z enable multiplexer 410. bit 2 of the register APG_XYZ_SCR_EN 312 enables or disables the scrambling function for the XScramble block 302 in dependence from blocks YScramble and ZScramble 304, 306. The blocks YScramble and ZScramble 304, 306 each have a unique bit, the bits respectively APG_XYZ_SCR_EN [1] and APG_XYZ_SCR_EN [0], to enable or disable the scramble function independent of the other scramble blocks . The register APG_XSCR_Z_EN 314 contains one bit for each of the eight (8) address lines x 404a, 404c which enables or disables the bit substitution function z for each line and can be set independently for each of the upper address lines 404a, 404c . In the described embodiment the bit APG_XSCR_Z_EN [8] is assigned to enable or disable the substitution of the bit z for the ninth real address line X 404a. A conjunction of the ninth bit originating in the APG_XSCR_Z_EN 314 register (i.e. the APG_XSCR_Z_EN [8] bit) and the APG_XYZ_SCR_EN [2] 312 bit selects either the ninth bit of real X address 404a or the substitution of bit z 408 to be presented as output 408 of bit enable multiplexer z 410. the conjunction operation disables the bit substitution function z if the scramble function is bypassed by block 302. consequently bit 2 of register APG_XYZ_SCR_EN 312 and the eighth bit of register APG_XSCR_Z_EN 314 must be set as true in order to operate the bit substitution function z. If any of the enable bits from registers 314 and 312 are set false, the logical x address bit 404a is presented to the output of the z-bit enable multiplexer has four (4) unique bits associated with it from the registers APG_XSCR_Z_BITS_L and APG_XSCR_Z_BITS_U 316 as a respective unique bit in the APG_XSCR_Z_EN_314 register. consequently the bit substitution function z can be programmed separately for each of the eight (8) most significant bits of the logical X address lines 404a, 404c. The collective output of the bit-substitution logic stage z is called selected address lines X z 412.

The XScramble, YScramble and ZScramble blocks 302, 304, 306 all contain the "jamming" logic stage. Consequently, the present description is relevant for all scramble blocks, only the XScramble block 302 being described in detail here. The jamming logic stage comprises a 2x1414 jamming multiplexer for each bit of the eight (8) least significant bits of the logical X address lines 404b and for each bit of the selected z most significant address lines 412. The jamming stage allows the overriding of the bit values presented as the logical Z address 404b or the selected X address z 412 with a fixed programmed value. The corresponding bit positions in the APG_XSCR__JAM_MASK 308 and APG_XSCR_JAM_ADDR 310 registers correspond to the respective bit position in the selected X address lines z 404, 412. The bits in the APG_XS CR_JAM_ADDR 310 register are presented as input in jamming multiplexer 414. The other input is one of the bits from the selected X address lines logical z 404b, 412. A bit in register APG_XSCR_JAM_MASK 308 that corresponds to the respective bit in the address line X selects either the selected address line X logical z 404b, 412 or the bit value programmed in the register APG_XSCR_JAM_MASK 310 shows how the output from jamming multiplexer 414. Each jamming stage has associated to it a unique bit in the registers APG_XSCR_JAM_ADDR and APG_XSCR_JAM_MASK 308, 310. Consequently the jamming function can be programmed separately for each of the sixteen address lines X 404. The collective output of the jamming logic stage is called lines of actual X address 416.

Actual X address lines 416 address a RAM; XScramble 418. XScramble 418 RAM is 64 kwords by 16 bit memory that provides a lookup table for the mapping function according to the convention. The actual X address lines 416 address one of the 64 kwords and the word being addressed is presented as 420 mapped X address lines. The XScramble 418 RAM is programmed with appropriate mapping values before running the test configuration and is programmed at the same time as APG registers 308-328.

The disabling stage achieved by appropriate programming of bits 0-2 of the APG_XYZ_SCR_EN 312 register. The test developer can programmatically disable the entire mapping function for each of the XScramble, YScramble and XScramble blocks 302, 304, 306. Each of the three (3) bits corresponding to the XScramble, YScramble and ZScramble 3902, 304, and 306 blocks respectively. The actual X address lines 416 feed two separate paths within the XScramble block 302. One path of the actual X address lines 416 addresses the XScramble RAM 418. The other path of the actual X address lines 416 bypasses the XScramble RAM 418 and is input into a scramble enabling stage 422.

The 422 scramble enable is a sixteen-channel 2x1 multiplexer that accepts the X address lines 420 mapped from the XScramble 418 RAM and the actual X address lines 416 from the jamming multiplexers 414. Bit 2 from the APG_XYZ_SCR_EN 312 register causes that the scramble enable 42 selects either the mapped X address lines 420 or the actual Z address lines 404 to be presented as output 326 of the XScramble block 302. Bit 1 of the APG_XYZ_SCR_EN register controls the YScramble enable and bit 0 of the register APG_XYZ_SCR_EN 312 controls the ZScramble enable in a similar way.

With specific reference to Figure 5 of the drawings, a block diagram of the ZScramble 306 block according to the teachings of the present invention is shown. As mentioned above, the ZScramble block 306 includes the bit substitution logic stage z but includes the jamming logic stage. The logical Z address lines 402 and the contents of the APG_ZSCR_JAM_ADDR 328 register are input to the sixteen (16) 2x1 jamming multiplexers 502. The APG_ZSCR_JAM_MASK register 326 selects between the two values for each bit to produce the actual Z address lines 304. The actual 504 z-address lines address a 506 ZScramble RAM to access the memory locations in 506 ZScramble RAM which become the 508 mapped Z-address lines. 508 mapped z-address lines are input into the 2x1 scramble enable a sixteen (16) channels 510. The actual z address lines 508 are also input into the 2x1 scramble enable at sixteen (16) channels 510. The bit associated with the ZScramble block 306 in the APG_XYZ_SCR_EN register 312, i.e. the APG_XYZ_SCR_EN [ 0] selects the actual Z address lines 504 or the mapped Z address lines 508 to be presented as real address information 330 at the output of the ZScra block mble 306.

The present description describes the features of the present invention which are described by way of example. One of ordinary skill in the art will appreciate that the present invention can be scaled without departing from the scope of the claims. The present description is intended to be illustrative and not limitative of the present invention, the scope of the invention being defined solely by the appended claims.

Claims (10)

CLAIMS 1. Apparatus for managing address channels in a memory testing device comprising: one or more address registers (24) storing a plurality of logic address bits (27), a plurality of replacement bits (408), each replacement bit corresponding to one of said logic address bits; a bit selector (410) for each combination of logical address bit and replacement bit, each bit selector independently selecting either said logical address bit or said replacement bit, a collective output of said bit selectors being a actual address (416), e a vector processor (40) for applying said actual address in said testing device. 2. Apparatus for managing the address channels in a memory testing device as set forth in claim 1 and further comprising a memory (418) which is turned on using said actual address (416). 3. Apparatus for managing address channels in a memory testing device as set forth in claim 1 and further comprising a substitution register (24) which stores a plurality of available bits (402) which are presented to a plurality of substitution bit selectors (406), each said substitution bit selector (406) corresponding to each in said respective plurality of said replacement bits (408), each said replacement bit selector (406) selecting one of said plurality of available bits (402) to generate each of said replacement bits (408). 4. Apparatus for managing the address channels in a memory testing device as set forth in claim 1 wherein one or more second address registers (24) store said plurality of available bits (402). 5. Apparatus for managing the address channels in a memory testing device as set forth in claim 1 or 4 wherein the contents of said one or more registers are generated by algorithms. 6. Apparatus for managing address channels in a memory tester as set forth in claim 3 wherein each said replacement bit selector (406) is addressed with a value to specify which of said available bits (420) is selected . Apparatus for managing address channels in a memory tester as set forth in claim 6 wherein each said value for specifying which of said available bits (420) is selected is stored in one or more selection control registers ( 316). 8. Apparatus for managing address channels in a memory tester as set forth in claim 7 wherein said one or more selection control registers (316) are programmable. 9. Apparatus for managing the address channels in a memory testing device as set forth in claim 7 wherein said selection control registers are programmable independently of each other. 10. Apparatus for managing the address channels in a memory testing device as set forth in claim 1 wherein said bit selector can be disabled.