KR20020019287A - Method for fabricating trench in semiconductor device - Google Patents
Method for fabricating trench in semiconductor device Download PDFInfo
- Publication number
- KR20020019287A KR20020019287A KR1020000052453A KR20000052453A KR20020019287A KR 20020019287 A KR20020019287 A KR 20020019287A KR 1020000052453 A KR1020000052453 A KR 1020000052453A KR 20000052453 A KR20000052453 A KR 20000052453A KR 20020019287 A KR20020019287 A KR 20020019287A
- Authority
- KR
- South Korea
- Prior art keywords
- trench
- forming
- oxide film
- epitaxial layer
- semiconductor device
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 29
- 239000004065 semiconductor Substances 0.000 title abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000002955 isolation Methods 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 3
- 239000000126 substance Substances 0.000 claims description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 2
- 238000004140 cleaning Methods 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 1
- 238000007517 polishing process Methods 0.000 claims 1
- 150000004767 nitrides Chemical class 0.000 abstract description 16
- 230000007547 defect Effects 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 230000003247 decreasing effect Effects 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 2
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76294—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using selective deposition of single crystal silicon, i.e. SEG techniques
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Element Separation (AREA)
Abstract
Description
본 발명은 반도체소자에 대한 것으로, 특히 트렌치를 형성한 후 그 코너를 라운딩 시키기에 알맞은 반도체소자의 트렌치 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method for forming a trench in a semiconductor device suitable for rounding corners after forming a trench.
첨부 도면을 참조하여 종래 반도체소자의 트렌치 형성방법에 대하여 설명하면 다음과 같다.Referring to the accompanying drawings, a trench forming method of a conventional semiconductor device will be described.
도 1a 내지 도 1d는 종래 반도체소자의 트렌치 형성방법을 나타낸 공정단면도이다.1A through 1D are cross-sectional views illustrating a method of forming a trench in a conventional semiconductor device.
종래 반도체소자의 트렌치 형성방법은 도 1a에 도시한 바와 같이 반도체기판(1)상에 초기산화막과 질화막을 증착한다.In the trench forming method of the conventional semiconductor device, an initial oxide film and a nitride film are deposited on the semiconductor substrate 1 as shown in FIG. 1A.
그리고 도면에는 도시되지 않았지만 질화막상에 감광막을 도포하고 소자 분리영역을 형성할 부분의 질화막이 노출되도록 노광 및 현상공정으로 선택적으로 감광막을 패터닝한다.Although not shown in the drawing, a photoresist is coated on the nitride film and the photoresist is selectively patterned by an exposure and development process so that the nitride film of the portion to form the device isolation region is exposed.
이후에 패터닝된 감광막을 마스크로 질화막과 초기산화막을 차례로 식각하여 패드산화막(2)과 패드질화막(3)을 차례로 적층 형성한다.Subsequently, the nitride film and the initial oxide film are etched sequentially using the patterned photoresist as a mask to sequentially form the pad oxide film 2 and the pad nitride film 3.
그리고 적층형성된 패드산화막(2)과 패드질화막(3)을 마스크로 반도체기판(1)을 이방성 식각해서 소자 분리영역을 형성할 트렌치(4)를 형성한다.The trench 4 for forming an isolation region is formed by anisotropically etching the semiconductor substrate 1 using the pad oxide film 2 and the pad nitride film 3 stacked thereon as a mask.
다음에 도 1b에 도시한 바와 같이 고온 열산화 공정에 의해 트렌치(4) 표면내에 산화막(5)을 형성한다.Next, as shown in FIG. 1B, the oxide film 5 is formed in the trench 4 surface by a high temperature thermal oxidation process.
이에 따라서 원래 'a'만큼의 폭을 갖는 활성영역이 'b'만큼의 폭을 갖게된다. 즉, 활성영역의 폭이 줄어들게 된다.As a result, the active region having a width of 'a' originally has a width of 'b'. That is, the width of the active area is reduced.
이후에 도 1c에 도시한 바와 같이 고밀도 플라즈마(High Density Plasma : HDP)산화막(6)을 트렌치(4)를 포함한 전면에 형성한다.Thereafter, as shown in FIG. 1C, a high density plasma (HDP) oxide film 6 is formed on the entire surface including the trench 4.
그리고 도 1d에 도시한 바와 같이 화학적 기계적 연마(CMP : Chemical mechanical Polishing)공정으로 고밀도 플라즈마 산화막(6)을 평탄화 시켜서 소자격리막(6a)을 형성한다.As shown in FIG. 1D, the high-density plasma oxide film 6 is planarized by a chemical mechanical polishing (CMP) process to form the device isolation film 6a.
상기와 같은 종래 반도체소자의 트렌치 형성방법은 다음과 같은 문제가 있다.The trench formation method of the conventional semiconductor device as described above has the following problems.
트렌치 형성후 고온 열산화공정을 진행하므로 트렌치 표면내에 산화막이 형성되어 활성영역의 폭이 줄어들게 된다.Since the high temperature thermal oxidation process is performed after the trench formation, an oxide film is formed in the trench surface, thereby reducing the width of the active region.
또한, 이와 같은 고온 열산화공정을 사용함에 따라서 기판의 부피 팽창에 따른 스트레스로 인해서 결정 결함이 발생할 수 있다.In addition, as the high temperature thermal oxidation process is used, crystal defects may occur due to the stress caused by the volume expansion of the substrate.
본 발명은 상기와 같은 문제를 해결하기 위하여 안출한 것으로 특히, 활성영역의 감소를 막고 기판에 결함없이 트렌치 코너를 라운딩시키기에 알맞은 반도체소자의 트렌치 형성방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a method for forming a trench in a semiconductor device suitable for preventing a decrease in active area and rounding a trench corner without defects on a substrate.
도 1a 내지 도 1d는 종래 반도체소자의 트렌치 형성방법을 나타낸 공정단면도1A through 1D are cross-sectional views illustrating a method of forming a trench in a conventional semiconductor device.
도 2a 내지 도 2d는 본 발명 반도체소자의 트렌치 형성방법을 나타낸 공정단면도2A through 2D are cross-sectional views illustrating a method of forming trenches in the semiconductor device of the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
31 : 반도체기판 32 : 패드산화막31 semiconductor substrate 32 pad oxide film
33 : 패드질화막 34 : 트렌치33: pad nitride film 34: trench
35 : 에피텍셜층 36 : 산화막35 epitaxial layer 36 oxide film
36a : 소자 격리막36a: device isolation layer
상기와 같은 목적을 달성하기 위한 본 발명 반도체소자의 트렌치 형성방법은 활성영역과 격리영역이 정의된 기판의 활성영역상에 제 1, 제 2 패드절연막을 적층 형성하는 공정, 상기 제 1, 제 2 패드절연막을 마스크로 상기 기판에 트렌치를 형성하는 공정, 상기 트렌치 표면상에 그 코너 부분이 라운딩(rounding)되도록 에피텍셜층을 성장시키는 공정, 상기 에피텍셜층상의 트렌치내에 소자 격리막을 형성함을 특징으로 한다.The trench forming method of the semiconductor device of the present invention for achieving the above object is a step of laminating the first and second pad insulating film on the active region of the substrate in which the active region and the isolation region are defined, the first and second Forming a trench in the substrate using a pad insulating film as a mask, growing an epitaxial layer such that a corner portion is rounded on the trench surface, and forming an isolation layer in the trench on the epitaxial layer It is done.
첨부 도면을 참조하여 본 발명 반도체소자의 트렌치 형성방법에 대하여 설명하면 다음과 같다.Referring to the accompanying drawings, the trench forming method of the semiconductor device of the present invention will be described.
도 2a 내지 도 2d는 본 발명 반도체소자의 트렌치 형성방법을 나타낸 공정단면도이다.2A through 2D are cross-sectional views illustrating a method of forming trenches in the semiconductor device of the present invention.
본 발명은 반도체소자에 트렌치를 형성할 때 특히, 그 코너 부분을 라운딩 시키기에 알맞은 방법에 대한 것으로 먼저, 도 2a에 도시한 바와 같이 반도체기판(31)상에 초기산화막과 질화막을 증착한다.The present invention relates to a method suitable for rounding a corner portion, particularly when forming a trench in a semiconductor device. First, an initial oxide film and a nitride film are deposited on a semiconductor substrate 31 as shown in FIG. 2A.
그리고 도면에는 도시되지 않았지만 질화막상에 감광막을 도포하고 소자 분리영역을 형성할 부분의 질화막이 노출되도록 노광 및 현상공정으로 선택적으로 감광막을 패터닝한다. 이후에 패터닝된 감광막을 마스크로 질화막과 초기산화막을 차례로 식각하여 패드산화막(32)과 패드질화막(33)을 차례로 적층 형성한다.Although not shown in the drawings, a photoresist is coated on the nitride film and the photoresist is selectively patterned by an exposure and development process so that the nitride film of the portion where the device isolation region is to be formed is exposed. Subsequently, the nitride film and the initial oxide film are etched sequentially using the patterned photoresist as a mask to sequentially form the pad oxide film 32 and the pad nitride film 33.
이후에 적층형성된 패드산화막(32)과 패드질화막(33)을 마스크로 반도체기판(31)을 이방성 식각해서 소자 분리영역을 형성할 트렌치(34)를 형성한다.Thereafter, the semiconductor substrate 31 is anisotropically etched using the pad oxide film 32 and the pad nitride film 33 stacked thereon to form a trench 34 for forming an isolation region.
그리고 다음 공정을 진행하기 전에 SCl(NH4OH)가스로 25~90℃정도의 온도에서 1~20분 정도 세정공정을 진행한다.And before proceeding to the next step of the cleaning process for 1 to 20 minutes at a temperature of 25 ~ 90 ℃ with SCl (NH 4 OH) gas.
다음에 도 2b에 도시한 바와 같이 패드산화막(32)과 패드질화막(33)을 마스크로 반도체기판(31)의 실리콘을 시드(seed)로 하여 선택적 에피텍셜 성장(Selective Epitaxial growth) 공정을 한다. 이와 같은 공정을 하여 트렌치(34)표면상에 50~700Å의 두께를 갖는 에피텍셜층(35)을 성장시킨다.Next, as shown in FIG. 2B, a selective epitaxial growth process is performed by using the pad oxide film 32 and the pad nitride film 33 as a mask to seed the silicon of the semiconductor substrate 31. In this manner, the epitaxial layer 35 having a thickness of 50 to 700 Å is grown on the surface of the trench 34.
이때 사용하는 가스는 0.3~0.7slpm의 HCl과 0.2~0.5slpm의 SiH2Cl2이고, 온도는 550~950℃ 정도에서 진행한다.At this time, the gas used is 0.3 ~ 0.7slpm HCl and 0.2 ~ 0.5slpm SiH 2 Cl 2 , the temperature proceeds at about 550 ~ 950 ℃.
일반적으로 열역학적 이론에 의하면 어떤 반응이 일어날 때 에너지는 감소하는 방향으로 간다. 이러한 원리에 의하면 에패텍셜층(35)을 성장시키는 반응에서 반도체기판(31)의 실리콘을 시드로 한 에피 셩장시에 트렌치 코너의 표면 장력이 감소되려면 에피텍셜층은 트렌치 코너에서 원형을 이루어야 한다.In general, thermodynamic theory states that when a reaction occurs, the energy goes in the direction of decreasing. According to this principle, the epitaxial layer should be circular at the trench corners in order to reduce the surface tension of the trench corners during epitaxial growth with the silicon of the semiconductor substrate 31 in the reaction of growing the epitaxial layer 35.
이에 따라서 트렌치 코너에 형성되는 에피텍셜층은 도 2b에서와 같이 라운드된다.Accordingly, the epitaxial layer formed at the trench corners is rounded as shown in FIG. 2B.
다음에 도 2c에 도시한 바와 같이 고밀도 플라즈마(High Density Plasma : HDP) 산화막이나 O3TEOS 산화막과 같은 산화막(36)을 트렌치(34)를 포함한 전면에 증착한다.Next, as shown in FIG. 2C, an oxide film 36 such as a high density plasma (HDP) oxide film or an O 3 TEOS oxide film is deposited on the entire surface including the trench 34.
그리고 도 2d에 도시한 바와 같이 화학적 기계적 연마(CMP : Chemical mechanical Polishing)공정으로 산화막(36)을 평탄화 시켜서 소자 격리막(36a)을 형성한다.As shown in FIG. 2D, the oxide isolation layer 36 is planarized by a chemical mechanical polishing (CMP) process to form the device isolation layer 36a.
상기와 같은 본 발명 반도체소자의 트렌치 형성방법은 다음과 같은 효과가 있다.The trench formation method of the semiconductor device of the present invention as described above has the following effects.
첫째, 에피텍셜 공정으로 트렌치 코너를 라운딩 시키므로 트렌치 코너 부분에서 발생될 수 있는 결함을 제거할 수 있다.First, since the trench corners are rounded by an epitaxial process, defects that may occur in the trench corners may be removed.
둘째, 트렌치 표면상에 에피텍셜층을 형성하므로 결과적으로 활성영역이 종래에 비해서 증가되는 효과가 있다.Second, since the epitaxial layer is formed on the trench surface, as a result, the active area is increased as compared with the prior art.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000052453A KR20020019287A (en) | 2000-09-05 | 2000-09-05 | Method for fabricating trench in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000052453A KR20020019287A (en) | 2000-09-05 | 2000-09-05 | Method for fabricating trench in semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20020019287A true KR20020019287A (en) | 2002-03-12 |
Family
ID=19687490
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020000052453A KR20020019287A (en) | 2000-09-05 | 2000-09-05 | Method for fabricating trench in semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20020019287A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100444607B1 (en) * | 2002-10-24 | 2004-08-16 | 주식회사 하이닉스반도체 | Method of forming an isolation layer in a semiconductor device |
| KR100474859B1 (en) * | 2002-11-05 | 2005-03-11 | 매그나칩 반도체 유한회사 | Method of forming an isolation layer in a semiconductor device |
| KR100571420B1 (en) * | 2004-12-23 | 2006-04-14 | 동부아남반도체 주식회사 | Semiconductor Device Having Shallow Trench Separation Membrane and Manufacturing Method Thereof |
| US7371656B2 (en) * | 2003-12-31 | 2008-05-13 | Dongbu Electronics Co., Ltd. | Method for forming STI of semiconductor device |
| KR101026474B1 (en) * | 2003-12-10 | 2011-04-01 | 매그나칩 반도체 유한회사 | Device Separating Method of Semiconductor Device |
| CN112885771A (en) * | 2019-11-29 | 2021-06-01 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor device and semiconductor device |
-
2000
- 2000-09-05 KR KR1020000052453A patent/KR20020019287A/en not_active Application Discontinuation
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100444607B1 (en) * | 2002-10-24 | 2004-08-16 | 주식회사 하이닉스반도체 | Method of forming an isolation layer in a semiconductor device |
| KR100474859B1 (en) * | 2002-11-05 | 2005-03-11 | 매그나칩 반도체 유한회사 | Method of forming an isolation layer in a semiconductor device |
| KR101026474B1 (en) * | 2003-12-10 | 2011-04-01 | 매그나칩 반도체 유한회사 | Device Separating Method of Semiconductor Device |
| US7371656B2 (en) * | 2003-12-31 | 2008-05-13 | Dongbu Electronics Co., Ltd. | Method for forming STI of semiconductor device |
| KR100571420B1 (en) * | 2004-12-23 | 2006-04-14 | 동부아남반도체 주식회사 | Semiconductor Device Having Shallow Trench Separation Membrane and Manufacturing Method Thereof |
| CN112885771A (en) * | 2019-11-29 | 2021-06-01 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor device and semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100536604B1 (en) | Method of gap-fill using a high density plasma deposision | |
| US7279396B2 (en) | Methods of forming trench isolation regions with nitride liner | |
| KR100406580B1 (en) | Method for forming contact plug of semiconductor device | |
| KR100555472B1 (en) | Trench device isolation using selective epitaxial growth | |
| KR20020019287A (en) | Method for fabricating trench in semiconductor device | |
| KR20050003011A (en) | Fabricating method for trench isolation in semiconductor device | |
| US7018905B1 (en) | Method of forming isolation film in semiconductor device | |
| KR100801739B1 (en) | Trench isolation film formation method for semiconductor devices | |
| KR20040036958A (en) | Forming method for field oxide of semiconductor device | |
| KR20020049807A (en) | Isolation method for a semiconductor device | |
| KR100295671B1 (en) | Method for isolating semiconductor device | |
| KR100492790B1 (en) | Device isolation insulating film formation method of semiconductor device | |
| KR100533966B1 (en) | Isolation by trench type and method for manufacturing the same | |
| KR20030012116A (en) | Method of shallow trench isolation of the semiconductor device | |
| JP2005057147A (en) | Method for manufacturing semiconductor device | |
| KR100357199B1 (en) | Method for manufacturing semiconductor device | |
| KR100455095B1 (en) | Method of forming an isolation film in semiconductor device | |
| KR100473728B1 (en) | Method of forming a isolation layer in a semiconductor device | |
| KR20050069074A (en) | Method for manufacturing semiconductor devices | |
| KR20020010816A (en) | Method of forming contact in semiconductor device | |
| KR20030000489A (en) | Manufacturing method for semiconductor device | |
| KR20000075235A (en) | Method for forming device isolation | |
| CN1801473A (en) | Formation method of stress-free shallow trench isolation structure | |
| KR20020049349A (en) | Method for growing an epi-silicon layer | |
| KR20100032039A (en) | Method for manufacturing shallow trench isolation of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 20000905 |
|
| PG1501 | Laying open of application | ||
| N231 | Notification of change of applicant | ||
| PN2301 | Change of applicant |
Patent event date: 20041006 Comment text: Notification of Change of Applicant Patent event code: PN23011R01D |
|
| PC1203 | Withdrawal of no request for examination | ||
| WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |