KR20020018037A - Method for processing grayscale display of the plasma display panel - Google Patents

Abstract

PURPOSE: A method for processing an assignment of an intensity level of a plasma display panel is provided to improve picture quality by reducing a degradation phenomenon of the picture quality without dividing or changing each sub-field. CONSTITUTION: An output processing portion(13) is formed with an adder portion(13A) and an operation portion(13B). The adder portion(13A) adds output data of the operation portion(13B) to digital image data of a flame memory and outputs the added result to a plasma display panel(100). The operation portion(13B) a dot counter(13C) for counting the number of dot. A line counter(13D) is used for counting the number of pixel. A field counter(13E) is used for counting the number of field. A plurality of exclusive OR circuit(13F,13G) is used for performing an exclusive OR operation. The dot counter(13C), the line counter(13D), and the line counter(13E) perform count operations according to the timing signal of a drive timing control portion.

Description

Plasma display panel gradation display processing method {METHOD FOR PROCESSING GRAYSCALE DISPLAY OF THE PLASMA DISPLAY PANEL}

The present invention relates to a gradation display processing method of a PDP.

In the PDP, one frame period is composed of a plurality of subfields SF1 to SF8 each having a relative ratio of lighting periods (dielectric zone period, proportional to light emission luminance). In accordance with A / D conversion, the input analog video signal is converted into a digital signal having the number of bits corresponding to the number of subfields, and the corresponding pixel is lit in an appropriate subfield based on the bit data to display a predetermined grayscale image. Doing.

Fig. 1 shows an arrangement of subfields used in the PDP, in which 256 gradation display is performed by eight gradation bits. The gradation bits in the following order correspond to SF1 at the highest gradation bit (the eighth bit). (7th bit) is SF2, gradation bit (6th bit) is SF3, gradation bit (5th bit) is SF4, gradation bit (4th bit) is SF5, and gradation bit (3rd bit) is SF6 corresponds to the gradation bit (second bit) and SF7, and the lowest gradation bit (the first bit) corresponds to SF8. In each of the subfields SF1 to SF8, the sustain discharge period is, for example, the number of gray scales (relative to the luminance ratio: the number of emission pulses (holding pulses)) 128, 64, 32, 16, 8, 4, 2, It is given by 1.

However, when the subfields are simply arranged in the order of luminance ratio and displayed, image quality deterioration called a fairy tale-like outline (for example, a phenomenon in which gradation is disturbed in a portion where gradation gradually changes like a human cheek). Occurs.

Conventionally, in order to prevent the image quality deterioration from occurring, a method of changing the arrangement of the respective subfields or changing the relative ratio of each subfield luminance is performed.

Such a method of reducing the moving picture-like contour is based on the control of the display driving circuit, that is, the division and rearrangement of the subfields. In order to further reduce the moving picture-like contour, there are limitations in the method by the division and rearrangement of the subfield. . For this reason, efforts have been made to further reduce assimilation-like contours by a new method.

An object of the present invention is to make it possible to further reduce the image quality deterioration called a moving picture-like outline by a new method, without resorting to division and rearrangement of subfields.

In order to solve the above object, the present invention provides a display device for performing gradation display of a PDP composed of a plurality of pixels, the least significant bit value of the first counter for sequentially selecting each pixel of one PDP line, and each of the PDPs. The first step of performing an exclusive AND operation with the least significant bit value of the second counter for sequentially selecting a line, and the least significant bit value based on the result of the first step are sequentially input, and the display data for each pixel is already input. And a second step of sequentially adding to each of the gradation data of the predetermined number of bits inputted therein, and a third step of outputting display data based on the processing result of the second step to the PDP.

Moreover, it has a 4th step which performs exclusive AND operation with the value of the operation result of a 1st step, the lowest value of the 3rd counter which selects each field of a PDP sequentially, and in a 2nd step, the operation of a 4th step A process of sequentially inputting the least significant bit value based on the result, and sequentially adding to each of the gradation data of a predetermined number of bits already input as display data for each pixel.

1 shows an arrangement of subfields used in a PDP apparatus.

2 is a block diagram showing the configuration of a PDP apparatus according to the present invention.

3 is a block diagram showing a main configuration of the PDP apparatus of FIG.

4 shows an example of the PDP display.

*** Explanation of symbols for the main parts of the drawing ***

11 AC / DC conversion unit 12 flame memory

13 output unit 14 synchronization separation unit

15: timing generator 16: memory controller

17: drive timing control unit 18: Government

13A: Adder 13B: Compute

13C: Dot counter 13D: Line counter

13E: Field Counter

13F, 13G: Exclusive-OR Circuit

100: plasma display panel (PDP)

101: plasma display panel (PDP) display area

AIN: Analog input video signal DIN: Digital input video signal

EMBODIMENT OF THE INVENTION Hereinafter, this invention is demonstrated with reference to drawings.

2 is a block diagram showing the configuration of a PDP apparatus according to the present invention.

As illustrated, the PDP apparatus includes an AC / DC conversion unit for converting the PDP 100 and the input analog video signal AIN into digital video data. 11), a flame memory 12 for storing digital image data, an output processor 13 for outputting the digital image data in the flame memory 12 to the PDP 100, and a synchronization signal from the analog image signal AIN. And a timing pulse on the basis of the synchronization signal, and converts the analog video signal (AIN) into an alternating current / direct current (AIN). A / D) timing generation unit 15 for converting, and based on the timing pulse, accumulation of data to the flame memory 12 and output of data to the output processor 13 from the flame memory 12. A memory control unit 16 that controls the control unit; and the output processing unit 13 based on the timing pulse. Drive timing controller for outputting the data of the flame memory 12 to the PDP 100 and outputting a driving pulse to the PDP 100 to display the gray level of the PDP 100. 17).

In addition, the PDP apparatus according to the present invention, in addition to the above-described parts, the gradation correction for the digital image data AC / DC (A / D) conversion by the AC / DC (A / D) conversion unit 11 Inverse corrector Inverse compensation operation is performed to accumulate in the flame memory 12. The reverse compensator 18 is provided.

FIG. 3 is a block diagram showing the main components of the PDP apparatus of FIG. 1, showing the configuration of the output processor 13. As shown in FIG. The output processor 13 includes an adder 13A and a calculator 13B. Here, the adder 13A adds output data a, which is a result of the calculation of the calculator 13B, to the digital image data of the flame memory 12, and outputs the output data to the PDP 100 as output data. . The calculating section 13B includes a dot counter 13C for counting the number of dots (pixels), a line counter 13D for counting the number of lines, and a field counter 13E for counting the number of fields. And Exclusive-OR circuits 13F and 13G, which are circuits for performing an exclusive-OR operation.

The dot counter 13C, the line counter 13D, and the field counter 13E constituting the arithmetic unit 13B count based on the timing signal output from the drive timing controller 17 in FIG. Will be done. The count value of the dot counter 13C corresponds to a pixel in the PDP 100 as described above, and the count value of the line counter 13D is assigned to a line in the PDP 100. At the same time, the count value of the field counter 13E corresponds to the field in the PDP 100.

Therefore, the output processing unit 13 selects a field according to the value of the line counter 13D in the selected field while simultaneously selecting a field of the PDP 100 according to the value of the field counter 13E. The digital image data in the flame memory 12 is outputted and displayed on the pixel represented by the value of the dot counter 13C in the selected line. In this case, the arithmetic unit 13B of the output processing unit 13 includes the least significant bit of the counter value of the dot counter 13C and the counter value of the line counter 13D in the exclusive logic circuit 13F. Compute the least significant bit of X with an exclusive AND. Subsequently, the exclusive logic circuit 13G calculates the exclusive logical product of the least significant bit according to the calculation result of the exclusive logic circuit 13F and the least significant bit according to the counter value of the field counter 13E. The least significant bit corresponding to the result of the calculation is output as the above-described output data a, while the adder 13A of the output processor 13 is configured to output the digital image data in the flame memory 12 as described above. The output data a is added, output to the corresponding pixel of the PDP 100, and displayed.

Now, in the state where the least significant bits of the line counter 13C and the field counter 13E of the calculating section 13B are all "0", the dot counter 13C is sequentially counted up and the least significant bit is 1 →. When 0 → 1 → 0 is changed, the output of the exclusive logic circuit 13F is also changed to 1 → 0 → 1 → 0, and the output of the exclusive logic circuit 13G is equally 1 → 0 → 1 → 0. To change.

Therefore, the data a output as the addition data to the adding unit 13A is output as data in which the least significant bit value has changed from 1 → 0 → 1 → 0 in accordance with the up count of the dot counter 13C.

From the state of the said calculating part 13B, when the said line counter 13D up counts one by one, and the least significant bit became "0" to "1", the sequential up count of the said dot counter 13C is performed. When the least significant bit changes from 1 → 0 → 1 → 0, the output of the exclusive logic circuit 13F changes from 0 → 1 → 0 → 1 differently than before, and the exclusive logic circuit 13G The output of) also changes from 0 → 1 → 0 → 1. Therefore, the data a output as addition data to the addition unit 13A is output as data in which the least significant bit is changed from 0 → 1 → 0 → 1 in accordance with the up count of the dot counter 13C.

In the state where the line counter 13C is up counted one by one, and the least significant bit is changed from "1" to "0", the least significant bit is 1 by the sequential up count of the dot counter 13C. When →→→→→ 0, the output of the exclusive logic circuit 13F is changed to 1 → 0 → 1 → 0 as before, and the output of the exclusive logic circuit 13G is equally 1 → 0 → Change from 1 → 0. Therefore, the data a output as the addition data to the adder 13A is also output as the data in which the least significant bit changes from 1 → 0 → 1 → 0 in accordance with the up count of the dot counter 13C.

In this manner, in the calculation unit 13B, for example, when an odd line is selected, the least significant bit alternately repeats "1" and "0" in response to an up count of the dot counter 13C. The data a is output, and when an even line is selected, the data a of a pattern in which the least significant bits alternately repeat "0" and "1" is output.

When the field counter 13E up counts one from the state of the operation unit 13B as described above, and the least significant bit changes from "0" to "1", the operation unit 13B returns to the previous (i.e., The inversion pattern as an output pattern of the field counter 13E before the up count is outputted. That is, when the odd number is selected in the state where the field counter 13E is up counted and the least significant bit is changed from "0" to "1", the up counter of the dot counter 13C is up. In response to this, the data of the pattern in which the least significant bits alternately repeat "0" and "1" is output, and when the even lines are selected, the data of the pattern in which the least significant bits alternately repeat "1" and "0". will print a.

Then, when the field counter 13E is further counted up and the least significant bit changes from "1" to "0", the dot counter 13C when the odd line is selected as before. In response to the up count of), the data a of the pattern in which the least significant bits alternately repeat "1" and "0" is output.If the even line is selected, the least significant bits alternately repeat "0" and "1". The data a of the pattern to be output is output.

When the digital input image signal DIN for the pixel A of the PDP 100 stored in the flame memory 12 is input to the adder 13A of the output processor 13, as described above, To the least significant bit of the input 8-bit data, output data a having the least significant bit value from the computing unit 13B is " 1 " is added to the PDP 100 and output for the next adjacent pixel B. When the digital input image signal DIN is input, the output data a having the lowest bit value from the calculator 13B is "0" is added to the least significant bit of the input 8-bit data, and the PDP 100 is added. Is output. The adder 13A outputs data a when the bit values of the 8-bit digital input image data DIN from the flame memory 12 are all data 255 (that is, "11111111"). Does not add.

4 shows an example of the PDP display, and according to the result, 8-bit data for each pixel of the odd line n + 1 in the field N + 1 of the PDP 100 is alternately set to the value " 1 " "," 0 "is added, and" 0 "and" 1 "are added to each pixel alternately for each pixel of the adjacent even line n + 2.

On the other hand, when the field N + 2 adjacent to the field N + 1 is selected, for each pixel of the odd line n + 1 of the field, "0" and "1" are alternately added for each pixel, and the even line n For each pixel of +2, "1" and "0" are alternately added to each pixel.

In this way, as the offset value "1" is assigned to each pixel in the display area of the PDP 100 in a checkerboard shape (chess board shape), a moving picture-like outline in the PDP 100 is generated and is smooth. Since the part where the gradation changes also spreads like a checkerboard shape, it can spread and reduce an assimilation-like outline. Therefore, the image quality deterioration called a moving picture-like outline can be further reduced regardless of the division and rearrangement of the subfields.

In the present embodiment, the exclusive logic circuit 13G is provided in the calculating section 13B of the output processing section 13, and the exclusive logic circuit 13G adds the value " 1 " for each field. By displacing the pixel to be added and the pixel to which the value "0" is added, the moving picture-like contour is more completely diffused and reduced.

However, the output of the exclusive logic circuit 13F which omits the exclusive logic circuit 13G and performs an exclusive AND operation on the value of the dot counter 13C and the value of the line counter 13D. Even when the configuration is made to add to 8-bit input data, the moving picture-like outline can be diffused and reduced.

As described above, the gradation display processing method of the PDP according to the present invention is a display device for performing gradation display of a PDP composed of a plurality of pixels, the first counter for sequentially selecting each pixel of one line of the PDP. An exclusive AND operation is performed on the least significant bit value and the least significant bit value of the second counter that sequentially selects each line of the PDP, and is applied to each of the gradation data of a predetermined number of bits already input as display data for each pixel. In this case, the least significant bit value based on the result of the exclusive AND operation is sequentially added, and the display data based on the addition result is output to the PDP, whereby an image quality called a moving picture-like outline that appears when the gray scale of the PDP is displayed. Deterioration can be reduced regardless of division and rearrangement of the subfields.

Furthermore, an exclusive AND operation is performed on the value of the result of the exclusive AND operation with the value of the least significant bit of the third counter that sequentially selects each field of the PDP, and the value of the operation result is already displayed for each pixel. Since the gradation data is sequentially added to each of the gradation data of a predetermined number of bits input as data, the moving picture-like outline can be further spread and reduced.

Claims (3)

A display apparatus for performing gradation display of a plasma display panel composed of a plurality of pixels, An exclusive AND operation is performed on the least significant bit value of the first counter that sequentially selects each pixel of one line of the plasma display panel and the least significant bit value of the second counter that sequentially selects each line of the plasma display panel. To perform the first step, A second step of sequentially inputting the least significant bit value of the data based on the operation result of the first step, and sequentially adding to each of the gradation data of a predetermined number of bits already input as display data for each pixel; And a third step of outputting display data based on the processing result of the second step to the plasma display panel. The method of claim 1, And a fourth step of performing an exclusive AND operation on the operation result value of the first step and the least significant bit value of the third counter that sequentially selects each field of the plasma display panel. Gradient display processing method of display panel. The method according to claim 1 or 2, The second step is a step of sequentially inputting the least significant bit value of the data based on the operation result of the fourth step, and sequentially adding each of the gradation data of a predetermined number of bits already input as data for each pixel. The gradation display processing method of the plasma display panel comprising a.