KR100421383B1 - Method for processing the gray scale display of plasma display panel - Google Patents

Abstract

The gradation display processing method of the plasma display panel according to the present invention increases the display gradation without increasing the subfields, thereby making it possible to reduce the assimilation-like outline and at the same time ensure a good display of the S / N ratio. In other words, the 8-bit data converted by the A / D conversion unit 12 is subjected to the backward correction operation by the backward correction unit 13 and output as 10-bit data. The bit data is divided into 8 bits of upper data and 2 bits of lower data. The average value of the lower two bits for the pixels C and D among the four pixels A, B, C, and D across the adjacent lines of the PDP is calculated, and the angles for the pixels A, B, C, and D are calculated based on the calculation result. The process of distributing display minimum levels to 8-bit data is performed in a pattern different from that of the odd field and the even field.

Description

Gradient display processing method of plasma display panel {METHOD FOR PROCESSING THE GRAY SCALE DISPLAY OF PLASMA DISPLAY PANEL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a method of processing gray scale display of a plasma display panel.

In a plasma display panel (hereinafter referred to as PDP), one frame period is composed of a plurality of subfields SF1 to SF8 each having a relative ratio of lighting periods (dielectric dielectric periods; proportional to light emission luminances). Then, the input analog video signal is A / D converted and converted into a digital signal having the number of bits corresponding to the number of subfields. Based on this bit data, the corresponding pixel is lit by an appropriate subfield to display a predetermined grayscale image. It is displaying.

In the PDP for performing gradation display, in order to maintain compatibility with the light emission characteristics of the CRT, correction called Υinverse correction, which is inverse correction of Υ correction (gradation correction), is performed.

1 is a block diagram showing a PDP apparatus according to the prior art. As shown, the PDP apparatus includes a PDP 100, a level adjuster 11 for adjusting the level of an analog video signal, and an A / D converter 12 for converting the level-adjusted video signal into digital video data. And an inverse correction unit 13 for performing an inverse correction operation, which is an inverse correction of gradation correction (correction correction), to the 8-bit digital image data A / D converted by the A / D conversion unit 12; A flame memory 14 for accumulating the digital image data, an output processor 15 for outputting the digital image data of the flame memory 14, and a synchronization separator 16 for separating synchronization signals from the analog image signal. ), A timing pulse generator 17 for generating timing pulses based on the synchronization signal, a memory controller 18 for controlling data accumulation and output of the flame memory 14 based on the timing pulses, Of the PDP 100 based on the timing pulse It consists of a driving timing generation unit 19 for generating the same pulse.

In the PDP apparatus according to the prior art, the analog video signal is level-adjusted by the level adjusting section 11, converted into 8-bit digital video data by the 8-bit A / D conversion section 12, and then 8-bit reverse correction. Back-correction is performed by (13), and is output to the PDP 100 via the flame memory 14 and the output processor 15.

2 is an arrangement diagram of subfields used in the PDP apparatus according to the prior art. As shown, the upper gradation bit (the eighth bit) corresponds to the subfield (hereinafter referred to as SF) 1, and in the following order, the gradation bit (the seventh bit) is referred to as SF2, and the gradation bit (the sixth bit) is referred to as SF3. The gradation bit (the fifth bit) corresponds to SF4, the gradation bit (the fourth bit) corresponds to SF5, the gradation bit (the third bit) corresponds to SF6, the gradation bit (the second bit) corresponds to SF7, and the lowest gradation. The bit (the first bit) corresponds to SF8.

Each of the SF1 to SF8 has a sustain discharge period, for example, the number of gray scales (relative ratio of the luminance of light emitted: proportional to the number of emission pulses (holding pulses)) 128, 64, 32, 16, 8, 4, 2, 1 As shown in FIG. 2, the display efficiency is best arranged in the order of emission luminance. Therefore, display of the PDP is performed based on the respective subfields SF1 to SF8 of the 256 gradations.

As described above, in the case of performing back inverse correction indicating the inverse correction of the gradation correction with respect to the digital image data, there is a problem that the display gradation of the low luminance part, especially of the display image displayed on the PDP 100, is remarkably lowered. Leads to.

In order to overcome such deterioration of image quality, increasing the display gradation from 256 to 1024 gradations increases the number of the subfields, thereby causing a problem of lowering the maximum luminance and increasing the number of emission pulses in the subfields. Fake outline; there is a problem of deterioration of image quality such as a phenomenon in which gray scales are disturbed in a slowly changing part such as a human ball.

In addition, when the number of gradations is increased by a known error diffusion process, since a value smaller than the minimum emission level (display minimum level) cannot be displayed, granular noise corresponding to the minimum emission level is generated on the display image. In particular, there is a problem that the S / N ratio of the gray scale display in the dark portion deteriorates.

Therefore, the gray scale display processing method of the plasma display panel according to the present invention increases display gray scales without increasing the subfields, thereby making it possible to reduce image quality deterioration, such as moving picture-like outlines, and at the same time, satisfactory gray scale display of the S / N ratio. The purpose is to secure.

In order to solve the above problems, the present invention provides a device having a PDP composed of a plurality of unit display regions (pixels), wherein the first and second units are provided on a first line and are adjacent to each other among a plurality of unit display regions. Third and fourth unit display regions (displayed on the display regions (pixels A and B) and second lines selected after the first line, respectively adjacent to the first and second unit display regions and adjacent to each other; When the first step of setting the pixels C and D as a pair of display areas and the analog video signal for the first to fourth unit display areas is input, m (m is a positive integer) bits are respectively converted into digital data. A third step of performing a predetermined correction process on the m-bit digital data converted based on the second step and the process of the second step and outputting n (n is a positive integer) bit larger than m; , N bits for the first to fourth unit display areas A fourth step of dividing the data into upper m-bit data and lower (n-m) bit data, and inputting at least the divided (n-m) bit data for the third and fourth unit display areas. The process of distributing a predetermined value based on the fifth step of the calculation and the fifth step operation result on the first to fourth unit display area m-bit data is performed for each odd and even field, and the odd field and And a seventh step of distributing the even fields in different distribution patterns, and a seventh step of outputting the m-bit data based on the processing result of the sixth step to the PDP to perform gradation display.

1 is a block diagram showing a configuration of a PDP apparatus according to the prior art.

2 is an arrangement diagram of subfields used in the PDP apparatus according to the prior art;

3 is a block diagram showing the configuration of a PDP apparatus according to the present invention;

Figure 4 is a block diagram showing the configuration of the gradation increasing unit according to the present invention.

5 is a view for explaining a pixel block to be displayed on a PDP according to the present invention;

Fig. 6 is an illustration of gradation increasing processing of the PDP apparatus according to the present invention.

7 is another embodiment of gradation increasing processing of the PDP apparatus according to the present invention;

* Description of the symbols for the main parts of the drawings *

11: level adjusting part 12: A / D conversion part

13: vice versa 14: flame memory

15: output processing section 16: synchronous separation section

17: timing pulse generator 18: memory controller

19: driving timing generating unit 20: gradation increasing unit

21 to 25: delay unit 26 to 29: addition unit

30, 31: line delay unit 32: average value calculation unit

33: selector 100: plasma display panel (PDP)

A, B, C, D, a, b, c, d: pixels

EMBODIMENT OF THE INVENTION Hereinafter, this invention is demonstrated with reference to drawings.

3 is a block diagram showing the configuration of a PDP (plasma display panel) device according to the present invention. As shown, the PDP apparatus according to the present invention includes a PDP 100, a level adjusting unit 11 for adjusting a level of an analog video signal, and an A / D conversion for converting a level adjusted video signal into digital video data. The section 12 and 8-bit digital video data A / D-converted by the A / D conversion section 12 perform a back inverse correction operation, which is an inverse correction of gradation correction (Υ correction), as 10-bit data. The gradation increasing unit 13 outputs the 8-bit data image data to the frame memory, which will be described later, for the 10-bit data that has been subjected to the backward-correction operation by the backward-correction unit 13 to output. 20, a flame memory 14 for storing digital image data, an output processor 15 for outputting the digital image data of the flame memory 14 to the PDP 100, and a synchronization signal from the analog image signal a. A synchronizing separator 16 for separating and other based on the synchronizing signal; A timing pulse generator 17 which generates a mining pulse, and controls the accumulation of data into the flame memory 14 and the output of data from the flame memory 14 to the output processor 15 based on the timing pulse. A memory control unit 18 and a drive timing generation unit 19 for generating a drive pulse of the PDP 100 based on the timing pulses.

4 is a block diagram showing a configuration of a gradation increasing unit according to the present invention. As shown in the figure, the gradation increasing unit 20 includes delay units 21 to 25, adders 26 to 29, line delay units 30 and 31, average value calculation unit 32, and selector ( 33).

5 is a view for explaining a pixel block to be displayed on a PDP according to the present invention.

3, 4 and 5, the gray scale display processing method of the PDP according to the present invention will be described below.

The 8-bit digital video data A / D-converted by the A / D converter 12 is subjected to back-correction calculation by the backward-correction unit 13 as described above and output as 10-bit data. . The gray scale increasing section 20 divides the 10-bit data into upper 8 bits and lower 2 bits of data as shown in FIG.

The gradation increasing section 20 calculates an average value of the lower two bits of a pixel block composed of four adjacent pixels, for example, pixels A, B, C, and D, shown in FIG. 5 over adjacent lines of the PDP 100. The display minimum level value is selectively added to the 8-bit data of each pixel A, B, C, D based on the calculation result.

In this case, when the 10-bit data for pixels A, B, C, and D are sequentially input to the gray scale increase unit 20, the upper 8-bit data for the pixel A is 1 in the delay units 21 and 22, respectively. After being delayed by the pixel, it is delayed by one line in the line delay unit 30, and is delayed by one pixel in the delay unit 23 to reach one input side of the adder 29. At this time, the upper 8-bit data for the pixel B is also delayed by one pixel in the delay units 21 and 22, respectively, and then delayed by one line in the line delay unit 30 to reach one input side of the adder 28. do. The upper 8-bit data for the pixel C is also delayed by one pixel in the delay units 21 and 22, respectively, and reaches one input side of the adder 27. The upper 8-bit data for the pixel D is also delayed by one pixel in the delay unit 21 and reaches one input side of the adder 26.

On the other hand, the lower two-bit data for the pixel A is delayed by one line in the line delay unit 31, and is delayed by one pixel in the delay unit 25 to reach the input side of the average value calculator 32. At this time, the lower two-bit data for the pixel B is delayed by one line in the line delay unit 31 and reaches the input side of the average value calculator 32. In addition, the lower two-bit data for the pixel C is delayed by one pixel in the delay unit 24 to reach the input side of the average value calculator 32, and the lower two-bit data for the pixel D is not delayed and the average value is calculated. The input side of the unit 32 is reached.

That is, each of the upper 8 bit data for the pixels A, B, C, and D is simultaneously input to one input side of the adders 26 to 29, and before the pixel A, The lower two-bit data for B, C, and D are simultaneously input to the average value calculating section 32. The average value calculation unit 32 calculates an average value of the lower two-bit data for the pixels A, B, C, and D.

The selector 33 synchronizes the value " 0 " or the display minimum level value " 1 " based on the calculation result of the average value calculator 32 with the pixel selection clock, and the other input side of the adders 26-29. Output to As a result, in the adders 26 to 29, the lower values for the pixels A, B, C, and D of the average value calculator 32 are applied to the upper 8 bit data for the pixels A, B, C, and D, respectively. The value " 0 " or the value " 1 " based on the calculation result of the average value of the two-bit data is added and output to the flame memory 14 as 8-bit data and accumulated.

In addition, the average value calculator 32 calculates an average of the lower two-bit data for the pixels C and D among the pixel blocks consisting of the pixels A, B, C, and D, and based on the calculation result, the pixels A, It is also possible to add the value "0" or the display minimum level value "1" to each of the upper 8 bit data for B, C, and D. In this case, the average value calculation unit 32 calculates an average value between the lower two-bit data for the pixel C passing through the delay unit 24 and the lower two-bit data for the pixel D not passing through the delay unit, The adders 26 to 29 respectively set the value " 0 " or the display minimum level value " 1 " based on the calculation result of the average value calculator 32 to each of the upper 8 bits for the pixels A, B, C, and D. Add to data and output.

The gradation increasing process by the gradation increasing unit 20 is performed for both the odd and even fields of the PDP 100 shown in FIG. Based on the average calculation result, the display minimum level value " 1 " is added to each of the upper 8 bit data for four pixels as shown in FIG.

Fig. 6 is an illustration of gradation increasing processing of the PDP apparatus according to the present invention.

Hereinafter, the first to third embodiments of the gradation increase processing in the gradation increase section will be described with reference to FIG. 6.

(First embodiment)

In the first embodiment, pixel blocks of the same line in the odd field and the even field (for example, pixels A and B of the line n + 1 of the odd field shown in Fig. 5 and pixels C of the following selection line n + 2, The gradation increasing process is performed for a pixel block made of D and a pixel block made up of pixels a, b of lines n + 1 of the even field and pixels c, d of lines n + 2.

In addition, for the odd field, an average calculation is performed on the lower two-bit data for pixels C and D among the pixel blocks consisting of pixels A, B, C, and D. In the even field, the average calculation is performed on the lower bit data for the pixels c and d among the pixel blocks including the pixels a, b, c and d.

In the case of the odd field, when the average calculation result of the lower two-bit data becomes "00", the upper eight-bit data of all the pixels A, B, C, and D are displayed as shown in FIG. The display minimum level value " 1 " When the average calculation result is " 01 ", the display minimum level value " 1 " is added to the upper 8 bit data of the pixels A, B, and C as shown in Fig. 6A. When the average calculation result is " 10 ", the display minimum level value " 1 " is added to the upper 8 bit data of the pixels A and D as shown in Fig. 6A, and at the same time, the average calculation is performed. When the result is " 11 ", the display minimum level value " 1 " is added only to the upper 8-bit data of the pixel B as shown in Fig. 6A.

On the other hand, in the case of the odd field, when the average calculation result for the lower two-bit data for the pixels c and d becomes "00", all the pixels a, b, c, d as shown in FIG. The display minimum level value "1" is added to each of the upper 8 bits of data. When the average calculation result is "01", the display minimum level value "1" is added to the upper 8 bit data of the pixels a, b, c, and d as shown in Fig. 6 (b-2). When the average calculation result is " 10 ", the display minimum level value " 1 " is added to the upper 8 bit data of the pixels b and c as shown in Fig. 6 (b-3), and the average calculation is performed. When the result is " 11 ", the display minimum level value " 1 " is added only to the upper 8-bit data of the pixel c as shown in Fig. 6B.

As a result of the tone increase processing of each pixel block of the odd field and the even field by the tone increase unit 20, the average calculation result for the lower two-bit data becomes " 00 " ), Gray scale display is performed so that the display minimum level value "1" is added to all the pixels A, B, C, and D. When the average calculation result is " 01 ", as shown in (c-2) in Fig. 6, for the pixels B and C, the display minimum level value " 1 " Is displayed as if half of the minimum display level value " 1 " was added. In addition, when the average calculation result is "10", as shown in (c-3) of FIG. 6, half of the display minimum level value "1" is added to all the pixels A, B, C, and D. When the average calculation result is " 11 ", gradation display is performed as if half of the display minimum level value " 1 " is added to the pixels B and C as shown in Fig. 6C.

This makes it possible to increase the display gradation with the gradation bit being 8 bits, and thus increase the display gradation without increasing the subfield. As a result, the degradation of the maximum luminance of the PDP 100 can be suppressed and the deterioration of image quality such as a moving picture-like outline can be reduced.

In the error diffusion process, granular noise is noticeable because the display minimum level values are irregularly arranged. In this embodiment, however, the display minimum level value is reduced by about 6 dB and the display minimum level value is in the shape of a houndstooth. Since it is distributed, the granular noise is inconspicuous, and thus the S / N ratio (S / N feeling) can be improved.

(2nd embodiment)

In the second embodiment, as shown in blackened portions in Fig. 5, for odd fields, for example, pixel blocks made up of pixels A, B on line n + 3 and pixels C, D on line n + 4, and even For the field, a gradation increasing process is performed for a pixel block composed of pixels c, d of lines n + 2 and pixels a, b of lines n + 3 which are shifted by one line from each pixel of the odd field. In addition, for the odd field, an average calculation is performed on the lower two-bit data for pixels C and D among the pixel blocks consisting of pixels A, B, C, and D. In the even field, average calculation is performed on the lower two-bit data for the pixels c and d among the pixel blocks composed of the pixels c, d, a, and b.

Here, the addition state of the display minimum level value "1" according to the average calculation result of the lower 2 bits of data for the upper 8 bits of data for the pixels A, B, C, and D of the odd field, and each pixel a of the even field The addition state of the display minimum level value " 1 " based on the average calculation result of the lower two bits of data for the upper 8 bits of data for b, c, and d is shown in Figs. 4) and the first embodiment shown in FIGS. 6 (b-1) to 6 (b-4).

Here, the addition state of the display minimum level value "1" according to the average calculation result of the lower 2 bits of data for the upper 8 bits of data for the pixels A, B, C, and D of the odd field, and each pixel a of the even field The addition state of the display minimum level value " 1 " based on the average calculation result of the lower two bits of data for the upper 8 bits of data for b, c, and d is shown in Figs. 4) and the first embodiment shown in FIGS. 6 (b-1) to 6 (b-4).

Therefore, when the average calculation result for the lower two-bit data becomes "00", the display minimum level values for all the pixels A, B, C, and D are the same as in the first embodiment as shown in FIG. The tone is displayed as if "1" is added. When the average calculation result is " 01 ", similarly to the first embodiment, the display minimum level value " 1 " is added to the pixels B and C as shown in Fig. 6C, and at the same time, The pixels A and D are grayscaled as if half of the display minimum level value " 1 " is added. Also, when the average calculation result is "10", as in the first embodiment, half of the display minimum level value "1" is added to all the pixels A, B, C, and D as shown in Fig. 6C. When the average calculation result is " 11 " and the average calculation result is " 11 ", the display minimum level value " 1 " The gradation is displayed as if half were added. This makes it possible to increase the display gradation while the gradation bit is 8 bits, and thus increase the display gradation without increasing the subfield. In addition, since a level smaller than the display minimum level value can be displayed, the deterioration of the S / N ratio due to the granular noise can be improved.

(Third embodiment)

In the third embodiment, the gradation increasing process is performed on the pixel blocks in which the odd field and the even field are the same line (the odd field and the even field may be shifted by one line as in the second embodiment). In the case of the odd field, the average calculation is performed for each of the lower two-bit data for the four pixels A, B, C, and D. The even field is also averaged for each of the lower two bits of data for six pixels a, b, c, and d.

Here, the addition state of the display minimum level value "1" according to the average calculation result of the lower two-bit data with respect to the upper 8-bit data for the pixels A, B, C, and D in the odd field, and each pixel a in the even field The addition status of the display minimum level value " 1 " according to the average calculation result of the lower two bit data with respect to the upper 8 bit data for, b, c, and d is the same as in the first and second embodiments.

Therefore, when the average calculation result for the lower two bits of data is " 00 ", as in the first and second embodiments, all the pixels A, B, C, and D are displayed as shown in Fig. 6C. The gray level display is performed as if the minimum level value "1" was added. When the average calculation result is " 01 ", similarly to the first and second embodiments, as shown in Fig. 6 (c-2), the display minimum level value " 1 " At the same time, half of the display minimum level value " 1 " is added to the pixels A and D in gray scale. When the average calculation result is " 01 ", similarly to the first and second embodiments, the display minimum level value " 1 " When the gray scale is displayed as if half is added and the average calculation result is " 11 ", similarly to the first and second embodiments, the display minimum level values for the pixels B and C as shown in FIG. It is displayed in gray scale as if half of "1" is added. This makes it possible to increase the display gradation with the gradation bit being 8 bits, and thus increase the display gradation without increasing the subfield. In addition, since a level smaller than the display minimum level value can be displayed, the deterioration of the S / N ratio due to the granular noise can be improved.

(4th Embodiment)

7 is another embodiment of the gradation increasing process of the PDP apparatus according to the present invention.

In the case where the pixel block is spread over the display area of the PDP 100 in which the gray scale display is gradually changed, the 10-bit data of the pixels A and C, for example, back-corrected by the backward compensator 13, is "0 0 0". In the case of 0 0 0 0 0 1 1, the 10-bit data of the pixels B and D becomes "0 0 0 0 0 0 0 1 0 0". In this case, in any case of each of the first to third embodiments, the representation value of each pixel based on the average value calculation result of the lower two-bit data, respectively,

Pixel A = Pixel C = 「0 0 0 0 0 0 0 0 0 1」

Pixel B = Pixel D = 「0 0 0 0 0 0 0 1 0 1」

The difference in data between the pixels A and C and the pixels B and D becomes large, so that these pixels are displayed in a certain line.

In the fourth embodiment, when the combination of the lower two-bit data in the 10-bit data is the combination of the value " 11 " and the value " 00 " as described above, and the average value is " 01 " As shown in (a-1), the display minimum level value " 1 " is added to the upper 8-bit data of the pixels B and D, and in the even field, the pixel B is shown in FIG. The display minimum level value " 1 " is added to each of the upper 8-bit data of, C, and D. As a result, the luminescence image of each pixel A, B, C, D becomes grayscale display as the display minimum level value "1" is added to pixel B, D as shown to (a-3) of FIG. For the pixel C, gray scale display is performed in which half of the display minimum level value "1" is added. As a result, the difference in data between the pixels A, C, and the pixels B, D becomes small, thus eliminating the above-mentioned line display.

In addition, when the combination of the lower two bits of the 10-bit data becomes "11" and "00", in the odd field, the upper 8 bits of each of the pixels A and D, as shown in FIG. The display minimum level value " 1 " is added to each other. In the case of an even field, the display minimum level value " 1 " is displayed for each of the upper 8 bit data of pixels A, B, and C as shown in FIG. ”Can be added. As a result, the luminescent image of each pixel A, B, C, D becomes gradation display as if display minimum level value "1" was added to pixel A, C as shown in (b-3) of FIG. For the pixel B, gray scale display is performed in which half of the display minimum level value "1" is added. As a result, the difference in data between the pixels A and C and the pixels B and D is reduced, and as a result, the line display between the pixels A, C pixels B and D can be eliminated.

Further, in the fourth embodiment, when the combination of the lower two bit data in the 10 bit data is the combination of the value "10" and the value "00", and the average value is "01", it is shown in FIG. As shown in c-1), the display minimum level value " 1 " is added to the upper 8-bit data of the pixels A, B, and D, and in the case of an even field, as shown in FIG. The display minimum level value "1" is added to each of the upper 8 bit data of B, C, and D. As a result, the luminescence image of each pixel A, B, C, D becomes gradation display as if display minimum level value "1" was added to pixels B and D as shown in FIG. For pixels A and C, gradation display appears as if half of the display minimum level value "1" is added. As a result, the difference in data between the pixels A, C and the pixels B, D can be reduced.

In addition, when the combination of the lower two bits of the 10-bit data becomes "10" and "00", in the odd field, each of the upper 8 of the pixels A, C, and D, as shown in FIG. The display minimum level value "1" is added to the bit data, and in the even field, the display minimum level value is displayed for each of the upper 8 bit data of the pixels A, B, and C as shown in (d-2) of FIG. It can be configured to add "1". As a result, the luminescence image of each pixel B, C, D becomes gradation display as if display minimum level value "1" was added to pixel A, C as shown in (d-3) of FIG. For D, gradation display appears as if half of the display minimum level value "1" is added. As a result, the data difference between the pixels A and C and the pixels B and D can be reduced.

As described above, according to the present invention, in the apparatus having a PDP composed of a plurality of unit display regions (pixels), the first and second unit display regions adjacent to each other are provided on the first line among the plurality of unit display regions. (Pixels A and B) and third and fourth unit display areas (pixel C) provided on the second line selected next to the first line, respectively adjacent to the first and second unit display areas and adjacent to each other. And D) are set as a pair of display areas, and when analog video signals for the first to fourth unit display areas are input, m (m is a positive integer) bits are converted into digital data, respectively, and the converted m bits A predetermined correction process is performed on the digital data of " n " and output as n-bit data larger than m (n is a positive integer). The n-bit data for the first to fourth unit display areas is respectively higher than the m-bit data. (N-m) bit data with and Inputting the divided (n-m) bit data for at least the third and fourth unit display areas, and calculating an average value of the divided and based on the calculation result for the m bit data for the first to fourth unit display areas. Since the allocation of the predetermined value is processed so that the odd field and the even field are different, the output is output to the PDP as m-bit data. Therefore, the display gradation can be increased without increasing the subfield, thereby suppressing the decrease in the maximum luminance of the PDP. In addition, deterioration of image quality of moving picture-like contours and the like, and satisfactory gradation display of S / N ratio can be ensured.

Claims (4)

A display apparatus having a plasma display panel composed of a plurality of unit display regions, and performing gradation display of the plasma display panel, The first and second unit display areas of the plurality of unit display areas are provided on the first line and are adjacent to each other, and are arranged on a second line selected next to the first line, respectively. A first step of setting the third and fourth unit display areas adjacent to and adjacent to each other as a pair of display areas; A second step of converting the analog video signal for the first to fourth unit display areas into digital data of m (m is a positive integer) bit, respectively; A third step of performing a predetermined correction process on the m-bit digital data converted on the basis of the process of the second step and outputting n (n is a positive integer) bit larger than m; A fourth step of dividing the n-bit data for the first to fourth unit display regions into upper m-bit data and lower (n-m) bit data, respectively; A fifth step of calculating an average value by inputting the divided (n-m) bit data for at least the third and fourth unit display areas; The process of distributing a predetermined value based on the fifth step operation result on the m-bit data for the first to fourth unit display areas for each odd and even field, and at the same time in different allocation patterns from the odd and even fields. The sixth step of distribution, And a seventh step of outputting m-bit data based on the sixth step result to the plasma display panel to perform gradation display. The method of claim 1, In the processing in the sixth step, when the calculation result of the fifth step is the first value, the value "1" is distributed to m-bit data for the first to fourth unit display areas, and the calculation result is the second. In the odd field, the value "1" is allocated to the m-bit data for the first to third unit display areas in the odd field, and the value "1" is assigned to the m-bit data for the second to fourth unit display areas in the even field. If the calculation result is a third value, the odd field allocates the value " 1 " to the m-bit data for the first and fourth unit display areas, and for the second and third unit display areas in the even field. The value "1" is allocated to m-bit data, and when the calculation result is a fourth value, the value "1" is allocated to m-bit data for the second unit display area in the odd field, and the third field in the even field. The value "1" is added to the m-bit data for the unit display area. Gray scale display method of a plasma display panel minute characterized in that it comprises a process for. The method of claim 1, And the sixth step is performed by shifting the pair of display areas by one line in odd and even fields. The method of claim 1, And the processing in the fifth step includes processing of inputting (n-m) bit data for the first to fourth unit display areas to calculate an average value.