JP2002149106A - Gradation display processing method for plasma display panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the display gradation without increasing subfields to realize the reduction of the moving picture false contour and to assure good display of the SN ratio. SOLUTION: A γ reverse correcting part 19 applies a γreverse correction calculation to the 8-bit data converted by an A/D conversion part 12 and the resultant data are outputted as 10-bit data. A gradation increase part 20 divides each of this 10-bit data into 8 bits of the higher order and 2 bits of the lower order. Then the average of the 2 bits of the lower order of pixels C and D is calculated among the four pixels A, B, C, and D over the contiguity line of a PDP. Processing for allocating the display minimum level to each of the 8 bit data for the pixels A, B, C and D is performed on the basis of the calculation result by using a pattern which is different in the cases of the odd number field and the even number field.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gradation display processing method for a plasma display panel.

[0002]

2. Description of the Related Art Plasma display panels (hereinafter referred to as P
In DP), one frame period is composed of a plurality of subfields SF1 to SF8, each having a different relative ratio of a lighting period (sustain discharge period; proportional to light emission luminance). Then, the input analog video signal is converted into a digital signal having the number of bits corresponding to the number of subfields by A / D conversion, and a corresponding pixel is turned on by an appropriate subfield based on the bit data to thereby perform a predetermined operation. A gradation image is displayed. The example of FIG. 7 is an example in which 256 grayscale display is performed by eight grayscale bits. The highest grayscale bit (eighth bit) corresponds to SF1 and the grayscale bits (7 bit Eye) to SF2, gradation bit (sixth bit) to SF3, gradation bit (fifth bit)
Corresponds to SF4, the gradation bit (the fourth bit) corresponds to SF5, the gradation bit (the third bit) corresponds to SF6, and the gradation bit (the second bit) corresponds to SF7. The first bit) corresponds to SF8.

In each of the subfields SF1 to SF8, the sustain discharge period has a gray scale number (relative ratio of light emission luminance:
128, 64, 3 (proportional to the number of light emission pulses (sustain pulses))
2, 16, 8, 4, 2, 1 are arranged, and it is considered that the display efficiency is the best when arranged in the order of the emission luminance as shown in FIG. 7, and each of the 256-gradation subfields SF1 to SF8 Is displayed based on the PDP.

[0004]

A PDP for performing gradation display
In order to maintain compatibility with the light emission characteristics of a CRT, a correction called γ reverse correction, which is a reverse correction of γ correction (tone correction), is performed. That is, as shown in FIG. 6, after the analog input video signal a is level-adjusted by the level adjustment unit 11 and further converted into 8-bit digital video data by the 8-bit A / D conversion unit 12, the 8-bit γ is converted. The γ is inversely corrected by the inverse correction unit 19 and output to the PDP 100 via the frame memory 13 and the output processing unit 14.

As described above, when the γ inverse correction indicating the inverse correction of the gradation correction is performed on the digital video data, the PDP
A problem occurs in that the display gradation of a low-luminance portion of the display image displayed on the display 100 is significantly reduced, which leads to deterioration of image quality. If the display gradation is increased from 256 gradations to 1024 gradations in order to avoid such image quality deterioration, the number of subfields increases, so that the problem that the maximum luminance decreases and the light emission in the subfields occurs. Due to the increase in the number of pulses, a pseudo contour of a moving image (a false contour of a moving image;
For example, image quality degradation called a phenomenon in which gradation is disturbed in a smoothly changing portion such as a human cheek) occurs. Furthermore, if the number of gradations is to be increased by a known error diffusion process, it is impossible to display a value smaller than the minimum light emission level (display minimum level). There is a problem that noise is generated and the S / N ratio of gradation display is deteriorated particularly in a dark part.

Accordingly, the present invention increases the display gradation without increasing the number of sub-fields, enables reduction of image quality deterioration such as a false contour of a moving image, and secures a gradation display with a good S / N ratio. The purpose is to do.

[0007]

According to the present invention, there is provided an apparatus having a PDP including a plurality of unit display areas (pixels). And the first and second unit display areas (pixels A and B) adjacent to each other and provided on the second line, and the first and second unit display areas provided on the second line selected next to the first line. Third and fourth unit display areas (pixels C and D) adjacent to and adjacent to the unit display area
A first step of setting as a pair of display areas;
When an analog video signal for the first to fourth unit display areas is input, each of the analog video signals is converted into digital data of m (m is a positive integer) bits, and is converted based on the processing of the second step. A third step of performing a predetermined correction process on the m-bit digital data and outputting it as n-bit (n is a positive integer) bit data larger than m, and a first or fourth unit display area. Of the upper m-bit data and the lower (n-m)
A fourth step of dividing the data into bit data, and (n-
m) a fifth step of inputting bit data and calculating an average value, and an odd number distribution process of a predetermined value based on a calculation result of the fifth step for m bit data for the first to fourth unit display areas. And a sixth step in which the distribution is performed for each of the even-numbered fields and different distribution patterns are used for the odd-numbered fields and the even-numbered fields. And a seventh step of performing

In the processing in the sixth step, when the operation result in the fifth step is the first value (“00”), the value “1” is added to the m-bit data for the first to fourth unit display areas. Is distributed, and the calculation result is the second value (“01”)
, The value “1” is allocated to the m-bit data for the first to third unit display areas in the odd field, and m for the second to fourth unit display area in the even field.
The value "1" is allocated to bit data, and when the operation result is the third value ("10"), the value "1" is allocated to m-bit data for the first and fourth unit display areas in an odd field. In the even field, the value “1” is allocated to the m-bit data for the second and third unit display areas, and when the operation result is the fourth value (“11”), the second unit display is performed in the odd field. The value “1” is allocated to the m-bit data for the area, and m is used for the third unit display area in the even field.
The value "1" is allocated to the bit data. Also,
The processing of the sixth step is to execute a pair of display areas by one line in odd and even fields. The process in the fifth step includes a process of inputting (nm) bit data for the first to fourth unit display areas and calculating an average value.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a PDP (plasma display panel) device to which the present invention is applied. In FIG. 1, the present PDP device is a PDP 100
And an A / D converter 1 for converting the level-adjusted video signal into digital video data, and a level adjuster 11 for adjusting the level of the input analog video signal a.
2 and a frame memory 1 for storing digital video data
3 and the digital video data in the frame memory 13
An output processing unit 14 for outputting to P100, a synchronization separation unit 15 for separating a synchronization signal from the analog video signal a, a timing pulse generation unit 16 for generating a timing pulse based on the synchronization signal, and a frame memory based on the timing pulse A memory control unit 17 for controlling the accumulation of data in the memory 13 and the output of data from the frame memory 13 to the output processing unit 14;
It has a drive timing generator 18 for generating a drive pulse of P100.

The PDP apparatus also performs γ inverse correction, which is the inverse correction of gradation correction (γ correction), on the 8-bit digital video data A / D converted by the A / D converter 12. A γ inverse correction unit 19 that performs a correction operation and outputs it as 10-bit data, and a predetermined arithmetic process is performed by each unit illustrated in FIG. Gradation increasing unit 2 for outputting 8-bit data to the frame memory 13 as video data
0.

FIG. 2 is a block diagram showing the configuration of the gradation increasing section 20. The gradation increasing unit 20 includes delay units 21 to 25,
It comprises adders 26 to 29, line delays 30 and 31, an average calculator 32, and a selector 33. by the way,
The 8-bit digital video data A / D-converted by the A / D conversion unit 12 is subjected to the γ-inverse correction operation by the γ-inverse correction unit 19 as described above, and is output as 10-bit data. The gradation increasing section 20 divides the 10-bit data into upper 8 bits and lower 2 bits as shown in FIG.

The tone increasing section 20 calculates an average value of lower two bits of a pixel block composed of four adjacent pixels, for example, pixels A, B, C, and D shown in FIG. Based on the calculation result, each pixel A,
A display minimum level value is selectively added to the 8-bit data of B, C, and D.

Here, the pixels A, B,
Assuming that each 10-bit data for C and D is input in order, the upper 8-bit data for pixel A is
After being delayed by one pixel at 22 respectively, the line delay unit 3
The signal is delayed by one line at 0 and further delayed by one pixel at the delay unit 23 and reaches one input side of the adder unit 29. At this time, the upper 8-bit data for pixel B is also transmitted to delay units 21 and 22.
, And is delayed by one line in the line delay unit 30 and reaches one input side of the adder unit 28. Further, the upper 8-bit data for pixel C is
The signals are delayed by one pixel at 1 and 22, respectively, and reach one input side of the adder 27. Furthermore, the upper 8-bit data for the pixel D is also delayed by one pixel in the delay unit 21 and reaches one input side of the addition unit 26.

On the other hand, the lower 2-bit data for the pixel A is delayed by one line in the line delay section 31, and
5, the signal is delayed by one pixel and reaches the input side of the average value calculation unit 32. At this time, the lower 2 bits of data for pixel B are delayed by one line in the line delay unit 31 and the average value calculation unit 32
Reaches the input side. The lower 2 bit data for the pixel C is delayed by one pixel in the delay unit 24 and reaches the input side of the average value calculator 32, and the lower 2 bit data for the pixel D is not delayed and is not delayed. Reaches the input side.

That is, the upper 8-bit data for the pixels A, B, C, and D are simultaneously input to one input side of the adders 29, 28, 27, and 26, respectively. Before pixel delay, pixels A, B, C, D
Are input to the average value calculation unit 32 at the same time. In the average value calculation unit 32, the pixels A, B, C,
Calculate the average value of the lower 2-bit data for D. The selector 33 supplies a value “0” or a display minimum level value “1” based on the calculation result of the average value calculation unit 32 to the other input side of the addition units 29, 28, 27, and 26 in synchronization with the pixel selection clock. Output. Thereby, the adders 29, 28, 2
7 and 26, the pixels A, B and C of the average value calculation unit 32 are compared with the upper 8 bits of data for the pixels A, B, C and D, respectively.
A value “0” or a value “1” based on the calculation result of the average value of the lower 2 bits of data for B, C, and D is added, and output to the frame memory 13 as 8-bit data and accumulated.

In the mean value calculating section 32, the pixels A,
In the pixel block consisting of B, C, and D, an average calculation is performed on the lower 2 bits of data for pixels C and D, and the upper 8 bits of data for pixels A, B, C, and D are calculated based on the calculation result. On the other hand, it is also possible to add the value “0” or the minimum display level value “1”. In this case, in the average value calculation unit 32, the lower 2
In addition to calculating the average value of the bit data and the lower 2 bit data for the pixel D that does not pass through the delay unit,
9, 28, 27, and 26 respectively assign a value “0” or a display minimum level value “1” based on the calculation result of the average value calculation unit 32 to the upper 8 bits of data for pixels A, B, C, and D. Add and output.

The gradation increasing process by the gradation increasing unit 20 is performed on both the odd field and the even field of the PDP 100 shown in FIG. Then, based on the average calculation result, the display minimum level value “1” is added to each of the upper 8-bit data for the four pixels as shown in FIG. Hereinafter, referring to FIG.
First to third embodiments of the gradation increasing process at 0 will be described.

(First Embodiment) In the first embodiment, the odd-numbered field and the even-numbered field have the same line of pixel blocks (for example, the pixels A and B on the line n + 1 of the odd-numbered field shown in FIG. , A pixel block composed of the pixels C and D of the selection line n + 2, and the pixels a and b of the line n + 1 and the pixels c and d of the line n + 2 in the even field.
Is performed for the pixel block composed of.
For odd fields, pixels A, B, C, D
The average calculation is performed on the lower two-bit data for the pixels C and D in the pixel block composed of. Further, with respect to the even-numbered fields, the average calculation is performed on the lower two-bit data for the pixels c and d in the pixel block including the pixels a, b, c, and d.

Here, in the case of an odd field, the lower 2
When the average calculation result of the bit data is “00”,
As shown in FIG. 4 (a-1), the display minimum level value "1" is added to the upper 8 bits of data of all the pixels A, B, C and D. When the average calculation result is “01”, FIG.
As shown in (a-2), the display minimum level value “1” is added to the upper 8 bits of each of the pixels A, B, and C. Further, when the average calculation result is "10", FIG.
As shown in FIG. 4 (a-4), the display minimum level value “1” is added to the upper 8 bits of each of the pixels A and D, and when the average calculation result is “11”, the pixel B as shown in FIG. The display minimum level value “1” is added only to the upper 8 bits of data.

On the other hand, in the case of the even field, the pixels c,
When the average calculation result for the lower 2 bit data for d is "00", the upper 8 bit data of all the pixels a, b, c and d are displayed as shown in FIG. The minimum level value “1” is added. When the average calculation result is "01", as shown in FIG.
A display minimum level value “1” is added to each of the upper 8 bits of d. Further, when the average calculation result is "10", as shown in FIG.
When the display minimum level value “1” is added to the bit data, and the average calculation result is “11”, FIG.
As shown in (b-4), the display minimum level value “1” is added only to the upper 8-bit data of the pixel c.

As a result of the gradation increasing process of each pixel block of the odd field and the even field by the gradation increasing unit 20, when the average calculation result for the lower 2 bit data is “00”, FIG. As shown in c-1), gradation display is performed such that the display minimum level value “1” is added to all the pixels A, B, C, and D. When the average calculation result is “01”, as shown in FIG.
For C, the gradation is displayed as if the display minimum level value “1” was added, and for the pixels A and D, the gradation was displayed as if half the display minimum level value “1” was added. Is displayed. Further, when the average calculation result is "10", gradation display is performed such that half of the display minimum level value "1" is added to all pixels A, B, C, and D as shown in FIG. At the same time, when the average calculation result is "11", gradation display is performed such that half of the display minimum level value "1" is added to the pixels B and C as shown in FIG. You.

As a result, it is possible to increase the display gradation while keeping the gradation bit at 8 bits, and thus it is possible to increase the display gradation without increasing the number of subfields. As a result, a decrease in the maximum luminance of the PDP 100 can be suppressed, and image quality deterioration such as a false contour of a moving image can be reduced. In the error diffusion process, granular noise is conspicuous because the display minimum level value is irregularly arranged. In this embodiment, the display minimum level value is reduced by about 6 dB and the display minimum level value is staggered. Since the particles are distributed in a grid pattern, the granular noise is inconspicuous, so that the S / N ratio (S / N feeling) can be improved.

(Second Embodiment) In the second embodiment, as shown by hatching in FIG. 3, for odd fields, for example, pixels A and B on line n + 3 and pixels C and C on line n + 4 D, and pixels c, d and line n + of line n + 2 which are connected to each pixel of the odd field by one line for the even field.
A gradation increasing process is performed on a pixel block including three pixels a and b. In the odd-numbered field, among the pixel blocks including the pixels A, B, C, and D, the pixels C,
An average calculation is performed on the lower two-bit data for D.
Further, for even fields, pixels c, d, a,
b, the lower two pixels for pixels c and d
Average calculation is performed on bit data.

Here, each pixel A, B,
The addition state of the display minimum level value “1” based on the average calculation result of the lower 2 bit data to the upper 8 bit data for C and D, and the upper 8 bit data for each pixel a, b, c, d of the even field 4 (a-1) to 4 (a-4) and FIGS. 4 (b-1) to 4 (4) show the addition states of the display minimum level value "1" based on the average calculation result of the lower 2 bits data. This is the same as the first embodiment shown in b-4).

Therefore, when the average calculation result for the lower two-bit data is "00", as in the first embodiment, as shown in FIG.
The gradation is displayed as if the display minimum level value “1” was added to D. Also, when the average calculation result is "01", the display minimum level value "1" is added to the pixels B and C as shown in FIG. 4C-2, as in the first embodiment. In addition to the gray scale display, the gray scale display is performed so that half of the display minimum level value “1” is added to the pixels A and D. Further, when the average calculation result is "10", the display minimum level value "1" is set for all the pixels A, B, C, and D as shown in FIG. 4C-3, as in the first embodiment. As in the first embodiment, when the gradation calculation is performed so that the halves have been added and the average calculation result is "11", the pixels B and C are set as shown in FIG. Thus, gradation display is performed as if half of the display minimum level value “1” was added.
As a result, it is possible to increase the display gradation while keeping the gradation bit at 8 bits, and thus it is possible to increase the display gradation without increasing the number of subfields. In addition, since a level smaller than the display minimum level value can be displayed, deterioration of the S / N ratio due to granular noise can be improved.

(Third Embodiment) In a third embodiment, a gradation increasing process is performed on a pixel block on the same line in an odd field and an even field (as in the second embodiment). And 1 in even field
Lines may be used). In the case of an odd-numbered field, an average calculation is performed on the lower two-bit data for each of the four pixels A, B, C, and D. Further, the average calculation is performed on the lower 2-bit data for the four pixels a, b, c, and d for the even-numbered fields.

Here, each pixel A, B,
The addition state of the display minimum level value “1” based on the average calculation result of the lower 2 bit data to the upper 8 bit data for C and D, and the upper 8 bit data for each pixel a, b, c, d of the even field On the other hand, the addition state of the display minimum level value “1” based on the average calculation result of the lower 2 bits data is the first
This is the same as in the second embodiment.

Therefore, when the average calculation result for the lower two-bit data is "00", as in the first and second embodiments, as shown in FIG.
The gradation is displayed as if the minimum display level value “1” was added to B, C, and D. The average calculation result is "01"
4 (c-), as in the first and second embodiments.
As shown in 2), gradation is displayed as if the display minimum level value “1” was added to the pixels B and C, and half of the display minimum level value “1” was displayed for the pixels A and D. Are displayed in a gray scale as if they were added. Further, when the average calculation result is “10”, similarly to the first and second embodiments,
As shown in FIG. 4C-3, gradation display is performed such that half of the minimum display level value “1” is added to all pixels A, B, C, and D, and the average calculation result is “11”. Similarly to the first and second embodiments, the gradation is such that half of the display minimum level value “1” is added to the pixels B and C as shown in FIG. Is displayed. As a result, it is possible to increase the display gradation while keeping the gradation bit at 8 bits, and thus it is possible to increase the display gradation without increasing the number of subfields. In addition, since a level smaller than the display minimum level value can be displayed, deterioration of the S / N ratio due to granular noise can be improved.

(Fourth Embodiment) FIG.
FIG. 14 is a diagram illustrating a fourth embodiment of the gradation increasing process at 0. When a pixel block spans the display area of the PDP 100 where the gradation display changes gradually, the γ inverse correction unit 1
For example, if the 10-bit data of the pixels A and C is “00000000011”, the 10-bit data of the pixels B and D is “00000001”
00 ”. In such a case, in any of the first to third embodiments, the expression value of each pixel based on the result of calculating the average value of the lower two-bit data is pixel A = pixel C = “00000000001” pixel B = pixel D = “00000000101”, the data difference between the pixels A and C and the pixels B and D becomes large, and therefore these pixels are displayed as a clear line.

In the fourth embodiment, when the combination of the lower 2-bit data of the 10-bit data is a combination of the value "11" and the value "00" as described above and the average value is "01" In the case of an odd field, FIG.
-1), the display minimum level value "1" is added to the upper 8 bits of each of the pixels B and D, and in the case of an even field, the pixels B and C are added as shown in FIG. , D are added to the display minimum level value “1”. As a result, each pixel A, B, C,
As shown in FIG. 5 (a-3), the light emission image of D has pixels B,
For D, the gradation display is such that the display minimum level value “1” is added, and for the pixel C, the gradation display is such that half of the display minimum level value “1” is added. As a result, the difference in data between the pixels A and C and the pixels B and D is reduced, and the above-described line display can be eliminated.

When the combination of the lower two bits of the 10-bit data is "11" and "00", the pixels A and D are in the odd field as shown in FIG. 5 (b-1). Is added to the upper 8-bit data of each pixel, and in the case of an even field, the upper 8-bit data of pixels A, B, and C are displayed as shown in FIG. The minimum level value “1” may be added. As a result, the light emission image of each of the pixels A, B, C, and D has a gradation such that the display minimum level value “1” is added to the pixels A and C as shown in FIG. Display is performed, and the pixel B has a gradation display in which half of the display minimum level value “1” is added. As a result, the difference in data between the pixels A and C and the pixels B and D is reduced, and as a result, the pixels A and C and the pixels B and
The line display between D can be similarly eliminated.

Further, in the fourth embodiment, when the combination of the lower two bits of the 10-bit data is a combination of the value "10" and the value "00" and the average value is "01", the odd number In the case of a field, FIG.
As shown in -1), the display minimum level value “1” is added to the upper 8 bits of each of the pixels A, B, and D, and
In the case of an even field, as shown in FIG. 5C-2, a display minimum level value "1" is added to the upper 8 bits of data of the pixels B, C, and D. As a result, each pixel A, B,
The light emission image of C and D has a gradation display in which the display minimum level value “1” is added to the pixels B and D as shown in FIG. Thus, the gradation display is such that half of the display minimum level value “1” is added. Thereby, the difference in data between the pixels A and C and the pixels B and D can be reduced.

When the combination of the lower two bits of the 10-bit data is "10" and "00", the pixels A and C are in the odd field as shown in FIG. 5 (d-1). , D, the display minimum level value “1” is added to the data, and in the case of an even field, the pixels A, B, C are added as shown in FIG.
Display minimum level value "1" for each upper 8-bit data
May be added. As a result, the light emission image of each of the pixels A, B, C, and D is as shown in FIG.
, The minimum display level value “1” for the pixels A and C
Are added, and for the pixels B and D, half the display minimum level value “1” is added. Thereby, pixels A and C and pixels B and D
Between the data can be reduced.

[0034]

As described above, according to the present invention, in an apparatus having a PDP composed of a plurality of unit display areas (pixels), a plurality of unit display areas are provided on a first line among the plurality of unit display areas. The first and second unit display areas (pixels A and B) adjacent to each other and the second line selected next to the first line are provided adjacent to the first and second unit display areas, respectively. When the third and fourth unit display areas (pixels C and D) adjacent to each other are set as a pair of display areas, and analog video signals for the first to fourth unit display areas are input, m ( m is a positive integer)
And converts the converted m-bit digital data into a predetermined n-bit (n is a positive integer) data larger than m and outputs the first to fourth digital data. Of the upper display unit and the lower (n)
-M) bit data, and inputting (nm) bit data for at least the third and fourth unit display areas, calculating an average value, and displaying the first to fourth unit displays. Since the distribution of the predetermined value based on the operation result for the m-bit data for the area is processed differently for the odd field and the even field and output to the PDP as m-bit data, the number of subfields is not increased. The display gradation can be increased, so that P
It is possible to suppress a decrease in the maximum luminance of the DP, reduce image quality deterioration such as a false contour of a moving image, and secure a gradation display with a good S / N ratio.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a PDP device to which the present invention has been applied.

FIG. 2 is a block diagram showing a main configuration of the PDP device.

FIG. 3 is a diagram illustrating a pixel block to be displayed on a PDP.

FIG. 4 is a diagram illustrating an operation of a main part of the PDP device.

FIG. 5 is a diagram illustrating an operation of a main part of the PDP device.

FIG. 6 is a block diagram showing a configuration of a conventional PDP device.

FIG. 7 is a diagram showing an arrangement configuration of subfields used in a PDP device.

[Explanation of symbols]

11: Level adjustment unit, 12: A / D conversion unit, 13: Frame memory, 14: Output processing unit, 15: Synchronization separation unit, 1
6 timing pulse generator 17 memory controller 1
8: drive timing generation unit, 19: γ inverse correction unit, 20:
Tone increasing section, 21 to 25 delay section, 26 to 29 addition section, 30, 31 line delay section, 32 average value calculation section,
33: selector, 100: plasma display panel (PDP), A, B, C, D, a, b, c, d: pixels.

Claims (4)

[Claims] 1. A display device having a plasma display panel comprising a plurality of unit display areas and performing a gradation display of the plasma display panel, wherein the display apparatus is provided on a first line of the plurality of unit display areas. First and second unit display areas adjacent to each other and
The third and fourth unit display areas provided on the second line selected next to the first and second unit display areas and adjacent to the first and second unit display areas, respectively, are set as a pair of display areas. A second step of receiving the analog video signals for the first to fourth unit display areas and converting them into digital data of m (m is a positive integer) bits respectively; A third step of performing a predetermined correction process on the m-bit digital data converted based on the processing of step (b) and outputting the data as n-bit data (n is a positive integer) larger than m; A fourth step of dividing the n-bit data for the fourth to fourth unit display areas into upper m-bit data and lower (nm) bit data, respectively; A fifth step of inputting (nm) bit data for the fourth unit display area and calculating an average value, and a fifth step of m-bit data for the first to fourth unit display areas. A sixth step of allocating a predetermined value based on the operation result for each of the odd and even fields and allocating the odd field and the even field in different allocation patterns; and m based on the processing result of the sixth step. A seventh step of outputting bit data to the plasma display panel to perform a gray scale display. 2. The processing according to claim 1, wherein the processing in the sixth step is such that when the operation result in the fifth step is a first value, the m-bit data for the first to fourth unit display areas is converted into a value. "1" is distributed, and when the operation result is the second value, m for the first to third unit display areas is used in the odd field.
A value "1" is allocated to the bit data, and a value "1" is allocated to the m-bit data for the second to fourth unit display areas in the even field, and when the operation result is the third value, the odd field is allocated. In the example, the value “1” is allocated to the m-bit data for the first and fourth unit display areas, and the value “1” is allocated to the m-bit data for the second and third unit display areas in the even field. When the operation result is the fourth value, the value "1" is distributed to m-bit data for the second unit display area in the odd field, and to the m-bit data for the third unit display area in the even field. A gradation display processing method for a plasma display panel, comprising a process of allocating a value “1”. 3. The gray scale of a plasma display panel according to claim 1, wherein the processing of the sixth step is performed by dividing the pair of display areas by one line in an odd field and an even field. Display processing method. 4. The method according to claim 1, wherein the process in the fifth step includes a process of inputting (nm) bit data for the first to fourth unit display areas and calculating an average value. And a gradation display processing method for a plasma display panel.