KR20020017273A - Method of fabricating a semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming a semiconductor device is provided to form a capacitor suitable for a radio frequency operation in which capacitance is increased, by forming a sub layer on a substrate such that the sub layer geometrically transforms the shape of a lower electrode. CONSTITUTION: A pre-metal insulation layer(31) is formed on the semiconductor substrate(30). An etch stop layer(32) and the sub layer(33) are sequentially formed on the pre-metal insulation layer. A predetermined portion of the sub layer is removed to form a groove. The lower electrode(340) is formed on the inner surface of the groove and on the sub layer extending from the groove wherein a space is left in the groove. A dielectric layer(35) is formed on the sub layer including the exposed surface of the lower electrode. An upper electrode(360) is so formed on the dielectric layer that an overlap area of the lower electrode and the upper electrode is maximized and the upper electrode does not overlap a partial surface of the lower electrode.

Description

Method of fabricating a semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to form a sublayer on a substrate and to remove a predetermined portion of the sublayer, thereby providing a lower electrode forming portion that geometrically bends the pattern of the lower electrode on the same layout area. The present invention relates to a method of manufacturing a capacitor of a semi-assembly device in which the surface area of the lower electrode on which the dielectric film is to be formed is maximized so as to be suitable for high frequency operation while maximizing the capacitance of the capacitor.

The MIM (metal-insulator-metal) capacitors used in the analog circuits of various graphics and multimedia devices, which occupy most of the merged DRAM and logic (MDL) devices, provide high capacitance with small series resistance and low thermal budget. Thermal budgets are widely used because of the high integration of the process.

MIM capacitors have low VCC and high precision mismatching characteristics compared to conventional polysilicon-insulator-polysilicon (PIP) capacitors. That is, the MIM capacitor is an analog capacitor and is formed of a metal having a high Q factor, almost no depletion as an electrode, and low resistance such as tungsten.

1 is a cross-sectional view of a polysilicon-insulator-polysilicon (PIP) capacitor of a semiconductor device according to the prior art.

Referring to FIG. 1, an insulating film 11 is formed on a silicon substrate 10, and a lower electrode 12 made of polysilicon doped on the insulating film 11 is patterned in a predetermined shape. In this case, the insulating film 11 may be a field oxide film.

On the surface of the lower electrode 12, a dielectric film 13 made of an oxide-nitride-oxide (ONO) film or an inter-polysilicon layer (IPO) film is formed. Since the dielectric film 13 has a high dielectric constant value, it is possible to secure necessary capacitance even in a small area.

Next, a capacitor having a PIP structure is completed by polysilicon doped with the upper electrode 14 covering the upper surface and one side surface of the dielectric film 13 and extending to the upper surface of the insulating film 11.

However, a capacitor having such a structure is advantageous in securing capacitance but is not easy to use due to the resistance of polysilicon in a device requiring high frequency operation.

2 is a cross-sectional view of a metal-insulator-metal capacitor (MIM) of a semiconductor device according to the prior art.

Referring to FIG. 2, an insulating film 21 is formed on the silicon substrate 20, and a lower electrode 22 made of a metal such as tungsten is patterned on the insulating film 21 in a predetermined shape. In this case, the insulating film 21 may be a field oxide film.

On the surface of the lower electrode 22, a dielectric film 23 having a thickness thicker than that of an oxide-nitride-oxide (ONO) film or an inter-polysilicon layer (IPO) film is formed on the surface of the MIM structure. However, the dielectric film 23 is thick, making it difficult to secure necessary capacitance.

Next, the upper electrode 24 covering the upper surface and one side surface of the dielectric film 23 and extending to the upper surface of the insulating film 21 is made of a metal material such as tungsten to complete the capacitor of the MIM structure.

However, capacitors having such a structure are advantageous in devices requiring high frequency operation, but are disadvantageous due to the thick dielectric film for securing capacitance.

As described above, in the prior art, PIP structure capacitors are disadvantageous in high frequency operation, and MIM structure capacitors have difficulty in securing required capacitance.

Accordingly, an object of the present invention is to provide a lower electrode forming portion which forms an auxiliary layer on a substrate and removes a predetermined portion of the auxiliary layer to geometrically bend the pattern of the lower electrode, thereby providing a lower electrode forming portion on the same layout area. The present invention provides a method of manufacturing a capacitor of a semi-assembly device that maximizes the surface area and maximizes the capacitance of the capacitor and is suitable for high frequency operation.

A semiconductor device manufacturing method according to the present invention for achieving the above object is a first step of sequentially forming an etch stop layer and an auxiliary layer on the premetal insulating layer of a semiconductor substrate having a premetal insulating layer formed thereon, and the auxiliary A second step of removing a predetermined portion of the layer to form a groove, a third step of forming a lower electrode on the inner surface of the groove and the auxiliary layer extending from the groove, but leaving a space in the groove; Forming a dielectric film on the auxiliary film including the lower electrode surface; and placing an upper electrode on the dielectric film so that an overlapping area with the lower electrode is maximized and does not overlap with a part of the lower electrode surface. Forming a fifth step. Preferably, the width of the groove is formed to be at least twice the thickness of the lower electrode.

1 is a cross-sectional view of a polysilicon-insulator-polysilicon (PIP) capacitor of a semiconductor device according to the prior art

2 is a cross-sectional view of a metal-insulator-metal capacitor of a semiconductor device according to the related art.

3A to 3C are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to the present invention.

4 is a capacitor layout of a semiconductor device according to the present invention.

MIM capacitors are manufactured from metals such as tungsten, which have a high quality factor as an analog capacitor, have little depletion as electrodes, and low resistance. However, it is difficult to increase the capacitance of the MIM structure due to the limitation of the dielectric film material selection and the shape of the lower electrode having the planar structure.

In the present invention, a capacitor suitable for high-frequency operation is manufactured while increasing capacitance by forming an auxiliary film that geometrically deforms the shape of a lower electrode on a substrate.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3A to 3C are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to the present invention, and the layout of FIG. 4 is taken along the cutting line I-I '.

Referring to FIG. 3A, a premetal insulating layer 31 for insulation is formed on a silicon substrate 30, which is a semiconductor substrate, and then a thin etch stop layer 32 is formed of a nitride film or undoped polysilicon. Next, an oxide layer is deposited on the etch stop layer 32 to form an auxiliary layer 33. In this case, the premetal insulating layer 31 may be a field oxide film for device isolation. In addition, the auxiliary layer 33 is formed to provide a portion where a frame for forming the shape of the lower electrode is to be geometrically refracted.

Then, a photoresist is applied on an auxiliary layer made of an oxide film, followed by exposure and development to form a photoresist pattern (not shown) exposing the lower electrode formation region of the capacitor.

The auxiliary layer not protected by the photoresist pattern is etched to form the grooves H. At this time, the lower electrode is formed in the subsequent process to expose the surface of the etch stop layer 32 and the groove H formed in the remaining auxiliary layer 33 and the upper surface of the auxiliary layer 33 extending from the groove.

After removing the photoresist pattern by a method such as oxygen ashing (O ₂ ashing), the first metal layer 34 is formed on the surface of the auxiliary layer 33 exposed to a thickness not completely filling the grooves H. At this time, the first metal layer 34 becomes the lower electrode material of the capacitor, and in the embodiment of the present invention, the first metal layer may be formed by depositing tungsten by sputtering.

Referring to FIG. 3B, the first metal layer is patterned and remains such that the first metal layer remains only in the groove and the upper surface of the auxiliary layer 33 extending from the groove, using the upper surface of the remaining auxiliary layer 33 as the etching end point. The lower electrode 340 formed of the first metal layer is formed. Therefore, since the lower electrode 340 is formed of the first metal layer 340 remaining over the inner surface of the groove and the upper surface of the auxiliary layer 33, the surface area of the groove that is actually exposed without increasing the area on the layout is conducted. Will increase.

At this time, the patterning of the first metal layer is performed by photolithography using anisotropic etching.

The dielectric layer 35 is formed on the auxiliary layer 33 including the exposed lower electrode 340 to have a predetermined thickness.

The second metal layer 36 for forming an upper electrode is formed on the dielectric layer 35. In this case, the second metal layer 36 may be formed by depositing tungsten by sputtering.

Referring to FIG. 3C, after the photoresist is coated on the second metal layer, exposure and development are performed to form a photoresist pattern (not shown) defining the upper electrode formation region. In this case, the photoresist pattern is formed to have a large area overlapping the layout with the lower electrode 360.

Then, the second metal layer of the portion not protected by the photoresist pattern is removed by anisotropic etching to simultaneously form the upper electrode 360 made of the remaining second metal layer. Then, the photoresist pattern is removed by a method such as oxygen ashing.

Therefore, since the lower electrode 340 and the upper electrode 360 interpose the dielectric film 35 and the corresponding area is significantly increased as compared with the related art, the capacitance of the MIM structure is increased and the high frequency operation is realized. do.

4 is a capacitor layout of a semiconductor device according to the present invention.

Referring to FIG. 4, an auxiliary layer 33 having grooves H formed thereon is formed on a silicon substrate 30, and a lower electrode 340 made of a tungsten metal is formed in a quadrangular shape on the silicon substrate 30.

In addition, the upper electrode 360 is also formed in a rectangular shape so that the area overlapping with the lower electrode 340 is maximized.

Although not shown, a dielectric film is interposed between the lower electrode 340 and the upper electrode 360.

Accordingly, the present invention has an advantage of manufacturing a capacitor suitable for high frequency operation while increasing capacitance in a method of forming an auxiliary film that geometrically deforms the shape of a lower electrode on a substrate.

Claims (5)

A first step of sequentially forming an etch stop layer and an auxiliary layer on the premetal insulating layer of the semiconductor substrate on which the premetal insulating layer is formed; A second step of forming a groove by removing a predetermined portion of the auxiliary layer; Forming a lower electrode on the inner surface of the groove and the auxiliary layer extending from the groove, but leaving a free space in the groove; Forming a dielectric layer on the auxiliary layer including the exposed lower electrode surface; And forming an upper electrode on the dielectric layer so as to have a maximum overlapping area with the lower electrode and not overlap with a part of the surface of the lower electrode. The method according to claim 1, And the lower electrode and the lower electrode are formed of tungsten. The method according to claim 1, And the premetal insulating layer is a device insulating field insulating film. The method according to claim 1, And the etch stop layer is formed by selecting any one of a nitride film and an undoped polysilicon and the auxiliary film is formed of an oxide film. The method according to claim 1, And the width of the groove is formed to be at least twice the thickness of the lower electrode.