KR20020013255A - Array Panel used for a Liquid Crystal Display and method for fabricating the same - Google Patents

Abstract

PURPOSE: An array panel for an LCD(Liquid Crystal Display) is provided to prevent the defect in opening by forming a data link for connecting a data line with a data pad, to inhibit galvanic corrosion by forming the sectional structure of the data pad with a gate insulating film and a data pad electrode, and to improve the yield rate of products by forming the data pad electrode with ITO(Indium Tin Oxide). CONSTITUTION: An array panel(100) consists of a substrate; a gate line(110) and a data line(130) crossing each other on the substrate; a TFT(Thin Film Transistor) connected with the gate line and the data line; a pixel electrode(128) made of ITO and positioned at an area defined by the crossing of the gate line and the data line; and a data pad(150) positioned at the tip of the data line, made of the same material as the gate line on the substrate, including a data pad(113) having first and second contact holes(122,124), an insulating film, a first pad electrode of ITO for connecting the first contact hole with the data line, and a second pad electrode of ITO for connecting the second contact hole with an external circuit. The pixel electrode is made of ITO having a low contact resistance value in tap bonding. Therefore, the process is simplified and the reject rate of products is reduced.

Description

Array panel used for a Liquid Crystal Display and method for fabricating the same}

The present invention relates to an array panel for a liquid crystal display device, and more particularly, to an array panel for a liquid crystal display device having a data pad part structure capable of preventing erosion and open defects that are likely to occur in the data pad part and a manufacturing method thereof. .

The driving principle of the liquid crystal display device is to use the optical anisotropy and polarization property of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Accordingly, when the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal due to optical anisotropy to express image information.

Currently, active matrix LCDs (AM-LCDs) in which thin film transistors (TFTs) and pixel electrodes connected to the thin film transistors are arranged in a matrix manner have the highest resolution and moving picture performance. I am getting it.

In general, the structure of a liquid crystal panel, which is a basic component of a liquid crystal display, is as follows.

1 is an exploded perspective view schematically illustrating a general liquid crystal display device.

As shown in the drawing, a general liquid crystal display includes a color filter 8 including a black matrix 6 and a sub color filter (red, green, blue) 4 and an upper portion on which a transparent common electrode 10 is formed on the color filter. A substrate 2, a pixel region P and a lower substrate 14 having an array wiring including a switching element and a pixel electrode 12 formed on the pixel region, the upper substrate 2 and the lower substrate ( The liquid crystal 16 is filled between the 14.

The lower substrate 14 is also referred to as an array panel, and the thin film transistor T, which is a switching element, is positioned in a matrix type, and the gate wiring 18 and the data wiring 20 passing through the plurality of thin film transistors cross each other. Is formed.

The pixel area P is an area defined by the gate wiring 18 and the data wiring 20 intersecting with each other.

In the liquid crystal display device configured as described above, the liquid crystal layer 16 positioned on the pixel electrode 12 is oriented by a signal applied from the thin film transistor T, and the liquid crystal layer is aligned according to the degree of alignment of the liquid crystal layer. The image can be represented in a manner that controls the amount of light that passes through layer 16.

FIG. 2 is a plan view showing a plane corresponding to one pixel portion of a lower array panel for a general liquid crystal display device. In particular, the structure of the data pad portion of the lower array panel will be described.

As illustrated, a general liquid crystal display device has a gate wiring 18 including a gate electrode 22 formed in a horizontal direction, and intersects with the gate wiring 18 so that the source and drain electrodes 30, 32 is connected to the data line 20, and at the end of the data line 20, a printed circuit board (PCB) having a predetermined area and a data pad part 34 having tab bonding are formed. Formed.

In addition, the pixel electrode 38 is formed in an area where the gate line 18 and the data line 20 cross each other.

The data pad 34 includes a data pad electrode 39 made of a pixel electrode material in contact with the metal material of the data line 20 through the data pad contact hole 36.

The data pad 34 is located at the end of the data line, and if an open defect occurs in the data pad 34, a signal is not applied to the data lines of the same row, resulting in a product defect.

The arrow II represents the data pad part 34 of the lower array panel exposed to the outside after the upper and lower panels are bonded to each other. The data pad part 34 is exposed to the outside to form tab bonding in the standby state. Therefore, there is a fear that erosion may occur in a high temperature and high humidity environment.

3 is a cross-sectional view illustrating a cross section taken along a cutting line A-A 'of FIG. 2.

That is, the problem of the structure of the conventional data pad unit will be described with reference to the cross-sectional view.

As shown, a metal gate electrode 22 is formed on the substrate 1, and the gate insulating film 24, the intrinsic semiconductor layer 26a, and the ohmic contact layer 26b are formed on the gate electrode 22. On the semiconductor layer 26 including the intrinsic semiconductor layer 26a and the ohmic contact layer 26b, metal source and drain electrodes 30 and 32 are formed, and the source and drain electrodes ( A protective layer 34 is formed on the 30 and 32 and the data line 20. In the pixel portion P and the data pad portion 34, the protective layer 34 is etched from the protective layer 34 to the semiconductor layer 26 at once. The insulating layer 26 is exposed, and a pixel electrode 38 and a data pad electrode 39 made of a transparent conductive material are formed on the exposed gate insulating layer 24.

The liquid crystal display device is a cross-sectional view of a lower array panel for a liquid crystal display device according to a general four mask process. The data pad portion 34 includes a data pad contact hole having a data pad electrode 39 formed with tab bonding. 36, wherein the data pad contact hole 36 is etched from the protective layer 34 to the semiconductor layer 26 at one time by the nature of the four mask process, thereby the data pad contact hole 36 and the data pad. A high step is achieved between the sections 34.

The drawing in the circle shown in FIG. II shows enlarged side contact defects that may occur when the data pad electrode 39 is formed in the data pad contact hole 36.

That is, as the data pad contact hole 36 achieves a high step, the C pad is deposited in the C portion in the process of bringing the data pad electrode 39 and the gate insulating layer 24 into contact with each other through the data pad contact hole 36. This is not done well, the open failure between the data line 20 metal and the data pad electrode 39 made of a transparent conductive material.

The open failure of the data pad 34 causes a signal application failure in the data line 20, and the result leads to a product defect.

In the circle shown in III, the end portion of the data pad portion 34 is enlarged. In this case, the data pad electrode 39 and the data line 20 exposed to the end side of the data pad portion 34 are made of metal material. When voltage is applied in a high-temperature, high-humidity environment, the moisture covers the data pad electrode 39 and the data wiring 20 metal material and floats electricity in the direction of the arrow G, thereby causing galvanic corrosion between the metals. 34) Erosion may occur at the tip.

In the conventional liquid crystal display, IZ0 is used as the material of the data pad electrode 39 formed in the data pad contact hole 36. In the tap bonding of the IZO, the resistance value is 20.0 to 200 Ω, and is about 1.5 to 3.8. Compared to ITO having a resistance value of Ω, the tap bonding resistance value is much higher, which may cause contact failure when tap bonding.

In order to solve the above problems, in the present invention, the cross-sectional structure of the data pad contact hole is formed of a gate metal, a gate insulating film, and a pixel electrode material, thereby reducing the step difference, and forming and opening a data link part connecting the data pad part and the data wire. The cross-sectional structure of the end of the data pad part is prevented from defects, and the gate insulating film and the data pad electrode can be used to prevent galvanic corrosion. The data pad electrode has ITO with low contact resistance during tap bonding. An object of the present invention is to provide a data pad structure of a liquid crystal display device which can be improved.

1 is an exploded perspective view showing a general liquid crystal display device.

2 is a plan view showing a plane corresponding to one pixel portion of a general array panel for a liquid crystal display device;

3 is a cross-sectional view taken along the line A-A 'of FIG. 2;

4 is a plan view showing a cross section corresponding to one pixel portion of an array panel for a liquid crystal display device according to the present invention;

Figures 5a to 5d is a cross-sectional view showing the manufacturing process step according to the cutting line B-B 'of FIG.

<Description of Symbols for Main Parts of Drawings>

100: lower array panel 110: gate wiring

112: gate electrode 113: data pad

118 source electrode 120 drain electrode

122: data link contact hole 124: data pad contact hole

128: pixel electrode 130: data wiring

140: data link unit 150: data pad unit

In order to achieve the above object, in one aspect of the present invention; Gate wiring and data wiring crossing each other on the substrate; A thin film transistor connected to the gate line and the data line; A pixel electrode of ITO material positioned in an area defined by crossing the gate wiring and the data wiring; Located at the end of the data line, and has a data pad of the same material as the gate line on the substrate, formed on the same layer, the first contact hole and the second contact hole on the data pad, the front surface of the substrate An insulating film formed on the insulating film, a first pad electrode formed on the insulating film and connecting the data line and the first contact hole, and a second pad electrode made of ITO connecting the second contact hole and an external circuit. Provided are an array panel for a liquid crystal display device including a data pad portion having a portion thereof.

The edge of the second pad electrode in the data line length direction of the data pad part may include the insulating layer directly contacting the substrate, and the insulating layer may further include a third contact hole. And a contact with the data pad through a second contact hole and the third contact hole.

In still another aspect of the present invention, there is provided a method of preparing a substrate; Forming a gate line and a data pad on the substrate using the same metal material; Stacking an insulating film, a semiconductor layer, a metal layer, and a protective layer on the substrate on which the gate wiring is formed; Forming a thin film transistor connected to the data line crossing the gate line and the gate line and the data line; Etching the protective layer, the metal layer, and the semiconductor layer on the data pad and forming first and second contact holes in the insulating film on the data pad; Forming a first pad electrode connecting the pixel electrode, the first contact hole on the data pad and the data line, and a second pad electrode connecting the second contact hole and an external circuit using the ITO material; A method of manufacturing an array panel for a liquid crystal display device is provided.

Before forming the protective layer on the metal layer, forming a channel layer of the thin film transistor and contact holes corresponding to positions of first and second contact holes formed in the insulating layer on the data pad, respectively. And forming the insulating film in direct contact with the substrate at the end edge of the negative second pad electrode in the data wiring length direction.

In the forming of the data pad unit, forming a data third contact hole so that the second pad electrode is connected through the second contact hole and the third contact hole.

It is characterized by including.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

4 is a plan view illustrating a plane corresponding to one pixel part of the liquid crystal display of the present invention.

As shown, the lower array panel of the liquid crystal display device of the present invention (100) is formed with the gate wiring 110 including the gate electrode 112 in the horizontal direction, the source and drain electrodes 118 in the vertical direction The data line 130 is formed simultaneously with the gate line 110 and intersects with the gate line 110.

The data line 130 formed at the same time as the source and drain electrodes 118 and 120 spaced apart from each other is formed on the gate electrode 112.

The pixel electrode 128 is formed in an area where the gate line 110 and the data line 130 cross each other.

The data link unit 140 and the data pad unit 150 having a predetermined area are formed at the ends of the data line 130.

The data line 130 is connected to the data pad unit 150 through the data link unit 140, and a data pad made of a gate metal material under the data link unit 140 and the data pad unit 150. 113 is formed.

The data hole 113 and the contact hole under the data link unit 140 are electrically connected to the contact hole 122 of the data link unit 140 to electrically connect the data line 130 and the data pad unit 150. A data link unit electrode 142 made of a pixel electrode material is formed to contact the through 122.

That is, the data pad 113 of the data pad unit 150 is formed up to the data link unit 140, and the data pad contact hole 124 and the data link unit contact hole 140 are formed in plurality to form a data line. The contact area between the 130 and the data pad unit 150 and the tab bonding area of the data pad unit 150 may be increased.

In addition, since the data link part electrode 142 and the data pad electrode 152 are made of the same transparent conductive material as the pixel electrode 128, the transparent conductive material is preferably made of ITO having low contact resistance when tapped. Do.

5A through 5D are cross-sectional views illustrating a manufacturing process according to the cutting line BB ′ of FIG. 4, and the present disclosure discloses a lower array panel for a liquid crystal display device using a four mask process.

In FIG. 5A, a metal material such as Cr or Al is deposited on the transparent substrate 1 and then patterned by a first mask process to form the gate electrode 112 and the data pad 113.

In FIG. 5B, an insulating material such as silicon nitride (SiNx) is deposited on the gate electrode 112 to form a gate insulating film 114, and an intrinsic semiconductor layer such as amorphous silicon is continuously formed on the gate insulating film 114. After depositing 116a and an amorphous semiconductor layer 116b such as n + amorphous silicon, the semiconductor layer 116 including the intrinsic semiconductor layer 116a and the impurity semiconductor layer 116b is subjected to a separate patterning process. An opaque metal material such as Mo is formed on the semiconductor layer 116 to etch the Mo metal and the impurity semiconductor layer 116a in the thin film transistor unit T, the data link unit 140 and the data pad unit 150. The source and drain electrodes 118 and 120 are formed, and the first contact hole 122a and the data pad first contact hole 124a of the data link unit are formed.

In the manufacturing process step, forming the primary contact holes 122a and 124a in the data link unit 140 and the data pad unit 150 may include the data link unit 140 and the data pad unit in the next mask process. This is to adjust the etching ratio so that the data pad 113 made of the gate electrode material is exposed through the contact hole of 150.

In FIG. 5C, after the passivation layer 126 is formed over the substrate on which the source and drain electrodes 118 and 120 are formed, the pixel portion region P, the data link portion 140, and the data pad portion 150 are formed. Etching the protective layers 126 to the semiconductor layer 116 at once is performed.

In this case, the gate insulating layer 114 is exposed in the pixel portion region P through the patterning of the protective layer 126, and the same etching as the pixel portion region P is performed in the data link portion and the pad portions 140 and 150. The data link second contact hole and the data pad second contact holes 122b and 124b are disposed at positions corresponding to the first contact hole 122a of the data link unit and the first contact hole 124a of the data pad unit, respectively. In forming, the data pad 113 is exposed through the contact holes 122b and 124b.

That is, a pattern of the data wire part D, the data link part 140, and the data pad part 150 is formed through the mask process.

In FIG. 5D, the pixel electrode, the data link unit electrode, and the data pad electrode are formed on the lower array panel.

That is, the transparent conductive material is deposited on the entire bottom array panel through the step of FIG. 5C to form the pixel electrode 128, the data link unit electrode 142, and the data pad electrode 152.

In this case, the transparent conductive material is preferably made of indium tin oxide (ITO) having a low contact resistance during tab bonding of the data pad part.

In addition, the pixel electrode 128 is in side contact at the stepped portion between the drain electrode 120, the drain electrode 120, and the pixel portion without forming a drain contact hole.

In addition, the data line part D having a structure stacked in order from the gate insulating layer 114 to the protective layer 126 is the data link part 140 and the data by the data link electrode 142 made of a transparent conductive material. In the stepped portion of the wiring unit D, the data line 130 and the data link unit electrode 142 are in side contact with each other to be in electrical communication.

In addition, the data link electrode 142 contacts the lower data pad 113 through the data link part contact hole 122 as well as the side contact with the data line 130. It is electrically connected.

In addition, the data pad electrode 152 in contact with the data pad 113 through the data pad contact hole 124 applies a data signal through tab bonding.

In the cross-sectional structure of the end of the data pad unit 150 of the original circle denoted by V, the data pad 113 is not formed to the end of the data pad unit 150, and the gate insulating layer 114 is the data pad unit 150. Since only the insulator material and the conductive material covering the ends are formed, it is possible to prevent erosion due to galvanic corrosion generated at the ends of the data pad part 150 by moisture even in a high temperature and high humidity atmosphere.

In addition, since only the gate insulating layer 114 forms a step between the data pad contact hole 124 and the data pad part 150, the open defect may be reduced by lowering the step gap of the contact hole as compared with the conventional pad. Since the electrode 152 and the data pad 113 make horizontal contact, the problem of contact failure may be solved, and the possibility of electrical contact failure caused by foreign substances being caught through the contact hole during the process may be reduced.

Up to now, the present invention solves the problem of the data pad part of the conventional four-mask thin film transistor liquid crystal display device, while utilizing the advantages of the process simplification and manufacturing cost, which are advantages of the four mask process, and also the galvanic phenomenon and the open defect problem of the data pad part. In order to solve the problem, and to lower the contact resistance during the tab bonding with the PCB of the data pad part, in particular, ITO is used as the data pad electrode material.

What has been described above is only one embodiment for implementing the data pad structure of the liquid crystal display device according to the present invention, and the present invention is not limited to the above-described embodiment, as claimed in the following claims. Without departing from the gist of the present invention, anyone of ordinary skill in the art will have the technical spirit of the present invention to the extent that various modifications can be made.

As described above, according to the structure of the data pad portion of the liquid crystal display device according to the present invention, the step of lowering the data pad portion can eliminate the problem of open defects and poor contact, and the cross-sectional structure of the end of the data pad portion can be replaced by a gate insulating film / By using the pixel electrode material, erosion at the end of the data pad portion can be prevented. The pixel electrode material is made of ITO having a low contact resistance value at the time of tab bonding, thereby simplifying the process, making the process safer and preventing product defects. It can be.

Claims (7)

A substrate; Gate wiring and data wiring crossing each other on the substrate; A thin film transistor connected to the gate line and the data line; A pixel electrode of ITO material positioned in an area defined by crossing the gate wiring and the data wiring; Located at the end of the data line, and has a data pad of the same material as the gate line on the substrate, formed on the same layer, the first contact hole and the second contact hole on the data pad, the front surface of the substrate An insulating film formed on the insulating film, a first pad electrode formed on the insulating film and connecting the data line and the first contact hole, and a second pad electrode made of ITO connecting the second contact hole and an external circuit. Data pad section Array panel for a liquid crystal display device comprising a. The method of claim 1, And an end edge of the second pad electrode in the data pad portion in the data wiring length direction, wherein the insulating film directly contacts the substrate. The method of claim 1, The insulating layer further includes a third contact hole, wherein the second pad electrode is in contact with the data pad through the second contact hole and the third contact hole. Preparing a substrate; Forming a gate line and a data pad on the substrate using the same metal material; Stacking an insulating film, a semiconductor layer, a metal layer, and a protective layer on the substrate on which the gate wiring is formed; Forming a thin film transistor connected to the data line crossing the gate line and the gate line and the data line; Etching the protective layer, the metal layer, and the semiconductor layer on the data pad and forming first and second contact holes in the insulating film on the data pad; Forming a first pad electrode connecting the pixel electrode, the first contact hole on the data pad and the data line, and a second pad electrode connecting the second contact hole and an external circuit using the ITO material; Method of manufacturing an array panel for a liquid crystal display device comprising a. The method of claim 4, wherein And forming contact holes corresponding to positions of the first and second contact holes formed in the channel layer of the thin film transistor and the insulating layer on the data pad, respectively, before the protective layer is deposited on the metal layer. Method of manufacturing an array panel. The method of claim 4, wherein And forming the insulating film in direct contact with the substrate at the end edge of the second pad electrode in the data pad portion in the data wiring length direction. The method of claim 4, wherein In the forming of the data pad part, forming a data third contact hole so that the second pad electrode is connected through the second contact hole and the third contact hole. Method of manufacturing an array panel for a liquid crystal display device comprising.