KR20020002083A - Method for manufacturing a fero-dielectric capacitor - Google Patents

Method for manufacturing a fero-dielectric capacitor Download PDF

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KR20020002083A
KR20020002083A KR1020000036524A KR20000036524A KR20020002083A KR 20020002083 A KR20020002083 A KR 20020002083A KR 1020000036524 A KR1020000036524 A KR 1020000036524A KR 20000036524 A KR20000036524 A KR 20000036524A KR 20020002083 A KR20020002083 A KR 20020002083A
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platinum
alloy
lower electrode
manufacturing
ferroelectric
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KR1020000036524A
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Korean (ko)
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장혁규
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박종섭
주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE: A method for manufacturing a ferroelectric capacitor is provided to prevent a lower electrode from being oxidized by using an alloy of Pt and Ru or an alloy of Pt and Ir to form the lower electrode, and to shorten process time by more easily performing an etch process for forming a pattern than performing a process for forming the lower electrode while using RuO2 or IrO2. CONSTITUTION: An alloy(13) including Pt(15) is evaporated on a semiconductor substrate(11) having an insulation layer(12) to form the lower electrode. A ferroelectric layer is formed on the lower electrode. Pt is evaporated on the ferroelectric layer to form an upper electrode.

Description

강유전체 캐패시터의 제조 방법 {Method for manufacturing a fero-dielectric capacitor}Method for manufacturing a ferroelectric capacitor {Method for manufacturing a fero-dielectric capacitor}

본 발명은 강유전체 캐패시터의 제조 방법에 관한 것으로, 특히, 산소(O2) 원자의 확산에 의한 하부전극의 산화가 방지되도록 한 강유전체 캐패시터의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a ferroelectric capacitor, and more particularly, to a method of manufacturing a ferroelectric capacitor in which oxidation of a lower electrode due to diffusion of oxygen (O 2 ) atoms is prevented.

일반적으로 FeRAM과 같은 메모리 소자는 캐패시터(Capacitor)에 정보가 저장되도록 구성된다. 이러한 캐패시터는 하부전극, 강유전체 및 상부전극이 적층된 구조로 이루어지며, 하부전극 및 상부전극은 절연막에 형성된 콘택홀(Contact Hole)을 통해 캐패시터의 상부에 형성되는 금속배선과 연결된다.In general, a memory device such as FeRAM is configured to store information in a capacitor. The capacitor has a structure in which a lower electrode, a ferroelectric, and an upper electrode are stacked, and the lower electrode and the upper electrode are connected to a metal wiring formed on the capacitor through a contact hole formed in the insulating film.

종래에는 도 1에 도시된 바와 같이 절연막(2)이 형성된 반도체 기판(1)상에 백금(Pt)(3)을 증착하여 하부전극을 형성한 후 상기 하부전극상에 PZT[Pb(Zr, Ti)O3], SBT[Sr(Bi, Ta)O3] 등과 같은 강유전체(4)를 증착하고 상기 강유전체(4)상에 백금(Pt)(5)을 증착하여 상부전극을 형성한다. 이때, 상기 백금(Pt)대신 산화 루데늄(RuO2), 산화 이리듐(IrO2) 등을 이용하여 하부 및 상부전극을 형성할 수 있다.Conventionally, as shown in FIG. 1, platinum (Pt) 3 is deposited on a semiconductor substrate 1 on which an insulating film 2 is formed to form a lower electrode, and then PZT [Pb (Zr, Ti) on the lower electrode. A ferroelectric 4 such as) O 3 ], SBT [Sr (Bi, Ta) O 3 ], etc. is deposited and platinum (Pt) 5 is deposited on the ferroelectric 4 to form an upper electrode. In this case, the lower and upper electrodes may be formed using ruthenium oxide (RuO 2 ), iridium oxide (IrO 2 ), or the like instead of platinum (Pt).

그런데 상기와 같이 하부전극을 백금(Pt)으로 형성하면 후속으로 실시되는 열처리 과정에서 산소(O2) 원자의 확산에 의해 하부전극의 산화가 유발된다. 또한, 산화 루데늄(RuO2) 또는 산화 이리듐(IrO2)을 이용하여 상기 하부전극을 형성하면 패턴을 형성하기 위한 식각 공정의 진행이 어려워진다.However, when the lower electrode is formed of platinum (Pt) as described above, oxidation of the lower electrode is caused by diffusion of oxygen (O 2 ) atoms in a subsequent heat treatment process. In addition, when the lower electrode is formed using ruthenium oxide (RuO 2 ) or iridium oxide (IrO 2 ), the etching process for forming the pattern becomes difficult.

따라서 하부전극의 산화로 인한 불량이 방지되며, 패턴의 형성이 용이한 새로운 공정기술의 개발이 요구된다.Therefore, a defect due to oxidation of the lower electrode is prevented, and development of a new process technology that is easy to form a pattern is required.

따라서 본 발명은 백금(Pt)이 포함된 합금을 이용하여 하부전극을 형성하므로써 상기한 단점을 해소할 수 있는 강유전체 캐패시터의 제조 방법을 제공하는 데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a ferroelectric capacitor that can solve the above disadvantages by forming a lower electrode using an alloy containing platinum (Pt).

도 1은 종래 강유전체 캐패시터의 제조 방법을 설명하기 위한 소자의 단면도.1 is a cross-sectional view of a device for explaining a method of manufacturing a conventional ferroelectric capacitor.

도 2는 본 발명에 따른 강유전체 캐패시터의 제조 방법을 설명하기 위한 소자의 단면도.2 is a cross-sectional view of a device for explaining a method of manufacturing a ferroelectric capacitor according to the present invention.

도 3은 증착 두께의 변화에 따른 밀도의 변화를 AES(Auger Electron Spectroscopy) 분석을 통해 도시한 그래프도.3 is a graph showing a change in density according to a change in deposition thickness through AES (Auger Electron Spectroscopy) analysis.

도 4는 투과 현미경(TEM)을 이용하여 관찰한 합금층의 단면도.4 is a cross-sectional view of the alloy layer observed using a transmission microscope (TEM).

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

1 및 11: 반도체 기판 2 및 12: 절연막1 and 11: semiconductor substrates 2 and 12: insulating film

3: 백금 4 및 14: 강유전체3: platinum 4 and 14: ferroelectric

5 및 15: 백금 13: 합금5 and 15: platinum 13: alloy

본 발명에 따른 강유전체 캐패시터의 제조 방법은 절연막이 형성된 반도체 기판상에 백금(Pt)이 포함된 합금을 증착하여 하부전극을 형성하는 단계와, 하부전극상에 강유전체막을 형성하는 단계와, 강유전체막상에 백금(Pt)을 증착하여 상부전극을 형성하는 단계로 이루어진다.A method of manufacturing a ferroelectric capacitor according to the present invention comprises the steps of forming a lower electrode by depositing an alloy containing platinum (Pt) on a semiconductor substrate having an insulating film, forming a ferroelectric film on the lower electrode, and on the ferroelectric film Depositing platinum (Pt) is formed to form an upper electrode.

상기 합금은 백금(Pt)과 루데늄(Ru)의 합금 또는 백금(Pt)과 이리듐(Ir)의 합금이며, 상기 백금(Pt)과 루데늄(Ru)은 95:5 내지 40:60의 비로 조성되며, 상기 백금(Pt)과 이리듐(Ir)은 95:5 내지 40:60의 비로 조성된다.The alloy is an alloy of platinum (Pt) and ruthenium (Ru) or an alloy of platinum (Pt) and iridium (Ir), and the platinum (Pt) and rudennium (Ru) are in a ratio of 95: 5 to 40:60. The platinum (Pt) and iridium (Ir) is formed in a ratio of 95: 5 to 40:60.

그러면 이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Next, the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명에 따른 강유전체 캐패시터의 제조 방법을 설명하기 위한 소자의 단면도이다.2 is a cross-sectional view of a device for explaining a method of manufacturing a ferroelectric capacitor according to the present invention.

절연막(12)이 형성된 반도체 기판(11)상에 백금(Pt)이 포함된 합금(13)을 증착하여 하부전극을 형성한다. 이후 상기 하부전극상에 PZT[Pb(Zr, Ti)O3], SBT[Sr(Bi, Ta)O3] 등과 같은 강유전체(14)를 증착하고 상기 강유전체(14)상에 백금(Pt)(15)을 증착하여 상부전극을 형성한다.The lower electrode is formed by depositing an alloy 13 including platinum Pt on the semiconductor substrate 11 on which the insulating layer 12 is formed. Then, a ferroelectric 14 such as PZT [Pb (Zr, Ti) O 3 ], SBT [Sr (Bi, Ta) O 3 ], etc. is deposited on the lower electrode, and platinum (Pt) ( 15) is deposited to form an upper electrode.

이때, 상기 합금(13)으로는 백금(Pt)과 루데늄(Ru)의 합금 또는 백금(Pt)과 이리듐(Ir)의 합금이 이용되며, 백금(Pt)과 루데늄(Ru) 또는 백금(Pt)의 조성비는 95:5 내지 40:60이 되도록 한다.In this case, an alloy of platinum (Pt) and rudenium (Ru) or an alloy of platinum (Pt) and iridium (Ir) is used as the alloy 13, and platinum (Pt) and rudenium (Ru) or platinum ( The composition ratio of Pt) is set to 95: 5 to 40:60.

상기와 같이 하부전극을 백금(Pt)과 루데늄(Ru)의 합금 또는 백금(Pt)과 이리듐(Ir)의 합금으로 형성하므로써 후속으로 실시되는 열처리 과정에서 산소(O2) 원자의 확산이 방지된다.As described above, the lower electrode is formed of an alloy of platinum (Pt) and ruthenium (Ru) or an alloy of platinum (Pt) and iridium (Ir) to prevent diffusion of oxygen (O 2 ) atoms during a subsequent heat treatment process. do.

본 발명에서는 실시예로서, 산화막(SiO2)이 형성된 실리콘(Si) 기판상에 티타늄 질화막(TiN)을 형성한 후 그 상부에 백금(Pt)과 루데늄(Ru)의 합금층을 형성하고 상기 합금층상에 유전체막으로 이용되는 PZT를 증착하였다.In an embodiment of the present invention, after forming a titanium nitride film (TiN) on a silicon (Si) substrate on which an oxide film (SiO 2 ) is formed, an alloy layer of platinum (Pt) and rudenium (Ru) is formed thereon. PZT used as a dielectric film was deposited on the alloy layer.

이때, 상기 티타늄 질화막(TiN)은 50㎚의 두께로 형성하여 베리어(Barrier)층 역할을 할 수 있도록 하였으며, 상기 합금은 스퍼터링(Co-sputtering) 방법을 이용하여 200㎚의 두께로 증착하였고, 55:45의 조성비를 갖도록 하였다. 또한 상기 PZT는 300㎚의 두께로 형성하였다.In this case, the titanium nitride layer (TiN) was formed to have a thickness of 50 nm to serve as a barrier layer, and the alloy was deposited to a thickness of 200 nm using a sputtering method. It was made to have a composition ratio of: 45. In addition, the PZT was formed to a thickness of 300nm.

실험 결과 도 3에 도시된 바와 같이 상기 합금층과 PZT층의 경계면에서 산소(O2) 원자가 급격히 감소되었다. 도 3은 AES 분석을 통해 증착 두께의 변화에따른 밀도의 변화를 도시한 그래프도이다.As shown in FIG. 3, oxygen (O 2 ) atoms were drastically reduced at the interface between the alloy layer and the PZT layer. 3 is a graph illustrating a change in density according to a change in deposition thickness through AES analysis.

도 4는 상기와 같은 합금층이 형성된 기판에 200㎚ 두께의 PZT층을 형성한 후 650℃의 온도 및 산소(O2) 분위기에서 30분간 열처리한 후 투과 현미경(TEM)을 이용하여 관찰한 단면을 도시하는데, 상기 PZT층과 접촉된 백금(Pt) 및 루데늄(Ru)의 합금이 3층으로 분리된 것을 알 수 있다. EDX 분석을 실시한 결과 약 10㎚ 두께의 백금(pt)층, 약 35㎚ 두께의 산화 루데늄(RuO2)층, 백금(Pt) 및 루데늄(Ru)층으로 밝혀졌다.4 is a cross-sectional view of the PZT layer having a thickness of 200 nm on the substrate on which the alloy layer is formed, followed by heat treatment at 650 ° C. for 30 minutes in an oxygen (O 2 ) atmosphere, and then using a transmission microscope (TEM). To illustrate, it can be seen that the alloy of platinum (Pt) and rudenium (Ru) in contact with the PZT layer is separated into three layers. EDX analysis revealed a platinum (pt) layer about 10 nm thick, a ruthenium oxide (RuO 2) layer about 35 nm thick, and a platinum (Pt) and rudenium (Ru) layer.

상기한 바와 같이 본 발명은 백금(Pt)과 루데늄(Ru)의 합금 또는 백금(Pt)과 이리듐(Ir)의 합금으로 하부전극을 형성하므로써 후속 열처리 과정에서 산소 원자의 침투가 차단되고, 이에 따라 하부전극의 산화가 방지되어 소자의 신뢰성이 향상된다. 또한, 산화 루데늄(RuO2) 또는 산화 이리듐(IrO2)을 사용하여 하부전극을 형성한 경우보다 패턴을 형성하기 위한 식각 공정이 용이하게 실시될 수 있으며, 이에 의해 공정 시간이 단축되어 소자의 수율 향상을 이룰 수 있다.As described above, the present invention forms a lower electrode of an alloy of platinum (Pt) and rudenium (Ru) or an alloy of platinum (Pt) and iridium (Ir), thereby preventing the penetration of oxygen atoms in a subsequent heat treatment process. Accordingly, oxidation of the lower electrode is prevented, thereby improving reliability of the device. In addition, an etching process for forming a pattern may be performed more easily than when the lower electrode is formed using ruthenium oxide (RuO 2 ) or iridium oxide (IrO 2 ), thereby reducing the process time and Yield improvement can be achieved.

Claims (6)

절연막이 형성된 반도체 기판상에 백금(Pt)이 포함된 합금을 증착하여 하부전극을 형성하는 단계와,Depositing an alloy containing platinum (Pt) on the semiconductor substrate on which the insulating film is formed to form a lower electrode; 상기 하부전극상에 강유전체막을 형성하는 단계와,Forming a ferroelectric film on the lower electrode; 상기 강유전체막상에 백금(Pt)을 증착하여 상부전극을 형성하는 단계로 이루어지는 것을 특징으로 하는 강유전체 캐패시터의 제조 방법.And depositing platinum (Pt) on the ferroelectric film to form an upper electrode. 제 1 항에 있어서,The method of claim 1, 상기 합금은 백금(Pt)과 루데늄(Ru)의 합금인 것을 특징으로 하는 강유전체 캐패시터의 제조 방법.The alloy is a method of producing a ferroelectric capacitor, characterized in that the alloy of platinum (Pt) and rudenium (Ru). 제 2 항에 있어서,The method of claim 2, 상기 백금(Pt)과 루데늄(Ru)은 95:5 내지 40:60의 비율로 조성된 것을 특징으로 하는 강유전체 캐패시터의 제조 방법.The platinum (Pt) and rudenium (Ru) is a method of manufacturing a ferroelectric capacitor, characterized in that the composition of the ratio of 95: 5 to 40:60. 제 1 항에 있어서,The method of claim 1, 상기 합금은 백금(Pt)과 이리듐(Ir)의 합금인 것을 특징으로 하는 강유전체 캐패시터의 제조 방법.The alloy is a method of manufacturing a ferroelectric capacitor, characterized in that the alloy of platinum (Pt) and iridium (Ir). 제 4 항에 있어서,The method of claim 4, wherein 상기 백금(Pt)과 이리듐(Ir)은 95:5 내지 40:60의 비율로 조성된 것을 특징으로 하는 강유전체 캐패시터의 제조 방법.Platinum (Pt) and iridium (Ir) is a method of manufacturing a ferroelectric capacitor, characterized in that the composition in the ratio of 95: 5 to 40:60. 제 1 항에 있어서,The method of claim 1, 상기 강유전체는 PZT[Pb(Zr, Ti)O3] 및 SBT[Sr(Bi, Ta)O3]중 어느 하나인 것을 특징으로 하는 강유전체 캐패시터의 제조 방법.Wherein the ferroelectric is any one of PZT [Pb (Zr, Ti) O 3 ] and SBT [Sr (Bi, Ta) O 3 ].
KR1020000036524A 2000-06-29 2000-06-29 Method for manufacturing a fero-dielectric capacitor KR20020002083A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180056030A (en) 2016-11-18 2018-05-28 삼성전기주식회사 Thin film capacitor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180056030A (en) 2016-11-18 2018-05-28 삼성전기주식회사 Thin film capacitor
US10446324B2 (en) 2016-11-18 2019-10-15 Samsung Electro-Mechanics Co., Ltd. Thin film capacitor

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